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Searched refs:ADF_CSR_WR (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/drivers/crypto/qat/qat_common/
Dadf_transport_access_macros.h128 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
135 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
137 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
141 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
144 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
148 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
150 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
154 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
157 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
161 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
Dicp_qat_hal.h103 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
113 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
121 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
123 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
Dadf_accel_devices.h170 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
Dqat_hal.c453 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
/linux-4.1.27/drivers/crypto/qat/qat_dh895xcc/
Dadf_hw_arbiter.c65 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
69 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
73 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
78 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
82 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
87 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
Dadf_dh895xcc_hw_data.c170 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
173 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
180 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
183 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
194 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
196 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
Dadf_admin.c83 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync()
123 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); in adf_init_admin_comms()
124 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); in adf_init_admin_comms()