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Searched refs:ADF_CSR_RD (Results 1 – 6 of 6) sorted by relevance

/linux-4.1.27/drivers/crypto/qat/qat_common/
Dicp_qat_hal.h105 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
114 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
124 #define SRAM_READ(handle, addr) ADF_CSR_RD(handle->hal_sram_addr_v, addr)
Dadf_transport_access_macros.h119 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
122 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
125 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
Dadf_accel_devices.h174 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
Dqat_hal.c447 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
451 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
/linux-4.1.27/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c168 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
171 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
178 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
181 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()
Dadf_admin.c77 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { in adf_put_admin_msg_sync()
87 if (ADF_CSR_RD(mailbox, mb_offset) == 0) { in adf_put_admin_msg_sync()