1 /* 2 * Performance events: 3 * 4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 7 * 8 * Data type definitions, declarations, prototypes. 9 * 10 * Started by: Thomas Gleixner and Ingo Molnar 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 #ifndef _UAPI_LINUX_PERF_EVENT_H 15 #define _UAPI_LINUX_PERF_EVENT_H 16 17 #include <linux/types.h> 18 #include <linux/ioctl.h> 19 #include <asm/byteorder.h> 20 21 /* 22 * User-space ABI bits: 23 */ 24 25 /* 26 * attr.type 27 */ 28 enum perf_type_id { 29 PERF_TYPE_HARDWARE = 0, 30 PERF_TYPE_SOFTWARE = 1, 31 PERF_TYPE_TRACEPOINT = 2, 32 PERF_TYPE_HW_CACHE = 3, 33 PERF_TYPE_RAW = 4, 34 PERF_TYPE_BREAKPOINT = 5, 35 36 PERF_TYPE_MAX, /* non-ABI */ 37 }; 38 39 /* 40 * Generalized performance event event_id types, used by the 41 * attr.event_id parameter of the sys_perf_event_open() 42 * syscall: 43 */ 44 enum perf_hw_id { 45 /* 46 * Common hardware events, generalized by the kernel: 47 */ 48 PERF_COUNT_HW_CPU_CYCLES = 0, 49 PERF_COUNT_HW_INSTRUCTIONS = 1, 50 PERF_COUNT_HW_CACHE_REFERENCES = 2, 51 PERF_COUNT_HW_CACHE_MISSES = 3, 52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 53 PERF_COUNT_HW_BRANCH_MISSES = 5, 54 PERF_COUNT_HW_BUS_CYCLES = 6, 55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 57 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 58 59 PERF_COUNT_HW_MAX, /* non-ABI */ 60 }; 61 62 /* 63 * Generalized hardware cache events: 64 * 65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 66 * { read, write, prefetch } x 67 * { accesses, misses } 68 */ 69 enum perf_hw_cache_id { 70 PERF_COUNT_HW_CACHE_L1D = 0, 71 PERF_COUNT_HW_CACHE_L1I = 1, 72 PERF_COUNT_HW_CACHE_LL = 2, 73 PERF_COUNT_HW_CACHE_DTLB = 3, 74 PERF_COUNT_HW_CACHE_ITLB = 4, 75 PERF_COUNT_HW_CACHE_BPU = 5, 76 PERF_COUNT_HW_CACHE_NODE = 6, 77 78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 79 }; 80 81 enum perf_hw_cache_op_id { 82 PERF_COUNT_HW_CACHE_OP_READ = 0, 83 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 85 86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 87 }; 88 89 enum perf_hw_cache_op_result_id { 90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 92 93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 94 }; 95 96 /* 97 * Special "software" events provided by the kernel, even if the hardware 98 * does not support performance events. These events measure various 99 * physical and sw events of the kernel (and allow the profiling of them as 100 * well): 101 */ 102 enum perf_sw_ids { 103 PERF_COUNT_SW_CPU_CLOCK = 0, 104 PERF_COUNT_SW_TASK_CLOCK = 1, 105 PERF_COUNT_SW_PAGE_FAULTS = 2, 106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 107 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 111 PERF_COUNT_SW_EMULATION_FAULTS = 8, 112 PERF_COUNT_SW_DUMMY = 9, 113 114 PERF_COUNT_SW_MAX, /* non-ABI */ 115 }; 116 117 /* 118 * Bits that can be set in attr.sample_type to request information 119 * in the overflow packets. 120 */ 121 enum perf_event_sample_format { 122 PERF_SAMPLE_IP = 1U << 0, 123 PERF_SAMPLE_TID = 1U << 1, 124 PERF_SAMPLE_TIME = 1U << 2, 125 PERF_SAMPLE_ADDR = 1U << 3, 126 PERF_SAMPLE_READ = 1U << 4, 127 PERF_SAMPLE_CALLCHAIN = 1U << 5, 128 PERF_SAMPLE_ID = 1U << 6, 129 PERF_SAMPLE_CPU = 1U << 7, 130 PERF_SAMPLE_PERIOD = 1U << 8, 131 PERF_SAMPLE_STREAM_ID = 1U << 9, 132 PERF_SAMPLE_RAW = 1U << 10, 133 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 134 PERF_SAMPLE_REGS_USER = 1U << 12, 135 PERF_SAMPLE_STACK_USER = 1U << 13, 136 PERF_SAMPLE_WEIGHT = 1U << 14, 137 PERF_SAMPLE_DATA_SRC = 1U << 15, 138 PERF_SAMPLE_IDENTIFIER = 1U << 16, 139 PERF_SAMPLE_TRANSACTION = 1U << 17, 140 PERF_SAMPLE_REGS_INTR = 1U << 18, 141 142 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */ 143 }; 144 145 /* 146 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 147 * 148 * If the user does not pass priv level information via branch_sample_type, 149 * the kernel uses the event's priv level. Branch and event priv levels do 150 * not have to match. Branch priv level is checked for permissions. 151 * 152 * The branch types can be combined, however BRANCH_ANY covers all types 153 * of branches and therefore it supersedes all the other types. 154 */ 155 enum perf_branch_sample_type_shift { 156 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 157 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 158 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 159 160 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 161 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 162 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 163 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 164 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 165 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 166 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 167 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 168 169 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 170 171 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 172 }; 173 174 enum perf_branch_sample_type { 175 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 176 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 177 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 178 179 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 180 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 181 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 182 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 183 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 184 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 185 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 186 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 187 188 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 189 190 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 191 }; 192 193 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 194 (PERF_SAMPLE_BRANCH_USER|\ 195 PERF_SAMPLE_BRANCH_KERNEL|\ 196 PERF_SAMPLE_BRANCH_HV) 197 198 /* 199 * Values to determine ABI of the registers dump. 200 */ 201 enum perf_sample_regs_abi { 202 PERF_SAMPLE_REGS_ABI_NONE = 0, 203 PERF_SAMPLE_REGS_ABI_32 = 1, 204 PERF_SAMPLE_REGS_ABI_64 = 2, 205 }; 206 207 /* 208 * Values for the memory transaction event qualifier, mostly for 209 * abort events. Multiple bits can be set. 210 */ 211 enum { 212 PERF_TXN_ELISION = (1 << 0), /* From elision */ 213 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 214 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 215 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 216 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 217 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 218 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 219 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 220 221 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 222 223 /* bits 32..63 are reserved for the abort code */ 224 225 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 226 PERF_TXN_ABORT_SHIFT = 32, 227 }; 228 229 /* 230 * The format of the data returned by read() on a perf event fd, 231 * as specified by attr.read_format: 232 * 233 * struct read_format { 234 * { u64 value; 235 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 236 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 237 * { u64 id; } && PERF_FORMAT_ID 238 * } && !PERF_FORMAT_GROUP 239 * 240 * { u64 nr; 241 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 242 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 243 * { u64 value; 244 * { u64 id; } && PERF_FORMAT_ID 245 * } cntr[nr]; 246 * } && PERF_FORMAT_GROUP 247 * }; 248 */ 249 enum perf_event_read_format { 250 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 251 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 252 PERF_FORMAT_ID = 1U << 2, 253 PERF_FORMAT_GROUP = 1U << 3, 254 255 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 256 }; 257 258 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 259 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 260 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 261 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 262 /* add: sample_stack_user */ 263 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 264 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 265 266 /* 267 * Hardware event_id to monitor via a performance monitoring event: 268 */ 269 struct perf_event_attr { 270 271 /* 272 * Major type: hardware/software/tracepoint/etc. 273 */ 274 __u32 type; 275 276 /* 277 * Size of the attr structure, for fwd/bwd compat. 278 */ 279 __u32 size; 280 281 /* 282 * Type specific configuration information. 283 */ 284 __u64 config; 285 286 union { 287 __u64 sample_period; 288 __u64 sample_freq; 289 }; 290 291 __u64 sample_type; 292 __u64 read_format; 293 294 __u64 disabled : 1, /* off by default */ 295 inherit : 1, /* children inherit it */ 296 pinned : 1, /* must always be on PMU */ 297 exclusive : 1, /* only group on PMU */ 298 exclude_user : 1, /* don't count user */ 299 exclude_kernel : 1, /* ditto kernel */ 300 exclude_hv : 1, /* ditto hypervisor */ 301 exclude_idle : 1, /* don't count when idle */ 302 mmap : 1, /* include mmap data */ 303 comm : 1, /* include comm data */ 304 freq : 1, /* use freq, not period */ 305 inherit_stat : 1, /* per task counts */ 306 enable_on_exec : 1, /* next exec enables */ 307 task : 1, /* trace fork/exit */ 308 watermark : 1, /* wakeup_watermark */ 309 /* 310 * precise_ip: 311 * 312 * 0 - SAMPLE_IP can have arbitrary skid 313 * 1 - SAMPLE_IP must have constant skid 314 * 2 - SAMPLE_IP requested to have 0 skid 315 * 3 - SAMPLE_IP must have 0 skid 316 * 317 * See also PERF_RECORD_MISC_EXACT_IP 318 */ 319 precise_ip : 2, /* skid constraint */ 320 mmap_data : 1, /* non-exec mmap data */ 321 sample_id_all : 1, /* sample_type all events */ 322 323 exclude_host : 1, /* don't count in host */ 324 exclude_guest : 1, /* don't count in guest */ 325 326 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 327 exclude_callchain_user : 1, /* exclude user callchains */ 328 mmap2 : 1, /* include mmap with inode data */ 329 comm_exec : 1, /* flag comm events that are due to an exec */ 330 use_clockid : 1, /* use @clockid for time fields */ 331 __reserved_1 : 38; 332 333 union { 334 __u32 wakeup_events; /* wakeup every n events */ 335 __u32 wakeup_watermark; /* bytes before wakeup */ 336 }; 337 338 __u32 bp_type; 339 union { 340 __u64 bp_addr; 341 __u64 config1; /* extension of config */ 342 }; 343 union { 344 __u64 bp_len; 345 __u64 config2; /* extension of config1 */ 346 }; 347 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 348 349 /* 350 * Defines set of user regs to dump on samples. 351 * See asm/perf_regs.h for details. 352 */ 353 __u64 sample_regs_user; 354 355 /* 356 * Defines size of the user stack to dump on samples. 357 */ 358 __u32 sample_stack_user; 359 360 __s32 clockid; 361 /* 362 * Defines set of regs to dump for each sample 363 * state captured on: 364 * - precise = 0: PMU interrupt 365 * - precise > 0: sampled instruction 366 * 367 * See asm/perf_regs.h for details. 368 */ 369 __u64 sample_regs_intr; 370 371 /* 372 * Wakeup watermark for AUX area 373 */ 374 __u32 aux_watermark; 375 __u32 __reserved_2; /* align to __u64 */ 376 }; 377 378 #define perf_flags(attr) (*(&(attr)->read_format + 1)) 379 380 /* 381 * Ioctls that can be done on a perf event fd: 382 */ 383 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 384 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 385 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 386 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 387 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 388 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 389 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 390 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 391 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 392 393 enum perf_event_ioc_flags { 394 PERF_IOC_FLAG_GROUP = 1U << 0, 395 }; 396 397 /* 398 * Structure of the page that can be mapped via mmap 399 */ 400 struct perf_event_mmap_page { 401 __u32 version; /* version number of this structure */ 402 __u32 compat_version; /* lowest version this is compat with */ 403 404 /* 405 * Bits needed to read the hw events in user-space. 406 * 407 * u32 seq, time_mult, time_shift, index, width; 408 * u64 count, enabled, running; 409 * u64 cyc, time_offset; 410 * s64 pmc = 0; 411 * 412 * do { 413 * seq = pc->lock; 414 * barrier() 415 * 416 * enabled = pc->time_enabled; 417 * running = pc->time_running; 418 * 419 * if (pc->cap_usr_time && enabled != running) { 420 * cyc = rdtsc(); 421 * time_offset = pc->time_offset; 422 * time_mult = pc->time_mult; 423 * time_shift = pc->time_shift; 424 * } 425 * 426 * index = pc->index; 427 * count = pc->offset; 428 * if (pc->cap_user_rdpmc && index) { 429 * width = pc->pmc_width; 430 * pmc = rdpmc(index - 1); 431 * } 432 * 433 * barrier(); 434 * } while (pc->lock != seq); 435 * 436 * NOTE: for obvious reason this only works on self-monitoring 437 * processes. 438 */ 439 __u32 lock; /* seqlock for synchronization */ 440 __u32 index; /* hardware event identifier */ 441 __s64 offset; /* add to hardware event value */ 442 __u64 time_enabled; /* time event active */ 443 __u64 time_running; /* time event on cpu */ 444 union { 445 __u64 capabilities; 446 struct { 447 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 448 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 449 450 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 451 cap_user_time : 1, /* The time_* fields are used */ 452 cap_user_time_zero : 1, /* The time_zero field is used */ 453 cap_____res : 59; 454 }; 455 }; 456 457 /* 458 * If cap_user_rdpmc this field provides the bit-width of the value 459 * read using the rdpmc() or equivalent instruction. This can be used 460 * to sign extend the result like: 461 * 462 * pmc <<= 64 - width; 463 * pmc >>= 64 - width; // signed shift right 464 * count += pmc; 465 */ 466 __u16 pmc_width; 467 468 /* 469 * If cap_usr_time the below fields can be used to compute the time 470 * delta since time_enabled (in ns) using rdtsc or similar. 471 * 472 * u64 quot, rem; 473 * u64 delta; 474 * 475 * quot = (cyc >> time_shift); 476 * rem = cyc & ((1 << time_shift) - 1); 477 * delta = time_offset + quot * time_mult + 478 * ((rem * time_mult) >> time_shift); 479 * 480 * Where time_offset,time_mult,time_shift and cyc are read in the 481 * seqcount loop described above. This delta can then be added to 482 * enabled and possible running (if index), improving the scaling: 483 * 484 * enabled += delta; 485 * if (index) 486 * running += delta; 487 * 488 * quot = count / running; 489 * rem = count % running; 490 * count = quot * enabled + (rem * enabled) / running; 491 */ 492 __u16 time_shift; 493 __u32 time_mult; 494 __u64 time_offset; 495 /* 496 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 497 * from sample timestamps. 498 * 499 * time = timestamp - time_zero; 500 * quot = time / time_mult; 501 * rem = time % time_mult; 502 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 503 * 504 * And vice versa: 505 * 506 * quot = cyc >> time_shift; 507 * rem = cyc & ((1 << time_shift) - 1); 508 * timestamp = time_zero + quot * time_mult + 509 * ((rem * time_mult) >> time_shift); 510 */ 511 __u64 time_zero; 512 __u32 size; /* Header size up to __reserved[] fields. */ 513 514 /* 515 * Hole for extension of the self monitor capabilities 516 */ 517 518 __u8 __reserved[118*8+4]; /* align to 1k. */ 519 520 /* 521 * Control data for the mmap() data buffer. 522 * 523 * User-space reading the @data_head value should issue an smp_rmb(), 524 * after reading this value. 525 * 526 * When the mapping is PROT_WRITE the @data_tail value should be 527 * written by userspace to reflect the last read data, after issueing 528 * an smp_mb() to separate the data read from the ->data_tail store. 529 * In this case the kernel will not over-write unread data. 530 * 531 * See perf_output_put_handle() for the data ordering. 532 * 533 * data_{offset,size} indicate the location and size of the perf record 534 * buffer within the mmapped area. 535 */ 536 __u64 data_head; /* head in the data section */ 537 __u64 data_tail; /* user-space written tail */ 538 __u64 data_offset; /* where the buffer starts */ 539 __u64 data_size; /* data buffer size */ 540 541 /* 542 * AUX area is defined by aux_{offset,size} fields that should be set 543 * by the userspace, so that 544 * 545 * aux_offset >= data_offset + data_size 546 * 547 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 548 * 549 * Ring buffer pointers aux_{head,tail} have the same semantics as 550 * data_{head,tail} and same ordering rules apply. 551 */ 552 __u64 aux_head; 553 __u64 aux_tail; 554 __u64 aux_offset; 555 __u64 aux_size; 556 }; 557 558 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 559 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 560 #define PERF_RECORD_MISC_KERNEL (1 << 0) 561 #define PERF_RECORD_MISC_USER (2 << 0) 562 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 563 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 564 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 565 566 /* 567 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on 568 * different events so can reuse the same bit position. 569 */ 570 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 571 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 572 /* 573 * Indicates that the content of PERF_SAMPLE_IP points to 574 * the actual instruction that triggered the event. See also 575 * perf_event_attr::precise_ip. 576 */ 577 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 578 /* 579 * Reserve the last bit to indicate some extended misc field 580 */ 581 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 582 583 struct perf_event_header { 584 __u32 type; 585 __u16 misc; 586 __u16 size; 587 }; 588 589 enum perf_event_type { 590 591 /* 592 * If perf_event_attr.sample_id_all is set then all event types will 593 * have the sample_type selected fields related to where/when 594 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 595 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 596 * just after the perf_event_header and the fields already present for 597 * the existing fields, i.e. at the end of the payload. That way a newer 598 * perf.data file will be supported by older perf tools, with these new 599 * optional fields being ignored. 600 * 601 * struct sample_id { 602 * { u32 pid, tid; } && PERF_SAMPLE_TID 603 * { u64 time; } && PERF_SAMPLE_TIME 604 * { u64 id; } && PERF_SAMPLE_ID 605 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 606 * { u32 cpu, res; } && PERF_SAMPLE_CPU 607 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 608 * } && perf_event_attr::sample_id_all 609 * 610 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 611 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 612 * relative to header.size. 613 */ 614 615 /* 616 * The MMAP events record the PROT_EXEC mappings so that we can 617 * correlate userspace IPs to code. They have the following structure: 618 * 619 * struct { 620 * struct perf_event_header header; 621 * 622 * u32 pid, tid; 623 * u64 addr; 624 * u64 len; 625 * u64 pgoff; 626 * char filename[]; 627 * struct sample_id sample_id; 628 * }; 629 */ 630 PERF_RECORD_MMAP = 1, 631 632 /* 633 * struct { 634 * struct perf_event_header header; 635 * u64 id; 636 * u64 lost; 637 * struct sample_id sample_id; 638 * }; 639 */ 640 PERF_RECORD_LOST = 2, 641 642 /* 643 * struct { 644 * struct perf_event_header header; 645 * 646 * u32 pid, tid; 647 * char comm[]; 648 * struct sample_id sample_id; 649 * }; 650 */ 651 PERF_RECORD_COMM = 3, 652 653 /* 654 * struct { 655 * struct perf_event_header header; 656 * u32 pid, ppid; 657 * u32 tid, ptid; 658 * u64 time; 659 * struct sample_id sample_id; 660 * }; 661 */ 662 PERF_RECORD_EXIT = 4, 663 664 /* 665 * struct { 666 * struct perf_event_header header; 667 * u64 time; 668 * u64 id; 669 * u64 stream_id; 670 * struct sample_id sample_id; 671 * }; 672 */ 673 PERF_RECORD_THROTTLE = 5, 674 PERF_RECORD_UNTHROTTLE = 6, 675 676 /* 677 * struct { 678 * struct perf_event_header header; 679 * u32 pid, ppid; 680 * u32 tid, ptid; 681 * u64 time; 682 * struct sample_id sample_id; 683 * }; 684 */ 685 PERF_RECORD_FORK = 7, 686 687 /* 688 * struct { 689 * struct perf_event_header header; 690 * u32 pid, tid; 691 * 692 * struct read_format values; 693 * struct sample_id sample_id; 694 * }; 695 */ 696 PERF_RECORD_READ = 8, 697 698 /* 699 * struct { 700 * struct perf_event_header header; 701 * 702 * # 703 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 704 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 705 * # is fixed relative to header. 706 * # 707 * 708 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 709 * { u64 ip; } && PERF_SAMPLE_IP 710 * { u32 pid, tid; } && PERF_SAMPLE_TID 711 * { u64 time; } && PERF_SAMPLE_TIME 712 * { u64 addr; } && PERF_SAMPLE_ADDR 713 * { u64 id; } && PERF_SAMPLE_ID 714 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 715 * { u32 cpu, res; } && PERF_SAMPLE_CPU 716 * { u64 period; } && PERF_SAMPLE_PERIOD 717 * 718 * { struct read_format values; } && PERF_SAMPLE_READ 719 * 720 * { u64 nr, 721 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 722 * 723 * # 724 * # The RAW record below is opaque data wrt the ABI 725 * # 726 * # That is, the ABI doesn't make any promises wrt to 727 * # the stability of its content, it may vary depending 728 * # on event, hardware, kernel version and phase of 729 * # the moon. 730 * # 731 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 732 * # 733 * 734 * { u32 size; 735 * char data[size];}&& PERF_SAMPLE_RAW 736 * 737 * { u64 nr; 738 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 739 * 740 * { u64 abi; # enum perf_sample_regs_abi 741 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 742 * 743 * { u64 size; 744 * char data[size]; 745 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 746 * 747 * { u64 weight; } && PERF_SAMPLE_WEIGHT 748 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 749 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 750 * { u64 abi; # enum perf_sample_regs_abi 751 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 752 * }; 753 */ 754 PERF_RECORD_SAMPLE = 9, 755 756 /* 757 * The MMAP2 records are an augmented version of MMAP, they add 758 * maj, min, ino numbers to be used to uniquely identify each mapping 759 * 760 * struct { 761 * struct perf_event_header header; 762 * 763 * u32 pid, tid; 764 * u64 addr; 765 * u64 len; 766 * u64 pgoff; 767 * u32 maj; 768 * u32 min; 769 * u64 ino; 770 * u64 ino_generation; 771 * u32 prot, flags; 772 * char filename[]; 773 * struct sample_id sample_id; 774 * }; 775 */ 776 PERF_RECORD_MMAP2 = 10, 777 778 /* 779 * Records that new data landed in the AUX buffer part. 780 * 781 * struct { 782 * struct perf_event_header header; 783 * 784 * u64 aux_offset; 785 * u64 aux_size; 786 * u64 flags; 787 * struct sample_id sample_id; 788 * }; 789 */ 790 PERF_RECORD_AUX = 11, 791 792 /* 793 * Indicates that instruction trace has started 794 * 795 * struct { 796 * struct perf_event_header header; 797 * u32 pid; 798 * u32 tid; 799 * }; 800 */ 801 PERF_RECORD_ITRACE_START = 12, 802 803 PERF_RECORD_MAX, /* non-ABI */ 804 }; 805 806 #define PERF_MAX_STACK_DEPTH 127 807 808 enum perf_callchain_context { 809 PERF_CONTEXT_HV = (__u64)-32, 810 PERF_CONTEXT_KERNEL = (__u64)-128, 811 PERF_CONTEXT_USER = (__u64)-512, 812 813 PERF_CONTEXT_GUEST = (__u64)-2048, 814 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 815 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 816 817 PERF_CONTEXT_MAX = (__u64)-4095, 818 }; 819 820 /** 821 * PERF_RECORD_AUX::flags bits 822 */ 823 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 824 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 825 826 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 827 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 828 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 829 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 830 831 union perf_mem_data_src { 832 __u64 val; 833 struct { 834 __u64 mem_op:5, /* type of opcode */ 835 mem_lvl:14, /* memory hierarchy level */ 836 mem_snoop:5, /* snoop mode */ 837 mem_lock:2, /* lock instr */ 838 mem_dtlb:7, /* tlb access */ 839 mem_rsvd:31; 840 }; 841 }; 842 843 /* type of opcode (load/store/prefetch,code) */ 844 #define PERF_MEM_OP_NA 0x01 /* not available */ 845 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 846 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 847 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 848 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 849 #define PERF_MEM_OP_SHIFT 0 850 851 /* memory hierarchy (memory level, hit or miss) */ 852 #define PERF_MEM_LVL_NA 0x01 /* not available */ 853 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 854 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 855 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 856 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 857 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 858 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 859 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 860 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 861 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 862 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 863 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 864 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 865 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 866 #define PERF_MEM_LVL_SHIFT 5 867 868 /* snoop mode */ 869 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 870 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 871 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 872 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 873 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 874 #define PERF_MEM_SNOOP_SHIFT 19 875 876 /* locked instruction */ 877 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 878 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 879 #define PERF_MEM_LOCK_SHIFT 24 880 881 /* TLB access */ 882 #define PERF_MEM_TLB_NA 0x01 /* not available */ 883 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 884 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 885 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 886 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 887 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 888 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 889 #define PERF_MEM_TLB_SHIFT 26 890 891 #define PERF_MEM_S(a, s) \ 892 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 893 894 /* 895 * single taken branch record layout: 896 * 897 * from: source instruction (may not always be a branch insn) 898 * to: branch target 899 * mispred: branch target was mispredicted 900 * predicted: branch target was predicted 901 * 902 * support for mispred, predicted is optional. In case it 903 * is not supported mispred = predicted = 0. 904 * 905 * in_tx: running in a hardware transaction 906 * abort: aborting a hardware transaction 907 */ 908 struct perf_branch_entry { 909 __u64 from; 910 __u64 to; 911 __u64 mispred:1, /* target mispredicted */ 912 predicted:1,/* target predicted */ 913 in_tx:1, /* in transaction */ 914 abort:1, /* transaction abort */ 915 reserved:60; 916 }; 917 918 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 919