1 /* savage_drm.h -- Public header for the savage driver 2 * 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef __SAVAGE_DRM_H__ 27 #define __SAVAGE_DRM_H__ 28 29 #include <drm/drm.h> 30 31 #ifndef __SAVAGE_SAREA_DEFINES__ 32 #define __SAVAGE_SAREA_DEFINES__ 33 34 /* 2 heaps (1 for card, 1 for agp), each divided into up to 128 35 * regions, subject to a minimum region size of (1<<16) == 64k. 36 * 37 * Clients may subdivide regions internally, but when sharing between 38 * clients, the region size is the minimum granularity. 39 */ 40 41 #define SAVAGE_CARD_HEAP 0 42 #define SAVAGE_AGP_HEAP 1 43 #define SAVAGE_NR_TEX_HEAPS 2 44 #define SAVAGE_NR_TEX_REGIONS 16 45 #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 46 47 #endif /* __SAVAGE_SAREA_DEFINES__ */ 48 49 typedef struct _drm_savage_sarea { 50 /* LRU lists for texture memory in agp space and on the card. 51 */ 52 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 53 1]; 54 unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; 55 56 /* Mechanism to validate card state. 57 */ 58 int ctxOwner; 59 } drm_savage_sarea_t, *drm_savage_sarea_ptr; 60 61 /* Savage-specific ioctls 62 */ 63 #define DRM_SAVAGE_BCI_INIT 0x00 64 #define DRM_SAVAGE_BCI_CMDBUF 0x01 65 #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 66 #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 67 68 #define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) 69 #define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) 70 #define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) 71 #define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) 72 73 #define SAVAGE_DMA_PCI 1 74 #define SAVAGE_DMA_AGP 3 75 typedef struct drm_savage_init { 76 enum { 77 SAVAGE_INIT_BCI = 1, 78 SAVAGE_CLEANUP_BCI = 2 79 } func; 80 unsigned int sarea_priv_offset; 81 82 /* some parameters */ 83 unsigned int cob_size; 84 unsigned int bci_threshold_lo, bci_threshold_hi; 85 unsigned int dma_type; 86 87 /* frame buffer layout */ 88 unsigned int fb_bpp; 89 unsigned int front_offset, front_pitch; 90 unsigned int back_offset, back_pitch; 91 unsigned int depth_bpp; 92 unsigned int depth_offset, depth_pitch; 93 94 /* local textures */ 95 unsigned int texture_offset; 96 unsigned int texture_size; 97 98 /* physical locations of non-permanent maps */ 99 unsigned long status_offset; 100 unsigned long buffers_offset; 101 unsigned long agp_textures_offset; 102 unsigned long cmd_dma_offset; 103 } drm_savage_init_t; 104 105 typedef union drm_savage_cmd_header drm_savage_cmd_header_t; 106 typedef struct drm_savage_cmdbuf { 107 /* command buffer in client's address space */ 108 drm_savage_cmd_header_t __user *cmd_addr; 109 unsigned int size; /* size of the command buffer in 64bit units */ 110 111 unsigned int dma_idx; /* DMA buffer index to use */ 112 int discard; /* discard DMA buffer when done */ 113 /* vertex buffer in client's address space */ 114 unsigned int __user *vb_addr; 115 unsigned int vb_size; /* size of client vertex buffer in bytes */ 116 unsigned int vb_stride; /* stride of vertices in 32bit words */ 117 /* boxes in client's address space */ 118 struct drm_clip_rect __user *box_addr; 119 unsigned int nbox; /* number of clipping boxes */ 120 } drm_savage_cmdbuf_t; 121 122 #define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ 123 #define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ 124 #define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ 125 typedef struct drm_savage_event { 126 unsigned int count; 127 unsigned int flags; 128 } drm_savage_event_emit_t, drm_savage_event_wait_t; 129 130 /* Commands for the cmdbuf ioctl 131 */ 132 #define SAVAGE_CMD_STATE 0 /* a range of state registers */ 133 #define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ 134 #define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ 135 #define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ 136 #define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ 137 #define SAVAGE_CMD_CLEAR 5 /* clear buffers */ 138 #define SAVAGE_CMD_SWAP 6 /* swap buffers */ 139 140 /* Primitive types 141 */ 142 #define SAVAGE_PRIM_TRILIST 0 /* triangle list */ 143 #define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ 144 #define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ 145 #define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat 146 * shading on s3d */ 147 148 /* Skip flags (vertex format) 149 */ 150 #define SAVAGE_SKIP_Z 0x01 151 #define SAVAGE_SKIP_W 0x02 152 #define SAVAGE_SKIP_C0 0x04 153 #define SAVAGE_SKIP_C1 0x08 154 #define SAVAGE_SKIP_S0 0x10 155 #define SAVAGE_SKIP_T0 0x20 156 #define SAVAGE_SKIP_ST0 0x30 157 #define SAVAGE_SKIP_S1 0x40 158 #define SAVAGE_SKIP_T1 0x80 159 #define SAVAGE_SKIP_ST1 0xc0 160 #define SAVAGE_SKIP_ALL_S3D 0x3f 161 #define SAVAGE_SKIP_ALL_S4 0xff 162 163 /* Buffer names for clear command 164 */ 165 #define SAVAGE_FRONT 0x1 166 #define SAVAGE_BACK 0x2 167 #define SAVAGE_DEPTH 0x4 168 169 /* 64-bit command header 170 */ 171 union drm_savage_cmd_header { 172 struct { 173 unsigned char cmd; /* command */ 174 unsigned char pad0; 175 unsigned short pad1; 176 unsigned short pad2; 177 unsigned short pad3; 178 } cmd; /* generic */ 179 struct { 180 unsigned char cmd; 181 unsigned char global; /* need idle engine? */ 182 unsigned short count; /* number of consecutive registers */ 183 unsigned short start; /* first register */ 184 unsigned short pad3; 185 } state; /* SAVAGE_CMD_STATE */ 186 struct { 187 unsigned char cmd; 188 unsigned char prim; /* primitive type */ 189 unsigned short skip; /* vertex format (skip flags) */ 190 unsigned short count; /* number of vertices */ 191 unsigned short start; /* first vertex in DMA/vertex buffer */ 192 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ 193 struct { 194 unsigned char cmd; 195 unsigned char prim; 196 unsigned short skip; 197 unsigned short count; /* number of indices that follow */ 198 unsigned short pad3; 199 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ 200 struct { 201 unsigned char cmd; 202 unsigned char pad0; 203 unsigned short pad1; 204 unsigned int flags; 205 } clear0; /* SAVAGE_CMD_CLEAR */ 206 struct { 207 unsigned int mask; 208 unsigned int value; 209 } clear1; /* SAVAGE_CMD_CLEAR data */ 210 }; 211 212 #endif 213