1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/i2c-omap.h>
18
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
22
23 #include "omap_hwmod_common_data.h"
24
25 #include "control.h"
26 #include "cm33xx.h"
27 #include "prm33xx.h"
28 #include "prm-regbits-33xx.h"
29 #include "i2c.h"
30 #include "wd_timer.h"
31 #include "omap_hwmod_33xx_43xx_common_data.h"
32
33 /*
34 * IP blocks
35 */
36
37 /*
38 * 'emif' class
39 * instance(s): emif
40 */
41 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
42 .rev_offs = 0x0000,
43 };
44
45 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
46 .name = "emif",
47 .sysc = &am33xx_emif_sysc,
48 };
49
50 /* emif */
51 static struct omap_hwmod am33xx_emif_hwmod = {
52 .name = "emif",
53 .class = &am33xx_emif_hwmod_class,
54 .clkdm_name = "l3_clkdm",
55 .flags = HWMOD_INIT_NO_IDLE,
56 .main_clk = "dpll_ddr_m2_div2_ck",
57 .prcm = {
58 .omap4 = {
59 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
60 .modulemode = MODULEMODE_SWCTRL,
61 },
62 },
63 };
64
65 /* l4_hs */
66 static struct omap_hwmod am33xx_l4_hs_hwmod = {
67 .name = "l4_hs",
68 .class = &am33xx_l4_hwmod_class,
69 .clkdm_name = "l4hs_clkdm",
70 .flags = HWMOD_INIT_NO_IDLE,
71 .main_clk = "l4hs_gclk",
72 .prcm = {
73 .omap4 = {
74 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
75 .modulemode = MODULEMODE_SWCTRL,
76 },
77 },
78 };
79
80 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
81 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
82 };
83
84 /* wkup_m3 */
85 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
86 .name = "wkup_m3",
87 .class = &am33xx_wkup_m3_hwmod_class,
88 .clkdm_name = "l4_wkup_aon_clkdm",
89 /* Keep hardreset asserted */
90 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
91 .main_clk = "dpll_core_m4_div2_ck",
92 .prcm = {
93 .omap4 = {
94 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
95 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
96 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
97 .modulemode = MODULEMODE_SWCTRL,
98 },
99 },
100 .rst_lines = am33xx_wkup_m3_resets,
101 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
102 };
103
104 /*
105 * 'adc/tsc' class
106 * TouchScreen Controller (Anolog-To-Digital Converter)
107 */
108 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
109 .rev_offs = 0x00,
110 .sysc_offs = 0x10,
111 .sysc_flags = SYSC_HAS_SIDLEMODE,
112 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
113 SIDLE_SMART_WKUP),
114 .sysc_fields = &omap_hwmod_sysc_type2,
115 };
116
117 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
118 .name = "adc_tsc",
119 .sysc = &am33xx_adc_tsc_sysc,
120 };
121
122 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
123 .name = "adc_tsc",
124 .class = &am33xx_adc_tsc_hwmod_class,
125 .clkdm_name = "l4_wkup_clkdm",
126 .main_clk = "adc_tsc_fck",
127 .prcm = {
128 .omap4 = {
129 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
130 .modulemode = MODULEMODE_SWCTRL,
131 },
132 },
133 };
134
135 /*
136 * Modules omap_hwmod structures
137 *
138 * The following IPs are excluded for the moment because:
139 * - They do not need an explicit SW control using omap_hwmod API.
140 * - They still need to be validated with the driver
141 * properly adapted to omap_hwmod / omap_device
142 *
143 * - cEFUSE (doesn't fall under any ocp_if)
144 * - clkdiv32k
145 * - ocp watch point
146 */
147 #if 0
148 /*
149 * 'cefuse' class
150 */
151 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
152 .name = "cefuse",
153 };
154
155 static struct omap_hwmod am33xx_cefuse_hwmod = {
156 .name = "cefuse",
157 .class = &am33xx_cefuse_hwmod_class,
158 .clkdm_name = "l4_cefuse_clkdm",
159 .main_clk = "cefuse_fck",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
164 },
165 },
166 };
167
168 /*
169 * 'clkdiv32k' class
170 */
171 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
172 .name = "clkdiv32k",
173 };
174
175 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
176 .name = "clkdiv32k",
177 .class = &am33xx_clkdiv32k_hwmod_class,
178 .clkdm_name = "clk_24mhz_clkdm",
179 .main_clk = "clkdiv32k_ick",
180 .prcm = {
181 .omap4 = {
182 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
183 .modulemode = MODULEMODE_SWCTRL,
184 },
185 },
186 };
187
188 /* ocpwp */
189 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
190 .name = "ocpwp",
191 };
192
193 static struct omap_hwmod am33xx_ocpwp_hwmod = {
194 .name = "ocpwp",
195 .class = &am33xx_ocpwp_hwmod_class,
196 .clkdm_name = "l4ls_clkdm",
197 .main_clk = "l4ls_gclk",
198 .prcm = {
199 .omap4 = {
200 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
201 .modulemode = MODULEMODE_SWCTRL,
202 },
203 },
204 };
205 #endif
206
207 /*
208 * 'debugss' class
209 * debug sub system
210 */
211 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
212 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
213 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
214 };
215
216 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
217 .name = "debugss",
218 };
219
220 static struct omap_hwmod am33xx_debugss_hwmod = {
221 .name = "debugss",
222 .class = &am33xx_debugss_hwmod_class,
223 .clkdm_name = "l3_aon_clkdm",
224 .main_clk = "trace_clk_div_ck",
225 .prcm = {
226 .omap4 = {
227 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
228 .modulemode = MODULEMODE_SWCTRL,
229 },
230 },
231 .opt_clks = debugss_opt_clks,
232 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
233 };
234
235 static struct omap_hwmod am33xx_control_hwmod = {
236 .name = "control",
237 .class = &am33xx_control_hwmod_class,
238 .clkdm_name = "l4_wkup_clkdm",
239 .flags = HWMOD_INIT_NO_IDLE,
240 .main_clk = "dpll_core_m4_div2_ck",
241 .prcm = {
242 .omap4 = {
243 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
244 .modulemode = MODULEMODE_SWCTRL,
245 },
246 },
247 };
248
249 /* gpio0 */
250 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
251 { .role = "dbclk", .clk = "gpio0_dbclk" },
252 };
253
254 static struct omap_hwmod am33xx_gpio0_hwmod = {
255 .name = "gpio1",
256 .class = &am33xx_gpio_hwmod_class,
257 .clkdm_name = "l4_wkup_clkdm",
258 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
259 .main_clk = "dpll_core_m4_div2_ck",
260 .prcm = {
261 .omap4 = {
262 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
263 .modulemode = MODULEMODE_SWCTRL,
264 },
265 },
266 .opt_clks = gpio0_opt_clks,
267 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
268 .dev_attr = &gpio_dev_attr,
269 };
270
271 /* lcdc */
272 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
273 .rev_offs = 0x0,
274 .sysc_offs = 0x54,
275 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
276 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
277 .sysc_fields = &omap_hwmod_sysc_type2,
278 };
279
280 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
281 .name = "lcdc",
282 .sysc = &lcdc_sysc,
283 };
284
285 static struct omap_hwmod am33xx_lcdc_hwmod = {
286 .name = "lcdc",
287 .class = &am33xx_lcdc_hwmod_class,
288 .clkdm_name = "lcdc_clkdm",
289 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
290 .main_clk = "lcd_gclk",
291 .prcm = {
292 .omap4 = {
293 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297 };
298
299 /*
300 * 'usb_otg' class
301 * high-speed on-the-go universal serial bus (usb_otg) controller
302 */
303 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
304 .rev_offs = 0x0,
305 .sysc_offs = 0x10,
306 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
309 .sysc_fields = &omap_hwmod_sysc_type2,
310 };
311
312 static struct omap_hwmod_class am33xx_usbotg_class = {
313 .name = "usbotg",
314 .sysc = &am33xx_usbhsotg_sysc,
315 };
316
317 static struct omap_hwmod am33xx_usbss_hwmod = {
318 .name = "usb_otg_hs",
319 .class = &am33xx_usbotg_class,
320 .clkdm_name = "l3s_clkdm",
321 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
322 .main_clk = "usbotg_fck",
323 .prcm = {
324 .omap4 = {
325 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
326 .modulemode = MODULEMODE_SWCTRL,
327 },
328 },
329 };
330
331
332 /*
333 * Interfaces
334 */
335
336 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
337 {
338 .pa_start = 0x4c000000,
339 .pa_end = 0x4c000fff,
340 .flags = ADDR_TYPE_RT
341 },
342 { }
343 };
344 /* l3 main -> emif */
345 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
346 .master = &am33xx_l3_main_hwmod,
347 .slave = &am33xx_emif_hwmod,
348 .clk = "dpll_core_m4_ck",
349 .addr = am33xx_emif_addrs,
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 };
352
353 /* l3 main -> l4 hs */
354 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
355 .master = &am33xx_l3_main_hwmod,
356 .slave = &am33xx_l4_hs_hwmod,
357 .clk = "l3s_gclk",
358 .user = OCP_USER_MPU | OCP_USER_SDMA,
359 };
360
361 /* wkup m3 -> l4 wkup */
362 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
363 .master = &am33xx_wkup_m3_hwmod,
364 .slave = &am33xx_l4_wkup_hwmod,
365 .clk = "dpll_core_m4_div2_ck",
366 .user = OCP_USER_MPU | OCP_USER_SDMA,
367 };
368
369 /* l4 wkup -> wkup m3 */
370 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
371 .master = &am33xx_l4_wkup_hwmod,
372 .slave = &am33xx_wkup_m3_hwmod,
373 .clk = "dpll_core_m4_div2_ck",
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375 };
376
377 /* l4 hs -> pru-icss */
378 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
379 .master = &am33xx_l4_hs_hwmod,
380 .slave = &am33xx_pruss_hwmod,
381 .clk = "dpll_core_m4_ck",
382 .user = OCP_USER_MPU | OCP_USER_SDMA,
383 };
384
385 /* l3_main -> debugss */
386 static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
387 {
388 .pa_start = 0x4b000000,
389 .pa_end = 0x4b000000 + SZ_16M - 1,
390 .flags = ADDR_TYPE_RT
391 },
392 { }
393 };
394
395 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
396 .master = &am33xx_l3_main_hwmod,
397 .slave = &am33xx_debugss_hwmod,
398 .clk = "dpll_core_m4_ck",
399 .addr = am33xx_debugss_addrs,
400 .user = OCP_USER_MPU,
401 };
402
403 /* l4 wkup -> smartreflex0 */
404 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
405 .master = &am33xx_l4_wkup_hwmod,
406 .slave = &am33xx_smartreflex0_hwmod,
407 .clk = "dpll_core_m4_div2_ck",
408 .user = OCP_USER_MPU,
409 };
410
411 /* l4 wkup -> smartreflex1 */
412 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
413 .master = &am33xx_l4_wkup_hwmod,
414 .slave = &am33xx_smartreflex1_hwmod,
415 .clk = "dpll_core_m4_div2_ck",
416 .user = OCP_USER_MPU,
417 };
418
419 /* l4 wkup -> control */
420 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
421 .master = &am33xx_l4_wkup_hwmod,
422 .slave = &am33xx_control_hwmod,
423 .clk = "dpll_core_m4_div2_ck",
424 .user = OCP_USER_MPU,
425 };
426
427 /* L4 WKUP -> I2C1 */
428 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
429 .master = &am33xx_l4_wkup_hwmod,
430 .slave = &am33xx_i2c1_hwmod,
431 .clk = "dpll_core_m4_div2_ck",
432 .user = OCP_USER_MPU,
433 };
434
435 /* L4 WKUP -> GPIO1 */
436 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
437 .master = &am33xx_l4_wkup_hwmod,
438 .slave = &am33xx_gpio0_hwmod,
439 .clk = "dpll_core_m4_div2_ck",
440 .user = OCP_USER_MPU | OCP_USER_SDMA,
441 };
442
443 /* L4 WKUP -> ADC_TSC */
444 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
445 {
446 .pa_start = 0x44E0D000,
447 .pa_end = 0x44E0D000 + SZ_8K - 1,
448 .flags = ADDR_TYPE_RT
449 },
450 { }
451 };
452
453 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
454 .master = &am33xx_l4_wkup_hwmod,
455 .slave = &am33xx_adc_tsc_hwmod,
456 .clk = "dpll_core_m4_div2_ck",
457 .addr = am33xx_adc_tsc_addrs,
458 .user = OCP_USER_MPU,
459 };
460
461 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
462 .master = &am33xx_l4_hs_hwmod,
463 .slave = &am33xx_cpgmac0_hwmod,
464 .clk = "cpsw_125mhz_gclk",
465 .user = OCP_USER_MPU,
466 };
467
468 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
469 {
470 .pa_start = 0x4830E000,
471 .pa_end = 0x4830E000 + SZ_8K - 1,
472 .flags = ADDR_TYPE_RT,
473 },
474 { }
475 };
476
477 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
478 .master = &am33xx_l3_main_hwmod,
479 .slave = &am33xx_lcdc_hwmod,
480 .clk = "dpll_core_m4_ck",
481 .addr = am33xx_lcdc_addr_space,
482 .user = OCP_USER_MPU,
483 };
484
485 /* l4 wkup -> timer1 */
486 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
487 .master = &am33xx_l4_wkup_hwmod,
488 .slave = &am33xx_timer1_hwmod,
489 .clk = "dpll_core_m4_div2_ck",
490 .user = OCP_USER_MPU,
491 };
492
493 /* l4 wkup -> uart1 */
494 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
495 .master = &am33xx_l4_wkup_hwmod,
496 .slave = &am33xx_uart1_hwmod,
497 .clk = "dpll_core_m4_div2_ck",
498 .user = OCP_USER_MPU,
499 };
500
501 /* l4 wkup -> wd_timer1 */
502 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
503 .master = &am33xx_l4_wkup_hwmod,
504 .slave = &am33xx_wd_timer1_hwmod,
505 .clk = "dpll_core_m4_div2_ck",
506 .user = OCP_USER_MPU,
507 };
508
509 /* usbss */
510 /* l3 s -> USBSS interface */
511 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
512 .master = &am33xx_l3_s_hwmod,
513 .slave = &am33xx_usbss_hwmod,
514 .clk = "l3s_gclk",
515 .user = OCP_USER_MPU,
516 .flags = OCPIF_SWSUP_IDLE,
517 };
518
519 /* rng */
520 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
521 .rev_offs = 0x1fe0,
522 .sysc_offs = 0x1fe4,
523 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
524 .idlemodes = SIDLE_FORCE | SIDLE_NO,
525 .sysc_fields = &omap_hwmod_sysc_type1,
526 };
527
528 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
529 .name = "rng",
530 .sysc = &am33xx_rng_sysc,
531 };
532
533 static struct omap_hwmod am33xx_rng_hwmod = {
534 .name = "rng",
535 .class = &am33xx_rng_hwmod_class,
536 .clkdm_name = "l4ls_clkdm",
537 .flags = HWMOD_SWSUP_SIDLE,
538 .main_clk = "rng_fck",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
543 },
544 },
545 };
546
547 static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
548 .master = &am33xx_l4_ls_hwmod,
549 .slave = &am33xx_rng_hwmod,
550 .clk = "rng_fck",
551 .user = OCP_USER_MPU,
552 };
553
554 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
555 &am33xx_l3_main__emif,
556 &am33xx_mpu__l3_main,
557 &am33xx_mpu__prcm,
558 &am33xx_l3_s__l4_ls,
559 &am33xx_l3_s__l4_wkup,
560 &am33xx_l3_main__l4_hs,
561 &am33xx_l3_main__l3_s,
562 &am33xx_l3_main__l3_instr,
563 &am33xx_l3_main__gfx,
564 &am33xx_l3_s__l3_main,
565 &am33xx_pruss__l3_main,
566 &am33xx_wkup_m3__l4_wkup,
567 &am33xx_gfx__l3_main,
568 &am33xx_l3_main__debugss,
569 &am33xx_l4_wkup__wkup_m3,
570 &am33xx_l4_wkup__control,
571 &am33xx_l4_wkup__smartreflex0,
572 &am33xx_l4_wkup__smartreflex1,
573 &am33xx_l4_wkup__uart1,
574 &am33xx_l4_wkup__timer1,
575 &am33xx_l4_wkup__rtc,
576 &am33xx_l4_wkup__i2c1,
577 &am33xx_l4_wkup__gpio0,
578 &am33xx_l4_wkup__adc_tsc,
579 &am33xx_l4_wkup__wd_timer1,
580 &am33xx_l4_hs__pruss,
581 &am33xx_l4_per__dcan0,
582 &am33xx_l4_per__dcan1,
583 &am33xx_l4_per__gpio1,
584 &am33xx_l4_per__gpio2,
585 &am33xx_l4_per__gpio3,
586 &am33xx_l4_per__i2c2,
587 &am33xx_l4_per__i2c3,
588 &am33xx_l4_per__mailbox,
589 &am33xx_l4_ls__mcasp0,
590 &am33xx_l4_ls__mcasp1,
591 &am33xx_l4_ls__mmc0,
592 &am33xx_l4_ls__mmc1,
593 &am33xx_l3_s__mmc2,
594 &am33xx_l4_ls__timer2,
595 &am33xx_l4_ls__timer3,
596 &am33xx_l4_ls__timer4,
597 &am33xx_l4_ls__timer5,
598 &am33xx_l4_ls__timer6,
599 &am33xx_l4_ls__timer7,
600 &am33xx_l3_main__tpcc,
601 &am33xx_l4_ls__uart2,
602 &am33xx_l4_ls__uart3,
603 &am33xx_l4_ls__uart4,
604 &am33xx_l4_ls__uart5,
605 &am33xx_l4_ls__uart6,
606 &am33xx_l4_ls__spinlock,
607 &am33xx_l4_ls__elm,
608 &am33xx_l4_ls__epwmss0,
609 &am33xx_epwmss0__ecap0,
610 &am33xx_epwmss0__eqep0,
611 &am33xx_epwmss0__ehrpwm0,
612 &am33xx_l4_ls__epwmss1,
613 &am33xx_epwmss1__ecap1,
614 &am33xx_epwmss1__eqep1,
615 &am33xx_epwmss1__ehrpwm1,
616 &am33xx_l4_ls__epwmss2,
617 &am33xx_epwmss2__ecap2,
618 &am33xx_epwmss2__eqep2,
619 &am33xx_epwmss2__ehrpwm2,
620 &am33xx_l3_s__gpmc,
621 &am33xx_l3_main__lcdc,
622 &am33xx_l4_ls__mcspi0,
623 &am33xx_l4_ls__mcspi1,
624 &am33xx_l3_main__tptc0,
625 &am33xx_l3_main__tptc1,
626 &am33xx_l3_main__tptc2,
627 &am33xx_l3_main__ocmc,
628 &am33xx_l3_s__usbss,
629 &am33xx_l4_hs__cpgmac0,
630 &am33xx_cpgmac0__mdio,
631 &am33xx_l3_main__sha0,
632 &am33xx_l3_main__aes0,
633 &am33xx_l4_per__rng,
634 NULL,
635 };
636
am33xx_hwmod_init(void)637 int __init am33xx_hwmod_init(void)
638 {
639 omap_hwmod_am33xx_reg();
640 omap_hwmod_init();
641 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
642 }
643