1 /*
2 module/mite.h
3 Hardware driver for NI Mite PCI interface chip
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17 */
18
19 #ifndef _MITE_H_
20 #define _MITE_H_
21
22 #include <linux/log2.h>
23 #include <linux/slab.h>
24 #include "../comedi_pci.h"
25
26 #define PCIMIO_COMPAT
27
28 #define MAX_MITE_DMA_CHANNELS 8
29
30 struct mite_dma_descriptor {
31 __le32 count;
32 __le32 addr;
33 __le32 next;
34 u32 dar;
35 };
36
37 struct mite_dma_descriptor_ring {
38 struct device *hw_dev;
39 unsigned int n_links;
40 struct mite_dma_descriptor *descriptors;
41 dma_addr_t descriptors_dma_addr;
42 };
43
44 struct mite_channel {
45 struct mite_struct *mite;
46 unsigned channel;
47 int dir;
48 int done;
49 struct mite_dma_descriptor_ring *ring;
50 };
51
52 struct mite_struct {
53 struct pci_dev *pcidev;
54 resource_size_t mite_phys_addr;
55 void __iomem *mite_io_addr;
56 resource_size_t daq_phys_addr;
57 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
58 short channel_allocated[MAX_MITE_DMA_CHANNELS];
59 int num_channels;
60 unsigned fifo_size;
61 spinlock_t lock;
62 };
63
64 struct mite_struct *mite_alloc(struct pci_dev *pcidev);
65
66 int mite_setup2(struct comedi_device *, struct mite_struct *, bool use_win1);
67
mite_setup(struct comedi_device * dev,struct mite_struct * mite)68 static inline int mite_setup(struct comedi_device *dev,
69 struct mite_struct *mite)
70 {
71 return mite_setup2(dev, mite, false);
72 }
73
74 void mite_detach(struct mite_struct *mite);
75 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
76 void mite_free_ring(struct mite_dma_descriptor_ring *ring);
77 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
78 struct
79 mite_dma_descriptor_ring
80 *ring, unsigned min_channel,
81 unsigned max_channel);
mite_request_channel(struct mite_struct * mite,struct mite_dma_descriptor_ring * ring)82 static inline struct mite_channel *mite_request_channel(struct mite_struct
83 *mite,
84 struct
85 mite_dma_descriptor_ring
86 *ring)
87 {
88 return mite_request_channel_in_range(mite, ring, 0,
89 mite->num_channels - 1);
90 }
91
92 void mite_release_channel(struct mite_channel *mite_chan);
93
94 unsigned mite_dma_tcr(struct mite_channel *mite_chan);
95 void mite_dma_arm(struct mite_channel *mite_chan);
96 void mite_dma_disarm(struct mite_channel *mite_chan);
97 int mite_sync_input_dma(struct mite_channel *mite_chan,
98 struct comedi_subdevice *s);
99 int mite_sync_output_dma(struct mite_channel *mite_chan,
100 struct comedi_subdevice *s);
101 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
102 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
103 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
104 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
105 u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
106 unsigned mite_get_status(struct mite_channel *mite_chan);
107 int mite_done(struct mite_channel *mite_chan);
108
109 void mite_prep_dma(struct mite_channel *mite_chan,
110 unsigned int num_device_bits, unsigned int num_memory_bits);
111 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
112 struct comedi_subdevice *s);
113
114 enum mite_registers {
115 /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
116 written and read back. The bits 0x1f always read as 1.
117 The rest always read as zero. */
118 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
119 MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
120 MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
121 MITE_IODWCR_1 = 0xf4,
122 MITE_PCI_CONFIG_OFFSET = 0x300,
123 MITE_CSIGR = 0x460 /* chip signature */
124 };
125
126 #define MITE_CHAN(x) (0x500 + 0x100 * (x))
127 #define MITE_CHOR(x) (0x00 + MITE_CHAN(x)) /* channel operation */
128 #define MITE_CHCR(x) (0x04 + MITE_CHAN(x)) /* channel control */
129 #define MITE_TCR(x) (0x08 + MITE_CHAN(x)) /* transfer count */
130 #define MITE_MCR(x) (0x0c + MITE_CHAN(x)) /* memory configuration */
131 #define MITE_MAR(x) (0x10 + MITE_CHAN(x)) /* memory address */
132 #define MITE_DCR(x) (0x14 + MITE_CHAN(x)) /* device configuration */
133 #define MITE_DAR(x) (0x18 + MITE_CHAN(x)) /* device address */
134 #define MITE_LKCR(x) (0x1c + MITE_CHAN(x)) /* link configuration */
135 #define MITE_LKAR(x) (0x20 + MITE_CHAN(x)) /* link address */
136 #define MITE_LLKAR(x) (0x24 + MITE_CHAN(x)) /* see tnt5002 manual */
137 #define MITE_BAR(x) (0x28 + MITE_CHAN(x)) /* base address */
138 #define MITE_BCR(x) (0x2c + MITE_CHAN(x)) /* base count */
139 #define MITE_SAR(x) (0x30 + MITE_CHAN(x)) /* ? address */
140 #define MITE_WSCR(x) (0x34 + MITE_CHAN(x)) /* ? */
141 #define MITE_WSER(x) (0x38 + MITE_CHAN(x)) /* ? */
142 #define MITE_CHSR(x) (0x3c + MITE_CHAN(x)) /* channel status */
143 #define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */
144
145 enum MITE_IODWBSR_bits {
146 WENAB = 0x80, /* window enable */
147 };
148
MITE_IODWBSR_1_WSIZE_bits(unsigned size)149 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
150 {
151 unsigned order = 0;
152
153 BUG_ON(size == 0);
154 order = ilog2(size);
155 BUG_ON(order < 1);
156 return (order - 1) & 0x1f;
157 }
158
159 enum MITE_UNKNOWN_DMA_BURST_bits {
160 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
161 };
162
mite_csigr_version(u32 csigr_bits)163 static inline int mite_csigr_version(u32 csigr_bits)
164 {
165 return csigr_bits & 0xf;
166 };
167
mite_csigr_type(u32 csigr_bits)168 static inline int mite_csigr_type(u32 csigr_bits)
169 { /* original mite = 0, minimite = 1 */
170 return (csigr_bits >> 4) & 0xf;
171 };
172
mite_csigr_mmode(u32 csigr_bits)173 static inline int mite_csigr_mmode(u32 csigr_bits)
174 { /* mite mode, minimite = 1 */
175 return (csigr_bits >> 8) & 0x3;
176 };
177
mite_csigr_imode(u32 csigr_bits)178 static inline int mite_csigr_imode(u32 csigr_bits)
179 { /* cpu port interface mode, pci = 0x3 */
180 return (csigr_bits >> 12) & 0x3;
181 };
182
mite_csigr_dmac(u32 csigr_bits)183 static inline int mite_csigr_dmac(u32 csigr_bits)
184 { /* number of dma channels */
185 return (csigr_bits >> 16) & 0xf;
186 };
187
mite_csigr_wpdep(u32 csigr_bits)188 static inline int mite_csigr_wpdep(u32 csigr_bits)
189 { /* write post fifo depth */
190 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
191
192 return (wpdep_bits) ? (1 << (wpdep_bits - 1)) : 0;
193 }
194
mite_csigr_wins(u32 csigr_bits)195 static inline int mite_csigr_wins(u32 csigr_bits)
196 {
197 return (csigr_bits >> 24) & 0x1f;
198 };
199
mite_csigr_iowins(u32 csigr_bits)200 static inline int mite_csigr_iowins(u32 csigr_bits)
201 { /* number of io windows */
202 return (csigr_bits >> 29) & 0x7;
203 };
204
205 enum MITE_MCR_bits {
206 MCRPON = 0,
207 };
208
209 enum MITE_DCR_bits {
210 DCR_NORMAL = (1 << 29),
211 DCRPON = 0,
212 };
213
214 enum MITE_CHOR_bits {
215 CHOR_DMARESET = (1 << 31),
216 CHOR_SET_SEND_TC = (1 << 11),
217 CHOR_CLR_SEND_TC = (1 << 10),
218 CHOR_SET_LPAUSE = (1 << 9),
219 CHOR_CLR_LPAUSE = (1 << 8),
220 CHOR_CLRDONE = (1 << 7),
221 CHOR_CLRRB = (1 << 6),
222 CHOR_CLRLC = (1 << 5),
223 CHOR_FRESET = (1 << 4),
224 CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
225 CHOR_STOP = (1 << 2), /* stop after emptying fifo */
226 CHOR_CONT = (1 << 1),
227 CHOR_START = (1 << 0),
228 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
229 };
230
231 enum MITE_CHCR_bits {
232 CHCR_SET_DMA_IE = (1 << 31),
233 CHCR_CLR_DMA_IE = (1 << 30),
234 CHCR_SET_LINKP_IE = (1 << 29),
235 CHCR_CLR_LINKP_IE = (1 << 28),
236 CHCR_SET_SAR_IE = (1 << 27),
237 CHCR_CLR_SAR_IE = (1 << 26),
238 CHCR_SET_DONE_IE = (1 << 25),
239 CHCR_CLR_DONE_IE = (1 << 24),
240 CHCR_SET_MRDY_IE = (1 << 23),
241 CHCR_CLR_MRDY_IE = (1 << 22),
242 CHCR_SET_DRDY_IE = (1 << 21),
243 CHCR_CLR_DRDY_IE = (1 << 20),
244 CHCR_SET_LC_IE = (1 << 19),
245 CHCR_CLR_LC_IE = (1 << 18),
246 CHCR_SET_CONT_RB_IE = (1 << 17),
247 CHCR_CLR_CONT_RB_IE = (1 << 16),
248 CHCR_FIFODIS = (1 << 15),
249 CHCR_FIFO_ON = 0,
250 CHCR_BURSTEN = (1 << 14),
251 CHCR_NO_BURSTEN = 0,
252 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
253 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
254 CHCR_DIR = (1 << 3),
255 CHCR_DEV_TO_MEM = CHCR_DIR,
256 CHCR_MEM_TO_DEV = 0,
257 CHCR_NORMAL = (0 << 0),
258 CHCR_CONTINUE = (1 << 0),
259 CHCR_RINGBUFF = (2 << 0),
260 CHCR_LINKSHORT = (4 << 0),
261 CHCR_LINKLONG = (5 << 0),
262 CHCRPON =
263 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
264 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
265 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
266 };
267
268 enum ConfigRegister_bits {
269 CR_REQS_MASK = 0x7 << 16,
270 CR_ASEQDONT = 0x0 << 10,
271 CR_ASEQUP = 0x1 << 10,
272 CR_ASEQDOWN = 0x2 << 10,
273 CR_ASEQ_MASK = 0x3 << 10,
274 CR_PSIZE8 = (1 << 8),
275 CR_PSIZE16 = (2 << 8),
276 CR_PSIZE32 = (3 << 8),
277 CR_PORTCPU = (0 << 6),
278 CR_PORTIO = (1 << 6),
279 CR_PORTVXI = (2 << 6),
280 CR_PORTMXI = (3 << 6),
281 CR_AMDEVICE = (1 << 0),
282 };
CR_REQS(int source)283 static inline int CR_REQS(int source)
284 {
285 return (source & 0x7) << 16;
286 };
287
CR_REQSDRQ(unsigned drq_line)288 static inline int CR_REQSDRQ(unsigned drq_line)
289 {
290 /* This also works on m-series when
291 using channels (drq_line) 4 or 5. */
292 return CR_REQS((drq_line & 0x3) | 0x4);
293 }
294
CR_RL(unsigned int retry_limit)295 static inline int CR_RL(unsigned int retry_limit)
296 {
297 int value = 0;
298
299 if (retry_limit)
300 value = 1 + ilog2(retry_limit);
301 if (value > 0x7)
302 value = 0x7;
303 return (value & 0x7) << 21;
304 }
305
306 enum CHSR_bits {
307 CHSR_INT = (1 << 31),
308 CHSR_LPAUSES = (1 << 29),
309 CHSR_SARS = (1 << 27),
310 CHSR_DONE = (1 << 25),
311 CHSR_MRDY = (1 << 23),
312 CHSR_DRDY = (1 << 21),
313 CHSR_LINKC = (1 << 19),
314 CHSR_CONTS_RB = (1 << 17),
315 CHSR_ERROR = (1 << 15),
316 CHSR_SABORT = (1 << 14),
317 CHSR_HABORT = (1 << 13),
318 CHSR_STOPS = (1 << 12),
319 CHSR_OPERR_mask = (3 << 10),
320 CHSR_OPERR_NOERROR = (0 << 10),
321 CHSR_OPERR_FIFOERROR = (1 << 10),
322 CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
323 CHSR_XFERR = (1 << 9),
324 CHSR_END = (1 << 8),
325 CHSR_DRQ1 = (1 << 7),
326 CHSR_DRQ0 = (1 << 6),
327 CHSR_LxERR_mask = (3 << 4),
328 CHSR_LBERR = (1 << 4),
329 CHSR_LRERR = (2 << 4),
330 CHSR_LOERR = (3 << 4),
331 CHSR_MxERR_mask = (3 << 2),
332 CHSR_MBERR = (1 << 2),
333 CHSR_MRERR = (2 << 2),
334 CHSR_MOERR = (3 << 2),
335 CHSR_DxERR_mask = (3 << 0),
336 CHSR_DBERR = (1 << 0),
337 CHSR_DRERR = (2 << 0),
338 CHSR_DOERR = (3 << 0),
339 };
340
mite_dma_reset(struct mite_channel * mite_chan)341 static inline void mite_dma_reset(struct mite_channel *mite_chan)
342 {
343 writel(CHOR_DMARESET | CHOR_FRESET,
344 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
345 };
346
347 #endif
348