1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __LINUX_MTD_SPI_NOR_H 11 #define __LINUX_MTD_SPI_NOR_H 12 13 /* 14 * Note on opcode nomenclature: some opcodes have a format like 15 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 16 * of I/O lines used for the opcode, address, and data (respectively). The 17 * FUNCTION has an optional suffix of '4', to represent an opcode which 18 * requires a 4-byte (32-bit) address. 19 */ 20 21 /* Flash opcodes. */ 22 #define SPINOR_OP_WREN 0x06 /* Write enable */ 23 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 24 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 25 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 26 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 27 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ 28 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ 29 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 30 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 31 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 32 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 33 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 34 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 35 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 36 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 37 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 38 39 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 40 #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ 41 #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ 42 #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ 43 #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ 44 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 45 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 46 47 /* Used for SST flashes only. */ 48 #define SPINOR_OP_BP 0x02 /* Byte program */ 49 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 50 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 51 52 /* Used for Macronix and Winbond flashes. */ 53 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 54 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 55 56 /* Used for Spansion flashes only. */ 57 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 58 59 /* Used for Micron flashes only. */ 60 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 61 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 62 63 /* Status Register bits. */ 64 #define SR_WIP 1 /* Write in progress */ 65 #define SR_WEL 2 /* Write enable latch */ 66 /* meaning of other SR_* bits may differ between vendors */ 67 #define SR_BP0 4 /* Block protect 0 */ 68 #define SR_BP1 8 /* Block protect 1 */ 69 #define SR_BP2 0x10 /* Block protect 2 */ 70 #define SR_SRWD 0x80 /* SR write protect */ 71 72 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ 73 74 /* Enhanced Volatile Configuration Register bits */ 75 #define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */ 76 77 /* Flag Status Register bits */ 78 #define FSR_READY 0x80 79 80 /* Configuration Register bits. */ 81 #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ 82 83 enum read_mode { 84 SPI_NOR_NORMAL = 0, 85 SPI_NOR_FAST, 86 SPI_NOR_DUAL, 87 SPI_NOR_QUAD, 88 }; 89 90 /** 91 * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer 92 * @wren: command for "Write Enable", or 0x00 for not required 93 * @cmd: command for operation 94 * @cmd_pins: number of pins to send @cmd (1, 2, 4) 95 * @addr: address for operation 96 * @addr_pins: number of pins to send @addr (1, 2, 4) 97 * @addr_width: number of address bytes 98 * (3,4, or 0 for address not required) 99 * @mode: mode data 100 * @mode_pins: number of pins to send @mode (1, 2, 4) 101 * @mode_cycles: number of mode cycles (0 for mode not required) 102 * @dummy_cycles: number of dummy cycles (0 for dummy not required) 103 */ 104 struct spi_nor_xfer_cfg { 105 u8 wren; 106 u8 cmd; 107 u8 cmd_pins; 108 u32 addr; 109 u8 addr_pins; 110 u8 addr_width; 111 u8 mode; 112 u8 mode_pins; 113 u8 mode_cycles; 114 u8 dummy_cycles; 115 }; 116 117 #define SPI_NOR_MAX_CMD_SIZE 8 118 enum spi_nor_ops { 119 SPI_NOR_OPS_READ = 0, 120 SPI_NOR_OPS_WRITE, 121 SPI_NOR_OPS_ERASE, 122 SPI_NOR_OPS_LOCK, 123 SPI_NOR_OPS_UNLOCK, 124 }; 125 126 enum spi_nor_option_flags { 127 SNOR_F_USE_FSR = BIT(0), 128 }; 129 130 /** 131 * struct spi_nor - Structure for defining a the SPI NOR layer 132 * @mtd: point to a mtd_info structure 133 * @lock: the lock for the read/write/erase/lock/unlock operations 134 * @dev: point to a spi device, or a spi nor controller device. 135 * @page_size: the page size of the SPI NOR 136 * @addr_width: number of address bytes 137 * @erase_opcode: the opcode for erasing a sector 138 * @read_opcode: the read opcode 139 * @read_dummy: the dummy needed by the read operation 140 * @program_opcode: the program opcode 141 * @flash_read: the mode of the read 142 * @sst_write_second: used by the SST write operation 143 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 144 * @cfg: used by the read_xfer/write_xfer 145 * @cmd_buf: used by the write_reg 146 * @prepare: [OPTIONAL] do some preparations for the 147 * read/write/erase/lock/unlock operations 148 * @unprepare: [OPTIONAL] do some post work after the 149 * read/write/erase/lock/unlock operations 150 * @read_xfer: [OPTIONAL] the read fundamental primitive 151 * @write_xfer: [OPTIONAL] the writefundamental primitive 152 * @read_reg: [DRIVER-SPECIFIC] read out the register 153 * @write_reg: [DRIVER-SPECIFIC] write data to the register 154 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 155 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 156 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 157 * at the offset @offs 158 * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 159 * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 160 * @priv: the private data 161 */ 162 struct spi_nor { 163 struct mtd_info *mtd; 164 struct mutex lock; 165 struct device *dev; 166 u32 page_size; 167 u8 addr_width; 168 u8 erase_opcode; 169 u8 read_opcode; 170 u8 read_dummy; 171 u8 program_opcode; 172 enum read_mode flash_read; 173 bool sst_write_second; 174 u32 flags; 175 struct spi_nor_xfer_cfg cfg; 176 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 177 178 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 179 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 180 int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, 181 u8 *buf, size_t len); 182 int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, 183 u8 *buf, size_t len); 184 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 185 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, 186 int write_enable); 187 188 int (*read)(struct spi_nor *nor, loff_t from, 189 size_t len, size_t *retlen, u_char *read_buf); 190 void (*write)(struct spi_nor *nor, loff_t to, 191 size_t len, size_t *retlen, const u_char *write_buf); 192 int (*erase)(struct spi_nor *nor, loff_t offs); 193 194 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 195 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 196 197 void *priv; 198 }; 199 200 /** 201 * spi_nor_scan() - scan the SPI NOR 202 * @nor: the spi_nor structure 203 * @name: the chip type name 204 * @mode: the read mode supported by the driver 205 * 206 * The drivers can use this fuction to scan the SPI NOR. 207 * In the scanning, it will try to get all the necessary information to 208 * fill the mtd_info{} and the spi_nor{}. 209 * 210 * The chip type name can be provided through the @name parameter. 211 * 212 * Return: 0 for success, others for failure. 213 */ 214 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode); 215 216 #endif 217