1 /*
2 * TI clock drivers support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #ifndef __LINUX_CLK_TI_H__
16 #define __LINUX_CLK_TI_H__
17
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20
21 /**
22 * struct dpll_data - DPLL registers and integration data
23 * @mult_div1_reg: register containing the DPLL M and N bitfields
24 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
25 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
26 * @clk_bypass: struct clk pointer to the clock's bypass clock input
27 * @clk_ref: struct clk pointer to the clock's reference clock input
28 * @control_reg: register containing the DPLL mode bitfield
29 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
30 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
31 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
32 * @last_rounded_m4xen: cache of the last M4X result of
33 * omap4_dpll_regm4xen_round_rate()
34 * @last_rounded_lpmode: cache of the last lpmode result of
35 * omap4_dpll_lpmode_recalc()
36 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
37 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
38 * @min_divider: minimum valid non-bypass divider value (actual)
39 * @max_divider: maximum valid non-bypass divider value (actual)
40 * @modes: possible values of @enable_mask
41 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
42 * @idlest_reg: register containing the DPLL idle status bitfield
43 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
44 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
45 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
46 * @dcc_rate: rate atleast which DCC @dcc_mask must be set
47 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
48 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
49 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
50 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
51 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
52 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
53 * @flags: DPLL type/features (see below)
54 *
55 * Possible values for @flags:
56 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
57 *
58 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
59 *
60 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
61 * correct to only have one @clk_bypass pointer.
62 *
63 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
64 * @last_rounded_n) should be separated from the runtime-fixed fields
65 * and placed into a different structure, so that the runtime-fixed data
66 * can be placed into read-only space.
67 */
68 struct dpll_data {
69 void __iomem *mult_div1_reg;
70 u32 mult_mask;
71 u32 div1_mask;
72 struct clk *clk_bypass;
73 struct clk *clk_ref;
74 void __iomem *control_reg;
75 u32 enable_mask;
76 unsigned long last_rounded_rate;
77 u16 last_rounded_m;
78 u8 last_rounded_m4xen;
79 u8 last_rounded_lpmode;
80 u16 max_multiplier;
81 u8 last_rounded_n;
82 u8 min_divider;
83 u16 max_divider;
84 u8 modes;
85 void __iomem *autoidle_reg;
86 void __iomem *idlest_reg;
87 u32 autoidle_mask;
88 u32 freqsel_mask;
89 u32 idlest_mask;
90 u32 dco_mask;
91 u32 sddiv_mask;
92 u32 dcc_mask;
93 unsigned long dcc_rate;
94 u32 lpmode_mask;
95 u32 m4xen_mask;
96 u8 auto_recal_bit;
97 u8 recal_en_bit;
98 u8 recal_st_bit;
99 u8 flags;
100 };
101
102 struct clk_hw_omap;
103
104 /**
105 * struct clk_hw_omap_ops - OMAP clk ops
106 * @find_idlest: find idlest register information for a clock
107 * @find_companion: find companion clock register information for a clock,
108 * basically converts CM_ICLKEN* <-> CM_FCLKEN*
109 * @allow_idle: enables autoidle hardware functionality for a clock
110 * @deny_idle: prevent autoidle hardware functionality for a clock
111 */
112 struct clk_hw_omap_ops {
113 void (*find_idlest)(struct clk_hw_omap *oclk,
114 void __iomem **idlest_reg,
115 u8 *idlest_bit, u8 *idlest_val);
116 void (*find_companion)(struct clk_hw_omap *oclk,
117 void __iomem **other_reg,
118 u8 *other_bit);
119 void (*allow_idle)(struct clk_hw_omap *oclk);
120 void (*deny_idle)(struct clk_hw_omap *oclk);
121 };
122
123 /**
124 * struct clk_hw_omap - OMAP struct clk
125 * @node: list_head connecting this clock into the full clock list
126 * @enable_reg: register to write to enable the clock (see @enable_bit)
127 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
128 * @flags: see "struct clk.flags possibilities" above
129 * @clksel_reg: for clksel clks, register va containing src/divisor select
130 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
131 * @clksel: for clksel clks, pointer to struct clksel for this clock
132 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
133 * @clkdm_name: clockdomain name that this clock is contained in
134 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
135 * @ops: clock ops for this clock
136 */
137 struct clk_hw_omap {
138 struct clk_hw hw;
139 struct list_head node;
140 unsigned long fixed_rate;
141 u8 fixed_div;
142 void __iomem *enable_reg;
143 u8 enable_bit;
144 u8 flags;
145 void __iomem *clksel_reg;
146 u32 clksel_mask;
147 const struct clksel *clksel;
148 struct dpll_data *dpll_data;
149 const char *clkdm_name;
150 struct clockdomain *clkdm;
151 const struct clk_hw_omap_ops *ops;
152 };
153
154 /*
155 * struct clk_hw_omap.flags possibilities
156 *
157 * XXX document the rest of the clock flags here
158 *
159 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
160 * with 32bit ops, by default OMAP1 uses 16bit ops.
161 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
162 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
163 * clock is put to no-idle mode.
164 * ENABLE_ON_INIT: Clock is enabled on init.
165 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
166 * disable. This inverts the behavior making '0' enable and '1' disable.
167 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
168 * bits share the same register. This flag allows the
169 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
170 * should be used. This is a temporary solution - a better approach
171 * would be to associate clock type-specific data with the clock,
172 * similar to the struct dpll_data approach.
173 * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
174 */
175 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
176 #define CLOCK_IDLE_CONTROL (1 << 1)
177 #define CLOCK_NO_IDLE_PARENT (1 << 2)
178 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
179 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
180 #define CLOCK_CLKOUTX2 (1 << 5)
181 #define MEMMAP_ADDRESSING (1 << 6)
182
183 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
184 #define DPLL_LOW_POWER_STOP 0x1
185 #define DPLL_LOW_POWER_BYPASS 0x5
186 #define DPLL_LOCKED 0x7
187
188 /* DPLL Type and DCO Selection Flags */
189 #define DPLL_J_TYPE 0x1
190
191 /* Static memmap indices */
192 enum {
193 TI_CLKM_CM = 0,
194 TI_CLKM_CM2,
195 TI_CLKM_PRM,
196 TI_CLKM_SCRM,
197 TI_CLKM_CTRL,
198 CLK_MAX_MEMMAPS
199 };
200
201 /**
202 * struct clk_omap_reg - OMAP register declaration
203 * @offset: offset from the master IP module base address
204 * @index: index of the master IP module
205 */
206 struct clk_omap_reg {
207 u16 offset;
208 u16 index;
209 };
210
211 /**
212 * struct ti_clk_ll_ops - low-level ops for clocks
213 * @clk_readl: pointer to register read function
214 * @clk_writel: pointer to register write function
215 * @clkdm_clk_enable: pointer to clockdomain enable function
216 * @clkdm_clk_disable: pointer to clockdomain disable function
217 * @cm_wait_module_ready: pointer to CM module wait ready function
218 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
219 *
220 * Low-level ops are generally used by the basic clock types (clk-gate,
221 * clk-mux, clk-divider etc.) to provide support for various low-level
222 * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
223 * by board code. Low-level ops also contain some other platform specific
224 * operations not provided directly by clock drivers.
225 */
226 struct ti_clk_ll_ops {
227 u32 (*clk_readl)(void __iomem *reg);
228 void (*clk_writel)(u32 val, void __iomem *reg);
229 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
230 int (*clkdm_clk_disable)(struct clockdomain *clkdm,
231 struct clk *clk);
232 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
233 u8 idlest_shift);
234 int (*cm_split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
235 u8 *idlest_reg_id);
236 };
237
238 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
239
240 void omap2_init_clk_clkdm(struct clk_hw *clk);
241 int omap2_clk_disable_autoidle_all(void);
242 int omap2_clk_enable_autoidle_all(void);
243 int omap2_clk_allow_idle(struct clk *clk);
244 int omap2_clk_deny_idle(struct clk *clk);
245 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
246 unsigned long parent_rate);
247 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
248 unsigned long parent_rate);
249 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
250 void omap2xxx_clkt_vps_init(void);
251 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
252
253 void ti_dt_clk_init_retry_clks(void);
254 void ti_dt_clockdomains_setup(void);
255 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
256
257 struct regmap;
258
259 int omap2_clk_provider_init(struct device_node *parent, int index,
260 struct regmap *syscon, void __iomem *mem);
261 void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
262
263 int omap3430_dt_clk_init(void);
264 int omap3630_dt_clk_init(void);
265 int am35xx_dt_clk_init(void);
266 int dm814x_dt_clk_init(void);
267 int dm816x_dt_clk_init(void);
268 int omap4xxx_dt_clk_init(void);
269 int omap5xxx_dt_clk_init(void);
270 int dra7xx_dt_clk_init(void);
271 int am33xx_dt_clk_init(void);
272 int am43xx_dt_clk_init(void);
273 int omap2420_dt_clk_init(void);
274 int omap2430_dt_clk_init(void);
275
276 struct ti_clk_features {
277 u32 flags;
278 long fint_min;
279 long fint_max;
280 long fint_band1_max;
281 long fint_band2_min;
282 u8 dpll_bypass_vals;
283 u8 cm_idlest_val;
284 };
285
286 #define TI_CLK_DPLL_HAS_FREQSEL BIT(0)
287 #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
288 #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
289
290 void ti_clk_setup_features(struct ti_clk_features *features);
291 const struct ti_clk_features *ti_clk_get_features(void);
292
293 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
294
295 #ifdef CONFIG_ATAGS
296 int omap3430_clk_legacy_init(void);
297 int omap3430es1_clk_legacy_init(void);
298 int omap36xx_clk_legacy_init(void);
299 int am35xx_clk_legacy_init(void);
300 #else
omap3430_clk_legacy_init(void)301 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
omap3430es1_clk_legacy_init(void)302 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
omap36xx_clk_legacy_init(void)303 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
am35xx_clk_legacy_init(void)304 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
305 #endif
306
307
308 #endif
309