1 /*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/pci.h>
35 #include <linux/delay.h>
36
37 #include "ipath_kernel.h"
38 #include "ipath_verbs.h"
39 #include "ipath_common.h"
40
41
42 /*
43 * Called when we might have an error that is specific to a particular
44 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
45 */
ipath_disarm_senderrbufs(struct ipath_devdata * dd)46 void ipath_disarm_senderrbufs(struct ipath_devdata *dd)
47 {
48 u32 piobcnt;
49 unsigned long sbuf[4];
50 /*
51 * it's possible that sendbuffererror could have bits set; might
52 * have already done this as a result of hardware error handling
53 */
54 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
55 /* read these before writing errorclear */
56 sbuf[0] = ipath_read_kreg64(
57 dd, dd->ipath_kregs->kr_sendbuffererror);
58 sbuf[1] = ipath_read_kreg64(
59 dd, dd->ipath_kregs->kr_sendbuffererror + 1);
60 if (piobcnt > 128)
61 sbuf[2] = ipath_read_kreg64(
62 dd, dd->ipath_kregs->kr_sendbuffererror + 2);
63 if (piobcnt > 192)
64 sbuf[3] = ipath_read_kreg64(
65 dd, dd->ipath_kregs->kr_sendbuffererror + 3);
66 else
67 sbuf[3] = 0;
68
69 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
70 int i;
71 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
72 time_after(dd->ipath_lastcancel, jiffies)) {
73 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
74 "SendbufErrs %lx %lx", sbuf[0],
75 sbuf[1]);
76 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
77 printk(" %lx %lx ", sbuf[2], sbuf[3]);
78 printk("\n");
79 }
80
81 for (i = 0; i < piobcnt; i++)
82 if (test_bit(i, sbuf))
83 ipath_disarm_piobufs(dd, i, 1);
84 /* ignore armlaunch errs for a bit */
85 dd->ipath_lastcancel = jiffies+3;
86 }
87 }
88
89
90 /* These are all rcv-related errors which we want to count for stats */
91 #define E_SUM_PKTERRS \
92 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
93 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
94 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
95 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
96 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
97 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
98
99 /* These are all send-related errors which we want to count for stats */
100 #define E_SUM_ERRS \
101 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
102 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
103 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
104 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
105 INFINIPATH_E_INVALIDADDR)
106
107 /*
108 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
109 * errors not related to freeze and cancelling buffers. Can't ignore
110 * armlaunch because could get more while still cleaning up, and need
111 * to cancel those as they happen.
112 */
113 #define E_SPKT_ERRS_IGNORE \
114 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
115 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \
116 INFINIPATH_E_SPKTLEN)
117
118 /*
119 * these are errors that can occur when the link changes state while
120 * a packet is being sent or received. This doesn't cover things
121 * like EBP or VCRC that can be the result of a sending having the
122 * link change state, so we receive a "known bad" packet.
123 */
124 #define E_SUM_LINK_PKTERRS \
125 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
126 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
127 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
128 INFINIPATH_E_RUNEXPCHAR)
129
handle_e_sum_errs(struct ipath_devdata * dd,ipath_err_t errs)130 static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
131 {
132 u64 ignore_this_time = 0;
133
134 ipath_disarm_senderrbufs(dd);
135 if ((errs & E_SUM_LINK_PKTERRS) &&
136 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
137 /*
138 * This can happen when SMA is trying to bring the link
139 * up, but the IB link changes state at the "wrong" time.
140 * The IB logic then complains that the packet isn't
141 * valid. We don't want to confuse people, so we just
142 * don't print them, except at debug
143 */
144 ipath_dbg("Ignoring packet errors %llx, because link not "
145 "ACTIVE\n", (unsigned long long) errs);
146 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
147 }
148
149 return ignore_this_time;
150 }
151
152 /* generic hw error messages... */
153 #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
154 { \
155 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
156 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
157 .msg = "TXE " #a " Memory Parity" \
158 }
159 #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
160 { \
161 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
162 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
163 .msg = "RXE " #a " Memory Parity" \
164 }
165
166 static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
167 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
168 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
169
170 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
171 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
172 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
173
174 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
175 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
176 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
177 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
178 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
179 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
180 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
181 };
182
183 /**
184 * ipath_format_hwmsg - format a single hwerror message
185 * @msg message buffer
186 * @msgl length of message buffer
187 * @hwmsg message to add to message buffer
188 */
ipath_format_hwmsg(char * msg,size_t msgl,const char * hwmsg)189 static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
190 {
191 strlcat(msg, "[", msgl);
192 strlcat(msg, hwmsg, msgl);
193 strlcat(msg, "]", msgl);
194 }
195
196 /**
197 * ipath_format_hwerrors - format hardware error messages for display
198 * @hwerrs hardware errors bit vector
199 * @hwerrmsgs hardware error descriptions
200 * @nhwerrmsgs number of hwerrmsgs
201 * @msg message buffer
202 * @msgl message buffer length
203 */
ipath_format_hwerrors(u64 hwerrs,const struct ipath_hwerror_msgs * hwerrmsgs,size_t nhwerrmsgs,char * msg,size_t msgl)204 void ipath_format_hwerrors(u64 hwerrs,
205 const struct ipath_hwerror_msgs *hwerrmsgs,
206 size_t nhwerrmsgs,
207 char *msg, size_t msgl)
208 {
209 int i;
210 const int glen =
211 ARRAY_SIZE(ipath_generic_hwerror_msgs);
212
213 for (i=0; i<glen; i++) {
214 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
215 ipath_format_hwmsg(msg, msgl,
216 ipath_generic_hwerror_msgs[i].msg);
217 }
218 }
219
220 for (i=0; i<nhwerrmsgs; i++) {
221 if (hwerrs & hwerrmsgs[i].mask) {
222 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
223 }
224 }
225 }
226
227 /* return the strings for the most common link states */
ib_linkstate(struct ipath_devdata * dd,u64 ibcs)228 static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
229 {
230 char *ret;
231 u32 state;
232
233 state = ipath_ib_state(dd, ibcs);
234 if (state == dd->ib_init)
235 ret = "Init";
236 else if (state == dd->ib_arm)
237 ret = "Arm";
238 else if (state == dd->ib_active)
239 ret = "Active";
240 else
241 ret = "Down";
242 return ret;
243 }
244
signal_ib_event(struct ipath_devdata * dd,enum ib_event_type ev)245 void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev)
246 {
247 struct ib_event event;
248
249 event.device = &dd->verbs_dev->ibdev;
250 event.element.port_num = 1;
251 event.event = ev;
252 ib_dispatch_event(&event);
253 }
254
handle_e_ibstatuschanged(struct ipath_devdata * dd,ipath_err_t errs)255 static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
256 ipath_err_t errs)
257 {
258 u32 ltstate, lstate, ibstate, lastlstate;
259 u32 init = dd->ib_init;
260 u32 arm = dd->ib_arm;
261 u32 active = dd->ib_active;
262 const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
263
264 lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */
265 ibstate = ipath_ib_state(dd, ibcs);
266 /* linkstate at last interrupt */
267 lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat);
268 ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */
269
270 /*
271 * Since going into a recovery state causes the link state to go
272 * down and since recovery is transitory, it is better if we "miss"
273 * ever seeing the link training state go into recovery (i.e.,
274 * ignore this transition for link state special handling purposes)
275 * without even updating ipath_lastibcstat.
276 */
277 if ((ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN) ||
278 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT) ||
279 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERIDLE))
280 goto done;
281
282 /*
283 * if linkstate transitions into INIT from any of the various down
284 * states, or if it transitions from any of the up (INIT or better)
285 * states into any of the down states (except link recovery), then
286 * call the chip-specific code to take appropriate actions.
287 */
288 if (lstate >= INFINIPATH_IBCS_L_STATE_INIT &&
289 lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) {
290 /* transitioned to UP */
291 if (dd->ipath_f_ib_updown(dd, 1, ibcs)) {
292 /* link came up, so we must no longer be disabled */
293 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
294 ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n");
295 goto skip_ibchange; /* chip-code handled */
296 }
297 } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT ||
298 (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) &&
299 ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT &&
300 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
301 int handled;
302 handled = dd->ipath_f_ib_updown(dd, 0, ibcs);
303 dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY;
304 if (handled) {
305 ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n");
306 goto skip_ibchange; /* chip-code handled */
307 }
308 }
309
310 /*
311 * Significant enough to always print and get into logs, if it was
312 * unexpected. If it was a requested state change, we'll have
313 * already cleared the flags, so we won't print this warning
314 */
315 if ((ibstate != arm && ibstate != active) &&
316 (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
317 dev_info(&dd->pcidev->dev, "Link state changed from %s "
318 "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ?
319 "ARM" : "ACTIVE", ib_linkstate(dd, ibcs));
320 }
321
322 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
323 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
324 u32 lastlts;
325 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
326 /*
327 * Ignore cycling back and forth from Polling.Active to
328 * Polling.Quiet while waiting for the other end of the link
329 * to come up, except to try and decide if we are connected
330 * to a live IB device or not. We will cycle back and
331 * forth between them if no cable is plugged in, the other
332 * device is powered off or disabled, etc.
333 */
334 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
335 lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
336 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
337 (++dd->ipath_ibpollcnt == 40)) {
338 dd->ipath_flags |= IPATH_NOCABLE;
339 *dd->ipath_statusp |=
340 IPATH_STATUS_IB_NOCABLE;
341 ipath_cdbg(LINKVERB, "Set NOCABLE\n");
342 }
343 ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n",
344 ipath_ibcstatus_str[ltstate], ibstate);
345 goto skip_ibchange;
346 }
347 }
348
349 dd->ipath_ibpollcnt = 0; /* not poll*, now */
350 ipath_stats.sps_iblink++;
351
352 if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) {
353 u64 linkrecov;
354 linkrecov = ipath_snap_cntr(dd,
355 dd->ipath_cregs->cr_iblinkerrrecovcnt);
356 if (linkrecov != dd->ipath_lastlinkrecov) {
357 ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n",
358 (unsigned long long) ibcs,
359 ib_linkstate(dd, ibcs),
360 ipath_ibcstatus_str[ltstate],
361 (unsigned long long) linkrecov);
362 /* and no more until active again */
363 dd->ipath_lastlinkrecov = 0;
364 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
365 goto skip_ibchange;
366 }
367 }
368
369 if (ibstate == init || ibstate == arm || ibstate == active) {
370 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
371 if (ibstate == init || ibstate == arm) {
372 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
373 if (dd->ipath_flags & IPATH_LINKACTIVE)
374 signal_ib_event(dd, IB_EVENT_PORT_ERR);
375 }
376 if (ibstate == arm) {
377 dd->ipath_flags |= IPATH_LINKARMED;
378 dd->ipath_flags &= ~(IPATH_LINKUNK |
379 IPATH_LINKINIT | IPATH_LINKDOWN |
380 IPATH_LINKACTIVE | IPATH_NOCABLE);
381 ipath_hol_down(dd);
382 } else if (ibstate == init) {
383 /*
384 * set INIT and DOWN. Down is checked by
385 * most of the other code, but INIT is
386 * useful to know in a few places.
387 */
388 dd->ipath_flags |= IPATH_LINKINIT |
389 IPATH_LINKDOWN;
390 dd->ipath_flags &= ~(IPATH_LINKUNK |
391 IPATH_LINKARMED | IPATH_LINKACTIVE |
392 IPATH_NOCABLE);
393 ipath_hol_down(dd);
394 } else { /* active */
395 dd->ipath_lastlinkrecov = ipath_snap_cntr(dd,
396 dd->ipath_cregs->cr_iblinkerrrecovcnt);
397 *dd->ipath_statusp |=
398 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
399 dd->ipath_flags |= IPATH_LINKACTIVE;
400 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
401 | IPATH_LINKDOWN | IPATH_LINKARMED |
402 IPATH_NOCABLE);
403 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
404 ipath_restart_sdma(dd);
405 signal_ib_event(dd, IB_EVENT_PORT_ACTIVE);
406 /* LED active not handled in chip _f_updown */
407 dd->ipath_f_setextled(dd, lstate, ltstate);
408 ipath_hol_up(dd);
409 }
410
411 /*
412 * print after we've already done the work, so as not to
413 * delay the state changes and notifications, for debugging
414 */
415 if (lstate == lastlstate)
416 ipath_cdbg(LINKVERB, "Unchanged from last: %s "
417 "(%x)\n", ib_linkstate(dd, ibcs), ibstate);
418 else
419 ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n",
420 dd->ipath_unit, ib_linkstate(dd, ibcs),
421 ipath_ibcstatus_str[ltstate], ibstate);
422 } else { /* down */
423 if (dd->ipath_flags & IPATH_LINKACTIVE)
424 signal_ib_event(dd, IB_EVENT_PORT_ERR);
425 dd->ipath_flags |= IPATH_LINKDOWN;
426 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
427 | IPATH_LINKACTIVE |
428 IPATH_LINKARMED);
429 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
430 dd->ipath_lli_counter = 0;
431
432 if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN)
433 ipath_cdbg(VERBOSE, "Unit %u link state down "
434 "(state 0x%x), from %s\n",
435 dd->ipath_unit, lstate,
436 ib_linkstate(dd, dd->ipath_lastibcstat));
437 else
438 ipath_cdbg(LINKVERB, "Unit %u link state changed "
439 "to %s (0x%x) from down (%x)\n",
440 dd->ipath_unit,
441 ipath_ibcstatus_str[ltstate],
442 ibstate, lastlstate);
443 }
444
445 skip_ibchange:
446 dd->ipath_lastibcstat = ibcs;
447 done:
448 return;
449 }
450
handle_supp_msgs(struct ipath_devdata * dd,unsigned supp_msgs,char * msg,u32 msgsz)451 static void handle_supp_msgs(struct ipath_devdata *dd,
452 unsigned supp_msgs, char *msg, u32 msgsz)
453 {
454 /*
455 * Print the message unless it's ibc status change only, which
456 * happens so often we never want to count it.
457 */
458 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
459 int iserr;
460 ipath_err_t mask;
461 iserr = ipath_decode_err(dd, msg, msgsz,
462 dd->ipath_lasterror &
463 ~INFINIPATH_E_IBSTATUSCHANGED);
464
465 mask = INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
466 INFINIPATH_E_PKTERRS | INFINIPATH_E_SDMADISABLED;
467
468 /* if we're in debug, then don't mask SDMADISABLED msgs */
469 if (ipath_debug & __IPATH_DBG)
470 mask &= ~INFINIPATH_E_SDMADISABLED;
471
472 if (dd->ipath_lasterror & ~mask)
473 ipath_dev_err(dd, "Suppressed %u messages for "
474 "fast-repeating errors (%s) (%llx)\n",
475 supp_msgs, msg,
476 (unsigned long long)
477 dd->ipath_lasterror);
478 else {
479 /*
480 * rcvegrfull and rcvhdrqfull are "normal", for some
481 * types of processes (mostly benchmarks) that send
482 * huge numbers of messages, while not processing
483 * them. So only complain about these at debug
484 * level.
485 */
486 if (iserr)
487 ipath_dbg("Suppressed %u messages for %s\n",
488 supp_msgs, msg);
489 else
490 ipath_cdbg(ERRPKT,
491 "Suppressed %u messages for %s\n",
492 supp_msgs, msg);
493 }
494 }
495 }
496
handle_frequent_errors(struct ipath_devdata * dd,ipath_err_t errs,char * msg,u32 msgsz,int * noprint)497 static unsigned handle_frequent_errors(struct ipath_devdata *dd,
498 ipath_err_t errs, char *msg,
499 u32 msgsz, int *noprint)
500 {
501 unsigned long nc;
502 static unsigned long nextmsg_time;
503 static unsigned nmsgs, supp_msgs;
504
505 /*
506 * Throttle back "fast" messages to no more than 10 per 5 seconds.
507 * This isn't perfect, but it's a reasonable heuristic. If we get
508 * more than 10, give a 6x longer delay.
509 */
510 nc = jiffies;
511 if (nmsgs > 10) {
512 if (time_before(nc, nextmsg_time)) {
513 *noprint = 1;
514 if (!supp_msgs++)
515 nextmsg_time = nc + HZ * 3;
516 } else if (supp_msgs) {
517 handle_supp_msgs(dd, supp_msgs, msg, msgsz);
518 supp_msgs = 0;
519 nmsgs = 0;
520 }
521 } else if (!nmsgs++ || time_after(nc, nextmsg_time)) {
522 nextmsg_time = nc + HZ / 2;
523 }
524
525 return supp_msgs;
526 }
527
handle_sdma_errors(struct ipath_devdata * dd,ipath_err_t errs)528 static void handle_sdma_errors(struct ipath_devdata *dd, ipath_err_t errs)
529 {
530 unsigned long flags;
531 int expected;
532
533 if (ipath_debug & __IPATH_DBG) {
534 char msg[128];
535 ipath_decode_err(dd, msg, sizeof msg, errs &
536 INFINIPATH_E_SDMAERRS);
537 ipath_dbg("errors %lx (%s)\n", (unsigned long)errs, msg);
538 }
539 if (ipath_debug & __IPATH_VERBDBG) {
540 unsigned long tl, hd, status, lengen;
541 tl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_senddmatail);
542 hd = ipath_read_kreg64(dd, dd->ipath_kregs->kr_senddmahead);
543 status = ipath_read_kreg64(dd
544 , dd->ipath_kregs->kr_senddmastatus);
545 lengen = ipath_read_kreg64(dd,
546 dd->ipath_kregs->kr_senddmalengen);
547 ipath_cdbg(VERBOSE, "sdma tl 0x%lx hd 0x%lx status 0x%lx "
548 "lengen 0x%lx\n", tl, hd, status, lengen);
549 }
550
551 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
552 __set_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status);
553 expected = test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
554 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
555 if (!expected)
556 ipath_cancel_sends(dd, 1);
557 }
558
handle_sdma_intr(struct ipath_devdata * dd,u64 istat)559 static void handle_sdma_intr(struct ipath_devdata *dd, u64 istat)
560 {
561 unsigned long flags;
562 int expected;
563
564 if ((istat & INFINIPATH_I_SDMAINT) &&
565 !test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
566 ipath_sdma_intr(dd);
567
568 if (istat & INFINIPATH_I_SDMADISABLED) {
569 expected = test_bit(IPATH_SDMA_ABORTING,
570 &dd->ipath_sdma_status);
571 ipath_dbg("%s SDmaDisabled intr\n",
572 expected ? "expected" : "unexpected");
573 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
574 __set_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status);
575 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
576 if (!expected)
577 ipath_cancel_sends(dd, 1);
578 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
579 tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
580 }
581 }
582
handle_hdrq_full(struct ipath_devdata * dd)583 static int handle_hdrq_full(struct ipath_devdata *dd)
584 {
585 int chkerrpkts = 0;
586 u32 hd, tl;
587 u32 i;
588
589 ipath_stats.sps_hdrqfull++;
590 for (i = 0; i < dd->ipath_cfgports; i++) {
591 struct ipath_portdata *pd = dd->ipath_pd[i];
592
593 if (i == 0) {
594 /*
595 * For kernel receive queues, we just want to know
596 * if there are packets in the queue that we can
597 * process.
598 */
599 if (pd->port_head != ipath_get_hdrqtail(pd))
600 chkerrpkts |= 1 << i;
601 continue;
602 }
603
604 /* Skip if user context is not open */
605 if (!pd || !pd->port_cnt)
606 continue;
607
608 /* Don't report the same point multiple times. */
609 if (dd->ipath_flags & IPATH_NODMA_RTAIL)
610 tl = ipath_read_ureg32(dd, ur_rcvhdrtail, i);
611 else
612 tl = ipath_get_rcvhdrtail(pd);
613 if (tl == pd->port_lastrcvhdrqtail)
614 continue;
615
616 hd = ipath_read_ureg32(dd, ur_rcvhdrhead, i);
617 if (hd == (tl + 1) || (!hd && tl == dd->ipath_hdrqlast)) {
618 pd->port_lastrcvhdrqtail = tl;
619 pd->port_hdrqfull++;
620 /* flush hdrqfull so that poll() sees it */
621 wmb();
622 wake_up_interruptible(&pd->port_wait);
623 }
624 }
625
626 return chkerrpkts;
627 }
628
handle_errors(struct ipath_devdata * dd,ipath_err_t errs)629 static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
630 {
631 char msg[128];
632 u64 ignore_this_time = 0;
633 u64 iserr = 0;
634 int chkerrpkts = 0, noprint = 0;
635 unsigned supp_msgs;
636 int log_idx;
637
638 /*
639 * don't report errors that are masked, either at init
640 * (not set in ipath_errormask), or temporarily (set in
641 * ipath_maskederrs)
642 */
643 errs &= dd->ipath_errormask & ~dd->ipath_maskederrs;
644
645 supp_msgs = handle_frequent_errors(dd, errs, msg, (u32)sizeof msg,
646 &noprint);
647
648 /* do these first, they are most important */
649 if (errs & INFINIPATH_E_HARDWARE) {
650 /* reuse same msg buf */
651 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
652 } else {
653 u64 mask;
654 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
655 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
656 if (errs & mask)
657 ipath_inc_eeprom_err(dd, log_idx, 1);
658 }
659 }
660
661 if (errs & INFINIPATH_E_SDMAERRS)
662 handle_sdma_errors(dd, errs);
663
664 if (!noprint && (errs & ~dd->ipath_e_bitsextant))
665 ipath_dev_err(dd, "error interrupt with unknown errors "
666 "%llx set\n", (unsigned long long)
667 (errs & ~dd->ipath_e_bitsextant));
668
669 if (errs & E_SUM_ERRS)
670 ignore_this_time = handle_e_sum_errs(dd, errs);
671 else if ((errs & E_SUM_LINK_PKTERRS) &&
672 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
673 /*
674 * This can happen when SMA is trying to bring the link
675 * up, but the IB link changes state at the "wrong" time.
676 * The IB logic then complains that the packet isn't
677 * valid. We don't want to confuse people, so we just
678 * don't print them, except at debug
679 */
680 ipath_dbg("Ignoring packet errors %llx, because link not "
681 "ACTIVE\n", (unsigned long long) errs);
682 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
683 }
684
685 if (supp_msgs == 250000) {
686 int s_iserr;
687 /*
688 * It's not entirely reasonable assuming that the errors set
689 * in the last clear period are all responsible for the
690 * problem, but the alternative is to assume it's the only
691 * ones on this particular interrupt, which also isn't great
692 */
693 dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
694
695 dd->ipath_errormask &= ~dd->ipath_maskederrs;
696 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
697 dd->ipath_errormask);
698 s_iserr = ipath_decode_err(dd, msg, sizeof msg,
699 dd->ipath_maskederrs);
700
701 if (dd->ipath_maskederrs &
702 ~(INFINIPATH_E_RRCVEGRFULL |
703 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
704 ipath_dev_err(dd, "Temporarily disabling "
705 "error(s) %llx reporting; too frequent (%s)\n",
706 (unsigned long long) dd->ipath_maskederrs,
707 msg);
708 else {
709 /*
710 * rcvegrfull and rcvhdrqfull are "normal",
711 * for some types of processes (mostly benchmarks)
712 * that send huge numbers of messages, while not
713 * processing them. So only complain about
714 * these at debug level.
715 */
716 if (s_iserr)
717 ipath_dbg("Temporarily disabling reporting "
718 "too frequent queue full errors (%s)\n",
719 msg);
720 else
721 ipath_cdbg(ERRPKT,
722 "Temporarily disabling reporting too"
723 " frequent packet errors (%s)\n",
724 msg);
725 }
726
727 /*
728 * Re-enable the masked errors after around 3 minutes. in
729 * ipath_get_faststats(). If we have a series of fast
730 * repeating but different errors, the interval will keep
731 * stretching out, but that's OK, as that's pretty
732 * catastrophic.
733 */
734 dd->ipath_unmasktime = jiffies + HZ * 180;
735 }
736
737 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
738 if (ignore_this_time)
739 errs &= ~ignore_this_time;
740 if (errs & ~dd->ipath_lasterror) {
741 errs &= ~dd->ipath_lasterror;
742 /* never suppress duplicate hwerrors or ibstatuschange */
743 dd->ipath_lasterror |= errs &
744 ~(INFINIPATH_E_HARDWARE |
745 INFINIPATH_E_IBSTATUSCHANGED);
746 }
747
748 if (errs & INFINIPATH_E_SENDSPECIALTRIGGER) {
749 dd->ipath_spectriggerhit++;
750 ipath_dbg("%lu special trigger hits\n",
751 dd->ipath_spectriggerhit);
752 }
753
754 /* likely due to cancel; so suppress message unless verbose */
755 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
756 time_after(dd->ipath_lastcancel, jiffies)) {
757 /* armlaunch takes precedence; it often causes both. */
758 ipath_cdbg(VERBOSE,
759 "Suppressed %s error (%llx) after sendbuf cancel\n",
760 (errs & INFINIPATH_E_SPIOARMLAUNCH) ?
761 "armlaunch" : "sendpktlen", (unsigned long long)errs);
762 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
763 }
764
765 if (!errs)
766 return 0;
767
768 if (!noprint) {
769 ipath_err_t mask;
770 /*
771 * The ones we mask off are handled specially below
772 * or above. Also mask SDMADISABLED by default as it
773 * is too chatty.
774 */
775 mask = INFINIPATH_E_IBSTATUSCHANGED |
776 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
777 INFINIPATH_E_HARDWARE | INFINIPATH_E_SDMADISABLED;
778
779 /* if we're in debug, then don't mask SDMADISABLED msgs */
780 if (ipath_debug & __IPATH_DBG)
781 mask &= ~INFINIPATH_E_SDMADISABLED;
782
783 ipath_decode_err(dd, msg, sizeof msg, errs & ~mask);
784 } else
785 /* so we don't need if (!noprint) at strlcat's below */
786 *msg = 0;
787
788 if (errs & E_SUM_PKTERRS) {
789 ipath_stats.sps_pkterrs++;
790 chkerrpkts = 1;
791 }
792 if (errs & E_SUM_ERRS)
793 ipath_stats.sps_errs++;
794
795 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
796 ipath_stats.sps_crcerrs++;
797 chkerrpkts = 1;
798 }
799 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
800
801
802 /*
803 * We don't want to print these two as they happen, or we can make
804 * the situation even worse, because it takes so long to print
805 * messages to serial consoles. Kernel ports get printed from
806 * fast_stats, no more than every 5 seconds, user ports get printed
807 * on close
808 */
809 if (errs & INFINIPATH_E_RRCVHDRFULL)
810 chkerrpkts |= handle_hdrq_full(dd);
811 if (errs & INFINIPATH_E_RRCVEGRFULL) {
812 struct ipath_portdata *pd = dd->ipath_pd[0];
813
814 /*
815 * since this is of less importance and not likely to
816 * happen without also getting hdrfull, only count
817 * occurrences; don't check each port (or even the kernel
818 * vs user)
819 */
820 ipath_stats.sps_etidfull++;
821 if (pd->port_head != ipath_get_hdrqtail(pd))
822 chkerrpkts |= 1;
823 }
824
825 /*
826 * do this before IBSTATUSCHANGED, in case both bits set in a single
827 * interrupt; we want the STATUSCHANGE to "win", so we do our
828 * internal copy of state machine correctly
829 */
830 if (errs & INFINIPATH_E_RIBLOSTLINK) {
831 /*
832 * force through block below
833 */
834 errs |= INFINIPATH_E_IBSTATUSCHANGED;
835 ipath_stats.sps_iblink++;
836 dd->ipath_flags |= IPATH_LINKDOWN;
837 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
838 | IPATH_LINKARMED | IPATH_LINKACTIVE);
839 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
840
841 ipath_dbg("Lost link, link now down (%s)\n",
842 ipath_ibcstatus_str[ipath_read_kreg64(dd,
843 dd->ipath_kregs->kr_ibcstatus) & 0xf]);
844 }
845 if (errs & INFINIPATH_E_IBSTATUSCHANGED)
846 handle_e_ibstatuschanged(dd, errs);
847
848 if (errs & INFINIPATH_E_RESET) {
849 if (!noprint)
850 ipath_dev_err(dd, "Got reset, requires re-init "
851 "(unload and reload driver)\n");
852 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
853 /* mark as having had error */
854 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
855 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
856 }
857
858 if (!noprint && *msg) {
859 if (iserr)
860 ipath_dev_err(dd, "%s error\n", msg);
861 }
862 if (dd->ipath_state_wanted & dd->ipath_flags) {
863 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
864 "waking\n", dd->ipath_state_wanted,
865 dd->ipath_flags);
866 wake_up_interruptible(&ipath_state_wait);
867 }
868
869 return chkerrpkts;
870 }
871
872 /*
873 * try to cleanup as much as possible for anything that might have gone
874 * wrong while in freeze mode, such as pio buffers being written by user
875 * processes (causing armlaunch), send errors due to going into freeze mode,
876 * etc., and try to avoid causing extra interrupts while doing so.
877 * Forcibly update the in-memory pioavail register copies after cleanup
878 * because the chip won't do it while in freeze mode (the register values
879 * themselves are kept correct).
880 * Make sure that we don't lose any important interrupts by using the chip
881 * feature that says that writing 0 to a bit in *clear that is set in
882 * *status will cause an interrupt to be generated again (if allowed by
883 * the *mask value).
884 */
ipath_clear_freeze(struct ipath_devdata * dd)885 void ipath_clear_freeze(struct ipath_devdata *dd)
886 {
887 /* disable error interrupts, to avoid confusion */
888 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
889
890 /* also disable interrupts; errormask is sometimes overwriten */
891 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
892
893 ipath_cancel_sends(dd, 1);
894
895 /* clear the freeze, and be sure chip saw it */
896 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
897 dd->ipath_control);
898 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
899
900 /* force in-memory update now we are out of freeze */
901 ipath_force_pio_avail_update(dd);
902
903 /*
904 * force new interrupt if any hwerr, error or interrupt bits are
905 * still set, and clear "safe" send packet errors related to freeze
906 * and cancelling sends. Re-enable error interrupts before possible
907 * force of re-interrupt on pending interrupts.
908 */
909 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL);
910 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
911 E_SPKT_ERRS_IGNORE);
912 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
913 dd->ipath_errormask);
914 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL);
915 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
916 }
917
918
919 /* this is separate to allow for better optimization of ipath_intr() */
920
ipath_bad_intr(struct ipath_devdata * dd,u32 * unexpectp)921 static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp)
922 {
923 /*
924 * sometimes happen during driver init and unload, don't want
925 * to process any interrupts at that point
926 */
927
928 /* this is just a bandaid, not a fix, if something goes badly
929 * wrong */
930 if (++*unexpectp > 100) {
931 if (++*unexpectp > 105) {
932 /*
933 * ok, we must be taking somebody else's interrupts,
934 * due to a messed up mptable and/or PIRQ table, so
935 * unregister the interrupt. We've seen this during
936 * linuxbios development work, and it may happen in
937 * the future again.
938 */
939 if (dd->pcidev && dd->ipath_irq) {
940 ipath_dev_err(dd, "Now %u unexpected "
941 "interrupts, unregistering "
942 "interrupt handler\n",
943 *unexpectp);
944 ipath_dbg("free_irq of irq %d\n",
945 dd->ipath_irq);
946 dd->ipath_f_free_irq(dd);
947 }
948 }
949 if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) {
950 ipath_dev_err(dd, "%u unexpected interrupts, "
951 "disabling interrupts completely\n",
952 *unexpectp);
953 /*
954 * disable all interrupts, something is very wrong
955 */
956 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
957 0ULL);
958 }
959 } else if (*unexpectp > 1)
960 ipath_dbg("Interrupt when not ready, should not happen, "
961 "ignoring\n");
962 }
963
ipath_bad_regread(struct ipath_devdata * dd)964 static noinline void ipath_bad_regread(struct ipath_devdata *dd)
965 {
966 static int allbits;
967
968 /* separate routine, for better optimization of ipath_intr() */
969
970 /*
971 * We print the message and disable interrupts, in hope of
972 * having a better chance of debugging the problem.
973 */
974 ipath_dev_err(dd,
975 "Read of interrupt status failed (all bits set)\n");
976 if (allbits++) {
977 /* disable all interrupts, something is very wrong */
978 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
979 if (allbits == 2) {
980 ipath_dev_err(dd, "Still bad interrupt status, "
981 "unregistering interrupt\n");
982 dd->ipath_f_free_irq(dd);
983 } else if (allbits > 2) {
984 if ((allbits % 10000) == 0)
985 printk(".");
986 } else
987 ipath_dev_err(dd, "Disabling interrupts, "
988 "multiple errors\n");
989 }
990 }
991
handle_layer_pioavail(struct ipath_devdata * dd)992 static void handle_layer_pioavail(struct ipath_devdata *dd)
993 {
994 unsigned long flags;
995 int ret;
996
997 ret = ipath_ib_piobufavail(dd->verbs_dev);
998 if (ret > 0)
999 goto set;
1000
1001 return;
1002 set:
1003 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1004 dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL;
1005 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1006 dd->ipath_sendctrl);
1007 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1008 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1009 }
1010
1011 /*
1012 * Handle receive interrupts for user ports; this means a user
1013 * process was waiting for a packet to arrive, and didn't want
1014 * to poll
1015 */
handle_urcv(struct ipath_devdata * dd,u64 istat)1016 static void handle_urcv(struct ipath_devdata *dd, u64 istat)
1017 {
1018 u64 portr;
1019 int i;
1020 int rcvdint = 0;
1021
1022 /*
1023 * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and
1024 * test_and_clear_bit(IPATH_PORT_WAITING_URG) below
1025 * would both like timely updates of the bits so that
1026 * we don't pass them by unnecessarily. the rmb()
1027 * here ensures that we see them promptly -- the
1028 * corresponding wmb()'s are in ipath_poll_urgent()
1029 * and ipath_poll_next()...
1030 */
1031 rmb();
1032 portr = ((istat >> dd->ipath_i_rcvavail_shift) &
1033 dd->ipath_i_rcvavail_mask) |
1034 ((istat >> dd->ipath_i_rcvurg_shift) &
1035 dd->ipath_i_rcvurg_mask);
1036 for (i = 1; i < dd->ipath_cfgports; i++) {
1037 struct ipath_portdata *pd = dd->ipath_pd[i];
1038
1039 if (portr & (1 << i) && pd && pd->port_cnt) {
1040 if (test_and_clear_bit(IPATH_PORT_WAITING_RCV,
1041 &pd->port_flag)) {
1042 clear_bit(i + dd->ipath_r_intravail_shift,
1043 &dd->ipath_rcvctrl);
1044 wake_up_interruptible(&pd->port_wait);
1045 rcvdint = 1;
1046 } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG,
1047 &pd->port_flag)) {
1048 pd->port_urgent++;
1049 wake_up_interruptible(&pd->port_wait);
1050 }
1051 }
1052 }
1053 if (rcvdint) {
1054 /* only want to take one interrupt, so turn off the rcv
1055 * interrupt for all the ports that we set the rcv_waiting
1056 * (but never for kernel port)
1057 */
1058 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1059 dd->ipath_rcvctrl);
1060 }
1061 }
1062
ipath_intr(int irq,void * data)1063 irqreturn_t ipath_intr(int irq, void *data)
1064 {
1065 struct ipath_devdata *dd = data;
1066 u64 istat, chk0rcv = 0;
1067 ipath_err_t estat = 0;
1068 irqreturn_t ret;
1069 static unsigned unexpected = 0;
1070 u64 kportrbits;
1071
1072 ipath_stats.sps_ints++;
1073
1074 if (dd->ipath_int_counter != (u32) -1)
1075 dd->ipath_int_counter++;
1076
1077 if (!(dd->ipath_flags & IPATH_PRESENT)) {
1078 /*
1079 * This return value is not great, but we do not want the
1080 * interrupt core code to remove our interrupt handler
1081 * because we don't appear to be handling an interrupt
1082 * during a chip reset.
1083 */
1084 return IRQ_HANDLED;
1085 }
1086
1087 /*
1088 * this needs to be flags&initted, not statusp, so we keep
1089 * taking interrupts even after link goes down, etc.
1090 * Also, we *must* clear the interrupt at some point, or we won't
1091 * take it again, which can be real bad for errors, etc...
1092 */
1093
1094 if (!(dd->ipath_flags & IPATH_INITTED)) {
1095 ipath_bad_intr(dd, &unexpected);
1096 ret = IRQ_NONE;
1097 goto bail;
1098 }
1099
1100 istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus);
1101
1102 if (unlikely(!istat)) {
1103 ipath_stats.sps_nullintr++;
1104 ret = IRQ_NONE; /* not our interrupt, or already handled */
1105 goto bail;
1106 }
1107 if (unlikely(istat == -1)) {
1108 ipath_bad_regread(dd);
1109 /* don't know if it was our interrupt or not */
1110 ret = IRQ_NONE;
1111 goto bail;
1112 }
1113
1114 if (unexpected)
1115 unexpected = 0;
1116
1117 if (unlikely(istat & ~dd->ipath_i_bitsextant))
1118 ipath_dev_err(dd,
1119 "interrupt with unknown interrupts %Lx set\n",
1120 (unsigned long long)
1121 istat & ~dd->ipath_i_bitsextant);
1122 else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */
1123 ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n",
1124 (unsigned long long) istat);
1125
1126 if (istat & INFINIPATH_I_ERROR) {
1127 ipath_stats.sps_errints++;
1128 estat = ipath_read_kreg64(dd,
1129 dd->ipath_kregs->kr_errorstatus);
1130 if (!estat)
1131 dev_info(&dd->pcidev->dev, "error interrupt (%Lx), "
1132 "but no error bits set!\n",
1133 (unsigned long long) istat);
1134 else if (estat == -1LL)
1135 /*
1136 * should we try clearing all, or hope next read
1137 * works?
1138 */
1139 ipath_dev_err(dd, "Read of error status failed "
1140 "(all bits set); ignoring\n");
1141 else
1142 chk0rcv |= handle_errors(dd, estat);
1143 }
1144
1145 if (istat & INFINIPATH_I_GPIO) {
1146 /*
1147 * GPIO interrupts fall in two broad classes:
1148 * GPIO_2 indicates (on some HT4xx boards) that a packet
1149 * has arrived for Port 0. Checking for this
1150 * is controlled by flag IPATH_GPIO_INTR.
1151 * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate
1152 * errors that we need to count. Checking for this
1153 * is controlled by flag IPATH_GPIO_ERRINTRS.
1154 */
1155 u32 gpiostatus;
1156 u32 to_clear = 0;
1157
1158 gpiostatus = ipath_read_kreg32(
1159 dd, dd->ipath_kregs->kr_gpio_status);
1160 /* First the error-counter case. */
1161 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
1162 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
1163 /* want to clear the bits we see asserted. */
1164 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
1165
1166 /*
1167 * Count appropriately, clear bits out of our copy,
1168 * as they have been "handled".
1169 */
1170 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
1171 ipath_dbg("FlowCtl on UnsupVL\n");
1172 dd->ipath_rxfc_unsupvl_errs++;
1173 }
1174 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
1175 ipath_dbg("Overrun Threshold exceeded\n");
1176 dd->ipath_overrun_thresh_errs++;
1177 }
1178 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
1179 ipath_dbg("Local Link Integrity error\n");
1180 dd->ipath_lli_errs++;
1181 }
1182 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
1183 }
1184 /* Now the Port0 Receive case */
1185 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
1186 (dd->ipath_flags & IPATH_GPIO_INTR)) {
1187 /*
1188 * GPIO status bit 2 is set, and we expected it.
1189 * clear it and indicate in p0bits.
1190 * This probably only happens if a Port0 pkt
1191 * arrives at _just_ the wrong time, and we
1192 * handle that by seting chk0rcv;
1193 */
1194 to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
1195 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
1196 chk0rcv = 1;
1197 }
1198 if (gpiostatus) {
1199 /*
1200 * Some unexpected bits remain. If they could have
1201 * caused the interrupt, complain and clear.
1202 * To avoid repetition of this condition, also clear
1203 * the mask. It is almost certainly due to error.
1204 */
1205 const u32 mask = (u32) dd->ipath_gpio_mask;
1206
1207 if (mask & gpiostatus) {
1208 ipath_dbg("Unexpected GPIO IRQ bits %x\n",
1209 gpiostatus & mask);
1210 to_clear |= (gpiostatus & mask);
1211 dd->ipath_gpio_mask &= ~(gpiostatus & mask);
1212 ipath_write_kreg(dd,
1213 dd->ipath_kregs->kr_gpio_mask,
1214 dd->ipath_gpio_mask);
1215 }
1216 }
1217 if (to_clear) {
1218 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1219 (u64) to_clear);
1220 }
1221 }
1222
1223 /*
1224 * Clear the interrupt bits we found set, unless they are receive
1225 * related, in which case we already cleared them above, and don't
1226 * want to clear them again, because we might lose an interrupt.
1227 * Clear it early, so we "know" know the chip will have seen this by
1228 * the time we process the queue, and will re-interrupt if necessary.
1229 * The processor itself won't take the interrupt again until we return.
1230 */
1231 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1232
1233 /*
1234 * Handle kernel receive queues before checking for pio buffers
1235 * available since receives can overflow; piobuf waiters can afford
1236 * a few extra cycles, since they were waiting anyway, and user's
1237 * waiting for receive are at the bottom.
1238 */
1239 kportrbits = (1ULL << dd->ipath_i_rcvavail_shift) |
1240 (1ULL << dd->ipath_i_rcvurg_shift);
1241 if (chk0rcv || (istat & kportrbits)) {
1242 istat &= ~kportrbits;
1243 ipath_kreceive(dd->ipath_pd[0]);
1244 }
1245
1246 if (istat & ((dd->ipath_i_rcvavail_mask << dd->ipath_i_rcvavail_shift) |
1247 (dd->ipath_i_rcvurg_mask << dd->ipath_i_rcvurg_shift)))
1248 handle_urcv(dd, istat);
1249
1250 if (istat & (INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED))
1251 handle_sdma_intr(dd, istat);
1252
1253 if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
1254 unsigned long flags;
1255
1256 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1257 dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL;
1258 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1259 dd->ipath_sendctrl);
1260 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1261 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1262
1263 /* always process; sdma verbs uses PIO for acks and VL15 */
1264 handle_layer_pioavail(dd);
1265 }
1266
1267 ret = IRQ_HANDLED;
1268
1269 bail:
1270 return ret;
1271 }
1272