1 /*
2  * Intel(R) Processor Trace PMU driver for perf
3  * Copyright (c) 2013-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * Intel PT is specified in the Intel Architecture Instruction Set Extensions
15  * Programming Reference:
16  * http://software.intel.com/en-us/intel-isa-extensions
17  */
18 
19 #ifndef __INTEL_PT_H__
20 #define __INTEL_PT_H__
21 
22 /*
23  * Single-entry ToPA: when this close to region boundary, switch
24  * buffers to avoid losing data.
25  */
26 #define TOPA_PMI_MARGIN 512
27 
28 /*
29  * Table of Physical Addresses bits
30  */
31 enum topa_sz {
32 	TOPA_4K	= 0,
33 	TOPA_8K,
34 	TOPA_16K,
35 	TOPA_32K,
36 	TOPA_64K,
37 	TOPA_128K,
38 	TOPA_256K,
39 	TOPA_512K,
40 	TOPA_1MB,
41 	TOPA_2MB,
42 	TOPA_4MB,
43 	TOPA_8MB,
44 	TOPA_16MB,
45 	TOPA_32MB,
46 	TOPA_64MB,
47 	TOPA_128MB,
48 	TOPA_SZ_END,
49 };
50 
sizes(enum topa_sz tsz)51 static inline unsigned int sizes(enum topa_sz tsz)
52 {
53 	return 1 << (tsz + 12);
54 };
55 
56 struct topa_entry {
57 	u64	end	: 1;
58 	u64	rsvd0	: 1;
59 	u64	intr	: 1;
60 	u64	rsvd1	: 1;
61 	u64	stop	: 1;
62 	u64	rsvd2	: 1;
63 	u64	size	: 4;
64 	u64	rsvd3	: 2;
65 	u64	base	: 36;
66 	u64	rsvd4	: 16;
67 };
68 
69 #define TOPA_SHIFT 12
70 #define PT_CPUID_LEAVES 2
71 
72 enum pt_capabilities {
73 	PT_CAP_max_subleaf = 0,
74 	PT_CAP_cr3_filtering,
75 	PT_CAP_topa_output,
76 	PT_CAP_topa_multiple_entries,
77 	PT_CAP_payloads_lip,
78 };
79 
80 struct pt_pmu {
81 	struct pmu		pmu;
82 	u32			caps[4 * PT_CPUID_LEAVES];
83 };
84 
85 /**
86  * struct pt_buffer - buffer configuration; one buffer per task_struct or
87  *		cpu, depending on perf event configuration
88  * @cpu:	cpu for per-cpu allocation
89  * @tables:	list of ToPA tables in this buffer
90  * @first:	shorthand for first topa table
91  * @last:	shorthand for last topa table
92  * @cur:	current topa table
93  * @nr_pages:	buffer size in pages
94  * @cur_idx:	current output region's index within @cur table
95  * @output_off:	offset within the current output region
96  * @data_size:	running total of the amount of data in this buffer
97  * @lost:	if data was lost/truncated
98  * @head:	logical write offset inside the buffer
99  * @snapshot:	if this is for a snapshot/overwrite counter
100  * @stop_pos:	STOP topa entry in the buffer
101  * @intr_pos:	INT topa entry in the buffer
102  * @data_pages:	array of pages from perf
103  * @topa_index:	table of topa entries indexed by page offset
104  */
105 struct pt_buffer {
106 	int			cpu;
107 	struct list_head	tables;
108 	struct topa		*first, *last, *cur;
109 	unsigned int		cur_idx;
110 	size_t			output_off;
111 	unsigned long		nr_pages;
112 	local_t			data_size;
113 	local_t			lost;
114 	local64_t		head;
115 	bool			snapshot;
116 	unsigned long		stop_pos, intr_pos;
117 	void			**data_pages;
118 	struct topa_entry	*topa_index[0];
119 };
120 
121 /**
122  * struct pt - per-cpu pt context
123  * @handle:	perf output handle
124  * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
125  */
126 struct pt {
127 	struct perf_output_handle handle;
128 	int			handle_nmi;
129 };
130 
131 #endif /* __INTEL_PT_H__ */
132