1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef LINUX_MMC_DW_MMC_H 15 #define LINUX_MMC_DW_MMC_H 16 17 #include <linux/scatterlist.h> 18 #include <linux/mmc/core.h> 19 #include <linux/dmaengine.h> 20 21 #define MAX_MCI_SLOTS 2 22 23 enum dw_mci_state { 24 STATE_IDLE = 0, 25 STATE_SENDING_CMD, 26 STATE_SENDING_DATA, 27 STATE_DATA_BUSY, 28 STATE_SENDING_STOP, 29 STATE_DATA_ERROR, 30 STATE_SENDING_CMD11, 31 STATE_WAITING_CMD11_DONE, 32 }; 33 34 enum { 35 EVENT_CMD_COMPLETE = 0, 36 EVENT_XFER_COMPLETE, 37 EVENT_DATA_COMPLETE, 38 EVENT_DATA_ERROR, 39 EVENT_XFER_ERROR 40 }; 41 42 struct mmc_data; 43 44 enum { 45 TRANS_MODE_PIO = 0, 46 TRANS_MODE_IDMAC, 47 TRANS_MODE_EDMAC 48 }; 49 50 struct dw_mci_dma_slave { 51 struct dma_chan *ch; 52 enum dma_transfer_direction direction; 53 }; 54 55 /** 56 * struct dw_mci - MMC controller state shared between all slots 57 * @lock: Spinlock protecting the queue and associated data. 58 * @regs: Pointer to MMIO registers. 59 * @fifo_reg: Pointer to MMIO registers for data FIFO 60 * @sg: Scatterlist entry currently being processed by PIO code, if any. 61 * @sg_miter: PIO mapping scatterlist iterator. 62 * @cur_slot: The slot which is currently using the controller. 63 * @mrq: The request currently being processed on @cur_slot, 64 * or NULL if the controller is idle. 65 * @cmd: The command currently being sent to the card, or NULL. 66 * @data: The data currently being transferred, or NULL if no data 67 * transfer is in progress. 68 * @use_dma: Whether DMA channel is initialized or not. 69 * @using_dma: Whether DMA is in use for the current transfer. 70 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 71 * @sg_dma: Bus address of DMA buffer. 72 * @sg_cpu: Virtual address of DMA buffer. 73 * @dma_ops: Pointer to platform-specific DMA callbacks. 74 * @cmd_status: Snapshot of SR taken upon completion of the current 75 * command. Only valid when EVENT_CMD_COMPLETE is pending. 76 * @data_status: Snapshot of SR taken upon completion of the current 77 * data transfer. Only valid when EVENT_DATA_COMPLETE or 78 * EVENT_DATA_ERROR is pending. 79 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 80 * to be sent. 81 * @dir_status: Direction of current transfer. 82 * @tasklet: Tasklet running the request state machine. 83 * @card_tasklet: Tasklet handling card detect. 84 * @pending_events: Bitmask of events flagged by the interrupt handler 85 * to be processed by the tasklet. 86 * @completed_events: Bitmask of events which the state machine has 87 * processed. 88 * @state: Tasklet state. 89 * @queue: List of slots waiting for access to the controller. 90 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 91 * rate and timeout calculations. 92 * @current_speed: Configured rate of the controller. 93 * @num_slots: Number of slots available. 94 * @verid: Denote Version ID. 95 * @dev: Device associated with the MMC controller. 96 * @pdata: Platform data associated with the MMC controller. 97 * @drv_data: Driver specific data for identified variant of the controller 98 * @priv: Implementation defined private data. 99 * @biu_clk: Pointer to bus interface unit clock instance. 100 * @ciu_clk: Pointer to card interface unit clock instance. 101 * @slot: Slots sharing this MMC controller. 102 * @fifo_depth: depth of FIFO. 103 * @data_shift: log2 of FIFO item size. 104 * @part_buf_start: Start index in part_buf. 105 * @part_buf_count: Bytes of partial data in part_buf. 106 * @part_buf: Simple buffer for partial fifo reads/writes. 107 * @push_data: Pointer to FIFO push function. 108 * @pull_data: Pointer to FIFO pull function. 109 * @quirks: Set of quirks that apply to specific versions of the IP. 110 * @irq_flags: The flags to be passed to request_irq. 111 * @irq: The irq value to be passed to request_irq. 112 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 113 * @dto_timer: Timer for broken data transfer over scheme. 114 * 115 * Locking 116 * ======= 117 * 118 * @lock is a softirq-safe spinlock protecting @queue as well as 119 * @cur_slot, @mrq and @state. These must always be updated 120 * at the same time while holding @lock. 121 * 122 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 123 * to allow the interrupt handler to modify it directly. Held for only long 124 * enough to read-modify-write INTMASK and no other locks are grabbed when 125 * holding this one. 126 * 127 * The @mrq field of struct dw_mci_slot is also protected by @lock, 128 * and must always be written at the same time as the slot is added to 129 * @queue. 130 * 131 * @pending_events and @completed_events are accessed using atomic bit 132 * operations, so they don't need any locking. 133 * 134 * None of the fields touched by the interrupt handler need any 135 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 136 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 137 * interrupts must be disabled and @data_status updated with a 138 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 139 * CMDRDY interrupt must be disabled and @cmd_status updated with a 140 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 141 * bytes_xfered field of @data must be written. This is ensured by 142 * using barriers. 143 */ 144 struct dw_mci { 145 spinlock_t lock; 146 spinlock_t irq_lock; 147 void __iomem *regs; 148 void __iomem *fifo_reg; 149 150 struct scatterlist *sg; 151 struct sg_mapping_iter sg_miter; 152 153 struct dw_mci_slot *cur_slot; 154 struct mmc_request *mrq; 155 struct mmc_command *cmd; 156 struct mmc_data *data; 157 struct mmc_command stop_abort; 158 unsigned int prev_blksz; 159 unsigned char timing; 160 161 /* DMA interface members*/ 162 int use_dma; 163 int using_dma; 164 int dma_64bit_address; 165 166 dma_addr_t sg_dma; 167 void *sg_cpu; 168 const struct dw_mci_dma_ops *dma_ops; 169 /* For idmac */ 170 unsigned int ring_size; 171 172 /* For edmac */ 173 struct dw_mci_dma_slave *dms; 174 /* Registers's physical base address */ 175 void *phy_regs; 176 177 u32 cmd_status; 178 u32 data_status; 179 u32 stop_cmdr; 180 u32 dir_status; 181 struct tasklet_struct tasklet; 182 unsigned long pending_events; 183 unsigned long completed_events; 184 enum dw_mci_state state; 185 struct list_head queue; 186 187 u32 bus_hz; 188 u32 current_speed; 189 u32 num_slots; 190 u32 fifoth_val; 191 u16 verid; 192 struct device *dev; 193 struct dw_mci_board *pdata; 194 const struct dw_mci_drv_data *drv_data; 195 void *priv; 196 struct clk *biu_clk; 197 struct clk *ciu_clk; 198 struct dw_mci_slot *slot[MAX_MCI_SLOTS]; 199 200 /* FIFO push and pull */ 201 int fifo_depth; 202 int data_shift; 203 u8 part_buf_start; 204 u8 part_buf_count; 205 union { 206 u16 part_buf16; 207 u32 part_buf32; 208 u64 part_buf; 209 }; 210 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 211 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 212 213 /* Workaround flags */ 214 u32 quirks; 215 216 bool vqmmc_enabled; 217 unsigned long irq_flags; /* IRQ flags */ 218 int irq; 219 220 int sdio_id0; 221 222 struct timer_list cmd11_timer; 223 struct timer_list dto_timer; 224 }; 225 226 /* DMA ops for Internal/External DMAC interface */ 227 struct dw_mci_dma_ops { 228 /* DMA Ops */ 229 int (*init)(struct dw_mci *host); 230 int (*start)(struct dw_mci *host, unsigned int sg_len); 231 void (*complete)(void *host); 232 void (*stop)(struct dw_mci *host); 233 void (*cleanup)(struct dw_mci *host); 234 void (*exit)(struct dw_mci *host); 235 }; 236 237 /* IP Quirks/flags. */ 238 /* DTO fix for command transmission with IDMAC configured */ 239 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0) 240 /* delay needed between retries on some 2.11a implementations */ 241 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1) 242 /* High Speed Capable - Supports HS cards (up to 50MHz) */ 243 #define DW_MCI_QUIRK_HIGHSPEED BIT(2) 244 /* Unreliable card detection */ 245 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3) 246 /* Timer for broken data transfer over scheme */ 247 #define DW_MCI_QUIRK_BROKEN_DTO BIT(4) 248 249 struct dma_pdata; 250 251 struct block_settings { 252 unsigned short max_segs; /* see blk_queue_max_segments */ 253 unsigned int max_blk_size; /* maximum size of one mmc block */ 254 unsigned int max_blk_count; /* maximum number of blocks in one req*/ 255 unsigned int max_req_size; /* maximum number of bytes in one req*/ 256 unsigned int max_seg_size; /* see blk_queue_max_segment_size */ 257 }; 258 259 /* Board platform data */ 260 struct dw_mci_board { 261 u32 num_slots; 262 263 u32 quirks; /* Workaround / Quirk flags */ 264 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 265 266 u32 caps; /* Capabilities */ 267 u32 caps2; /* More capabilities */ 268 u32 pm_caps; /* PM capabilities */ 269 /* 270 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 271 * but note that this may not be reliable after a bootloader has used 272 * it. 273 */ 274 unsigned int fifo_depth; 275 276 /* delay in mS before detecting cards after interrupt */ 277 u32 detect_delay_ms; 278 279 struct dw_mci_dma_ops *dma_ops; 280 struct dma_pdata *data; 281 }; 282 283 #endif /* LINUX_MMC_DW_MMC_H */ 284