1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef LINUX_MMC_DW_MMC_H 15 #define LINUX_MMC_DW_MMC_H 16 17 #include <linux/scatterlist.h> 18 #include <linux/mmc/core.h> 19 20 #define MAX_MCI_SLOTS 2 21 22 enum dw_mci_state { 23 STATE_IDLE = 0, 24 STATE_SENDING_CMD, 25 STATE_SENDING_DATA, 26 STATE_DATA_BUSY, 27 STATE_SENDING_STOP, 28 STATE_DATA_ERROR, 29 STATE_SENDING_CMD11, 30 STATE_WAITING_CMD11_DONE, 31 }; 32 33 enum { 34 EVENT_CMD_COMPLETE = 0, 35 EVENT_XFER_COMPLETE, 36 EVENT_DATA_COMPLETE, 37 EVENT_DATA_ERROR, 38 EVENT_XFER_ERROR 39 }; 40 41 struct mmc_data; 42 43 /** 44 * struct dw_mci - MMC controller state shared between all slots 45 * @lock: Spinlock protecting the queue and associated data. 46 * @regs: Pointer to MMIO registers. 47 * @fifo_reg: Pointer to MMIO registers for data FIFO 48 * @sg: Scatterlist entry currently being processed by PIO code, if any. 49 * @sg_miter: PIO mapping scatterlist iterator. 50 * @cur_slot: The slot which is currently using the controller. 51 * @mrq: The request currently being processed on @cur_slot, 52 * or NULL if the controller is idle. 53 * @cmd: The command currently being sent to the card, or NULL. 54 * @data: The data currently being transferred, or NULL if no data 55 * transfer is in progress. 56 * @use_dma: Whether DMA channel is initialized or not. 57 * @using_dma: Whether DMA is in use for the current transfer. 58 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 59 * @sg_dma: Bus address of DMA buffer. 60 * @sg_cpu: Virtual address of DMA buffer. 61 * @dma_ops: Pointer to platform-specific DMA callbacks. 62 * @cmd_status: Snapshot of SR taken upon completion of the current 63 * command. Only valid when EVENT_CMD_COMPLETE is pending. 64 * @data_status: Snapshot of SR taken upon completion of the current 65 * data transfer. Only valid when EVENT_DATA_COMPLETE or 66 * EVENT_DATA_ERROR is pending. 67 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 68 * to be sent. 69 * @dir_status: Direction of current transfer. 70 * @tasklet: Tasklet running the request state machine. 71 * @card_tasklet: Tasklet handling card detect. 72 * @pending_events: Bitmask of events flagged by the interrupt handler 73 * to be processed by the tasklet. 74 * @completed_events: Bitmask of events which the state machine has 75 * processed. 76 * @state: Tasklet state. 77 * @queue: List of slots waiting for access to the controller. 78 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 79 * rate and timeout calculations. 80 * @current_speed: Configured rate of the controller. 81 * @num_slots: Number of slots available. 82 * @verid: Denote Version ID. 83 * @dev: Device associated with the MMC controller. 84 * @pdata: Platform data associated with the MMC controller. 85 * @drv_data: Driver specific data for identified variant of the controller 86 * @priv: Implementation defined private data. 87 * @biu_clk: Pointer to bus interface unit clock instance. 88 * @ciu_clk: Pointer to card interface unit clock instance. 89 * @slot: Slots sharing this MMC controller. 90 * @fifo_depth: depth of FIFO. 91 * @data_shift: log2 of FIFO item size. 92 * @part_buf_start: Start index in part_buf. 93 * @part_buf_count: Bytes of partial data in part_buf. 94 * @part_buf: Simple buffer for partial fifo reads/writes. 95 * @push_data: Pointer to FIFO push function. 96 * @pull_data: Pointer to FIFO pull function. 97 * @quirks: Set of quirks that apply to specific versions of the IP. 98 * @irq_flags: The flags to be passed to request_irq. 99 * @irq: The irq value to be passed to request_irq. 100 * @sdio_id0: Number of slot0 in the SDIO interrupt registers. 101 * 102 * Locking 103 * ======= 104 * 105 * @lock is a softirq-safe spinlock protecting @queue as well as 106 * @cur_slot, @mrq and @state. These must always be updated 107 * at the same time while holding @lock. 108 * 109 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 110 * to allow the interrupt handler to modify it directly. Held for only long 111 * enough to read-modify-write INTMASK and no other locks are grabbed when 112 * holding this one. 113 * 114 * The @mrq field of struct dw_mci_slot is also protected by @lock, 115 * and must always be written at the same time as the slot is added to 116 * @queue. 117 * 118 * @pending_events and @completed_events are accessed using atomic bit 119 * operations, so they don't need any locking. 120 * 121 * None of the fields touched by the interrupt handler need any 122 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 123 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 124 * interrupts must be disabled and @data_status updated with a 125 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 126 * CMDRDY interrupt must be disabled and @cmd_status updated with a 127 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 128 * bytes_xfered field of @data must be written. This is ensured by 129 * using barriers. 130 */ 131 struct dw_mci { 132 spinlock_t lock; 133 spinlock_t irq_lock; 134 void __iomem *regs; 135 void __iomem *fifo_reg; 136 137 struct scatterlist *sg; 138 struct sg_mapping_iter sg_miter; 139 140 struct dw_mci_slot *cur_slot; 141 struct mmc_request *mrq; 142 struct mmc_command *cmd; 143 struct mmc_data *data; 144 struct mmc_command stop_abort; 145 unsigned int prev_blksz; 146 unsigned char timing; 147 148 /* DMA interface members*/ 149 int use_dma; 150 int using_dma; 151 int dma_64bit_address; 152 153 dma_addr_t sg_dma; 154 void *sg_cpu; 155 const struct dw_mci_dma_ops *dma_ops; 156 #ifdef CONFIG_MMC_DW_IDMAC 157 unsigned int ring_size; 158 #else 159 struct dw_mci_dma_data *dma_data; 160 #endif 161 u32 cmd_status; 162 u32 data_status; 163 u32 stop_cmdr; 164 u32 dir_status; 165 struct tasklet_struct tasklet; 166 unsigned long pending_events; 167 unsigned long completed_events; 168 enum dw_mci_state state; 169 struct list_head queue; 170 171 u32 bus_hz; 172 u32 current_speed; 173 u32 num_slots; 174 u32 fifoth_val; 175 u16 verid; 176 struct device *dev; 177 struct dw_mci_board *pdata; 178 const struct dw_mci_drv_data *drv_data; 179 void *priv; 180 struct clk *biu_clk; 181 struct clk *ciu_clk; 182 struct dw_mci_slot *slot[MAX_MCI_SLOTS]; 183 184 /* FIFO push and pull */ 185 int fifo_depth; 186 int data_shift; 187 u8 part_buf_start; 188 u8 part_buf_count; 189 union { 190 u16 part_buf16; 191 u32 part_buf32; 192 u64 part_buf; 193 }; 194 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 195 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 196 197 /* Workaround flags */ 198 u32 quirks; 199 200 bool vqmmc_enabled; 201 unsigned long irq_flags; /* IRQ flags */ 202 int irq; 203 204 int sdio_id0; 205 206 struct timer_list cmd11_timer; 207 }; 208 209 /* DMA ops for Internal/External DMAC interface */ 210 struct dw_mci_dma_ops { 211 /* DMA Ops */ 212 int (*init)(struct dw_mci *host); 213 void (*start)(struct dw_mci *host, unsigned int sg_len); 214 void (*complete)(struct dw_mci *host); 215 void (*stop)(struct dw_mci *host); 216 void (*cleanup)(struct dw_mci *host); 217 void (*exit)(struct dw_mci *host); 218 }; 219 220 /* IP Quirks/flags. */ 221 /* DTO fix for command transmission with IDMAC configured */ 222 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0) 223 /* delay needed between retries on some 2.11a implementations */ 224 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1) 225 /* High Speed Capable - Supports HS cards (up to 50MHz) */ 226 #define DW_MCI_QUIRK_HIGHSPEED BIT(2) 227 /* Unreliable card detection */ 228 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3) 229 /* No write protect */ 230 #define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4) 231 232 /* Slot level quirks */ 233 /* This slot has no write protect */ 234 #define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0) 235 236 struct dma_pdata; 237 238 struct block_settings { 239 unsigned short max_segs; /* see blk_queue_max_segments */ 240 unsigned int max_blk_size; /* maximum size of one mmc block */ 241 unsigned int max_blk_count; /* maximum number of blocks in one req*/ 242 unsigned int max_req_size; /* maximum number of bytes in one req*/ 243 unsigned int max_seg_size; /* see blk_queue_max_segment_size */ 244 }; 245 246 /* Board platform data */ 247 struct dw_mci_board { 248 u32 num_slots; 249 250 u32 quirks; /* Workaround / Quirk flags */ 251 unsigned int bus_hz; /* Clock speed at the cclk_in pad */ 252 253 u32 caps; /* Capabilities */ 254 u32 caps2; /* More capabilities */ 255 u32 pm_caps; /* PM capabilities */ 256 /* 257 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 258 * but note that this may not be reliable after a bootloader has used 259 * it. 260 */ 261 unsigned int fifo_depth; 262 263 /* delay in mS before detecting cards after interrupt */ 264 u32 detect_delay_ms; 265 266 struct dw_mci_dma_ops *dma_ops; 267 struct dma_pdata *data; 268 struct block_settings *blk_settings; 269 }; 270 271 #endif /* LINUX_MMC_DW_MMC_H */ 272