1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_HDA_CGCTL 0x48
94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
95 #define INTEL_SCH_HDA_DEVC 0x78
96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98 /* Define IN stream 0 FIFO size offset in VIA controller */
99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100 /* Define VIA HD Audio Device ID*/
101 #define VIA_HDAC_DEVICE_ID 0x3288
102
103 /* max number of SDs */
104 /* ICH, ATI and VIA have 4 playback and 4 capture */
105 #define ICH6_NUM_CAPTURE 4
106 #define ICH6_NUM_PLAYBACK 4
107
108 /* ULI has 6 playback and 5 capture */
109 #define ULI_NUM_CAPTURE 5
110 #define ULI_NUM_PLAYBACK 6
111
112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
113 #define ATIHDMI_NUM_CAPTURE 0
114 #define ATIHDMI_NUM_PLAYBACK 8
115
116 /* TERA has 4 playback and 3 capture */
117 #define TERA_NUM_CAPTURE 3
118 #define TERA_NUM_PLAYBACK 4
119
120
121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
124 static char *model[SNDRV_CARDS];
125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_only[SNDRV_CARDS];
129 static int jackpoll_ms[SNDRV_CARDS];
130 static bool single_cmd;
131 static int enable_msi = -1;
132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
133 static char *patch[SNDRV_CARDS];
134 #endif
135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138 #endif
139
140 module_param_array(index, int, NULL, 0444);
141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
142 module_param_array(id, charp, NULL, 0444);
143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
144 module_param_array(enable, bool, NULL, 0444);
145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146 module_param_array(model, charp, NULL, 0444);
147 MODULE_PARM_DESC(model, "Use the given board model.");
148 module_param_array(position_fix, int, NULL, 0444);
149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
151 module_param_array(bdl_pos_adj, int, NULL, 0644);
152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
153 module_param_array(probe_mask, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
155 module_param_array(probe_only, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
157 module_param_array(jackpoll_ms, int, NULL, 0444);
158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
159 module_param(single_cmd, bool, 0444);
160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
162 module_param(enable_msi, bint, 0444);
163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
165 module_param_array(patch, charp, NULL, 0444);
166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167 #endif
168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
169 module_param_array(beep_mode, bool, NULL, 0444);
170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
171 "(0=off, 1=on) (default=1).");
172 #endif
173
174 #ifdef CONFIG_PM
175 static int param_set_xint(const char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops param_ops_xint = {
177 .set = param_set_xint,
178 .get = param_get_int,
179 };
180 #define param_check_xint param_check_int
181
182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
183 module_param(power_save, xint, 0644);
184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
186
187 /* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
191 static bool power_save_controller = 1;
192 module_param(power_save_controller, bool, 0644);
193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
194 #else
195 #define power_save 0
196 #endif /* CONFIG_PM */
197
198 static int align_buffer_size = -1;
199 module_param(align_buffer_size, bint, 0644);
200 MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
203 #ifdef CONFIG_X86
204 static int hda_snoop = -1;
205 module_param_named(snoop, hda_snoop, bint, 0444);
206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
207 #else
208 #define hda_snoop true
209 #endif
210
211
212 MODULE_LICENSE("GPL");
213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
215 "{Intel, ICH7},"
216 "{Intel, ESB2},"
217 "{Intel, ICH8},"
218 "{Intel, ICH9},"
219 "{Intel, ICH10},"
220 "{Intel, PCH},"
221 "{Intel, CPT},"
222 "{Intel, PPT},"
223 "{Intel, LPT},"
224 "{Intel, LPT_LP},"
225 "{Intel, WPT_LP},"
226 "{Intel, SPT},"
227 "{Intel, SPT_LP},"
228 "{Intel, HPT},"
229 "{Intel, PBG},"
230 "{Intel, SCH},"
231 "{ATI, SB450},"
232 "{ATI, SB600},"
233 "{ATI, RS600},"
234 "{ATI, RS690},"
235 "{ATI, RS780},"
236 "{ATI, R600},"
237 "{ATI, RV630},"
238 "{ATI, RV610},"
239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
243 "{VIA, VT8251},"
244 "{VIA, VT8237A},"
245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
247 MODULE_DESCRIPTION("Intel HDA driver");
248
249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
251 #define SUPPORT_VGA_SWITCHEROO
252 #endif
253 #endif
254
255
256 /*
257 */
258
259 /* driver types */
260 enum {
261 AZX_DRIVER_ICH,
262 AZX_DRIVER_PCH,
263 AZX_DRIVER_SCH,
264 AZX_DRIVER_HDMI,
265 AZX_DRIVER_ATI,
266 AZX_DRIVER_ATIHDMI,
267 AZX_DRIVER_ATIHDMI_NS,
268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
271 AZX_DRIVER_NVIDIA,
272 AZX_DRIVER_TERA,
273 AZX_DRIVER_CTX,
274 AZX_DRIVER_CTHDA,
275 AZX_DRIVER_CMEDIA,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
287
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_NOPM \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
292
293 #define AZX_DCAPS_INTEL_PCH \
294 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
295
296 #define AZX_DCAPS_INTEL_HASWELL \
297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
299 AZX_DCAPS_SNOOP_TYPE(SCH))
300
301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
302 #define AZX_DCAPS_INTEL_BROADWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
306
307 #define AZX_DCAPS_INTEL_BAYTRAIL \
308 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
309
310 #define AZX_DCAPS_INTEL_BRASWELL \
311 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
312
313 #define AZX_DCAPS_INTEL_SKYLAKE \
314 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
315 AZX_DCAPS_I915_POWERWELL)
316
317 #define AZX_DCAPS_INTEL_BROXTON \
318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
320
321 /* quirks for ATI SB / AMD Hudson */
322 #define AZX_DCAPS_PRESET_ATI_SB \
323 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
324 AZX_DCAPS_SNOOP_TYPE(ATI))
325
326 /* quirks for ATI/AMD HDMI */
327 #define AZX_DCAPS_PRESET_ATI_HDMI \
328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
329 AZX_DCAPS_NO_MSI64)
330
331 /* quirks for ATI HDMI with snoop off */
332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
333 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
334
335 /* quirks for Nvidia */
336 #define AZX_DCAPS_PRESET_NVIDIA \
337 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
338 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
339 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
340
341 #define AZX_DCAPS_PRESET_CTHDA \
342 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
343 AZX_DCAPS_NO_64BIT |\
344 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
345
346 /*
347 * vga_switcheroo support
348 */
349 #ifdef SUPPORT_VGA_SWITCHEROO
350 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
351 #else
352 #define use_vga_switcheroo(chip) 0
353 #endif
354
355 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
356 ((pci)->device == 0x0c0c) || \
357 ((pci)->device == 0x0d0c) || \
358 ((pci)->device == 0x160c))
359
360 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
361 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
362 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
363 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
364 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
365 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
366 IS_KBL(pci) || IS_KBL_LP(pci)
367
368 static char *driver_short_names[] = {
369 [AZX_DRIVER_ICH] = "HDA Intel",
370 [AZX_DRIVER_PCH] = "HDA Intel PCH",
371 [AZX_DRIVER_SCH] = "HDA Intel MID",
372 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
373 [AZX_DRIVER_ATI] = "HDA ATI SB",
374 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
375 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
376 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
377 [AZX_DRIVER_SIS] = "HDA SIS966",
378 [AZX_DRIVER_ULI] = "HDA ULI M5461",
379 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
380 [AZX_DRIVER_TERA] = "HDA Teradici",
381 [AZX_DRIVER_CTX] = "HDA Creative",
382 [AZX_DRIVER_CTHDA] = "HDA Creative",
383 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
384 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
385 };
386
387 #ifdef CONFIG_X86
__mark_pages_wc(struct azx * chip,struct snd_dma_buffer * dmab,bool on)388 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
389 {
390 int pages;
391
392 if (azx_snoop(chip))
393 return;
394 if (!dmab || !dmab->area || !dmab->bytes)
395 return;
396
397 #ifdef CONFIG_SND_DMA_SGBUF
398 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
399 struct snd_sg_buf *sgbuf = dmab->private_data;
400 if (chip->driver_type == AZX_DRIVER_CMEDIA)
401 return; /* deal with only CORB/RIRB buffers */
402 if (on)
403 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
404 else
405 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
406 return;
407 }
408 #endif
409
410 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
411 if (on)
412 set_memory_wc((unsigned long)dmab->area, pages);
413 else
414 set_memory_wb((unsigned long)dmab->area, pages);
415 }
416
mark_pages_wc(struct azx * chip,struct snd_dma_buffer * buf,bool on)417 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419 {
420 __mark_pages_wc(chip, buf, on);
421 }
mark_runtime_wc(struct azx * chip,struct azx_dev * azx_dev,struct snd_pcm_substream * substream,bool on)422 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
423 struct snd_pcm_substream *substream, bool on)
424 {
425 if (azx_dev->wc_marked != on) {
426 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
427 azx_dev->wc_marked = on;
428 }
429 }
430 #else
431 /* NOP for other archs */
mark_pages_wc(struct azx * chip,struct snd_dma_buffer * buf,bool on)432 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
433 bool on)
434 {
435 }
mark_runtime_wc(struct azx * chip,struct azx_dev * azx_dev,struct snd_pcm_substream * substream,bool on)436 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
437 struct snd_pcm_substream *substream, bool on)
438 {
439 }
440 #endif
441
442 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
443
444 /*
445 * initialize the PCI registers
446 */
447 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)448 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
449 unsigned char mask, unsigned char val)
450 {
451 unsigned char data;
452
453 pci_read_config_byte(pci, reg, &data);
454 data &= ~mask;
455 data |= (val & mask);
456 pci_write_config_byte(pci, reg, data);
457 }
458
azx_init_pci(struct azx * chip)459 static void azx_init_pci(struct azx *chip)
460 {
461 int snoop_type = azx_get_snoop_type(chip);
462
463 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
464 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
465 * Ensuring these bits are 0 clears playback static on some HD Audio
466 * codecs.
467 * The PCI register TCSEL is defined in the Intel manuals.
468 */
469 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
470 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
471 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
472 }
473
474 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
475 * we need to enable snoop.
476 */
477 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
478 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
479 azx_snoop(chip));
480 update_pci_byte(chip->pci,
481 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
482 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
483 }
484
485 /* For NVIDIA HDA, enable snoop */
486 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
487 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
488 azx_snoop(chip));
489 update_pci_byte(chip->pci,
490 NVIDIA_HDA_TRANSREG_ADDR,
491 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_ISTRM_COH,
494 0x01, NVIDIA_HDA_ENABLE_COHBIT);
495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_OSTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 }
499
500 /* Enable SCH/PCH snoop if needed */
501 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
502 unsigned short snoop;
503 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
504 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
505 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
506 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
507 if (!azx_snoop(chip))
508 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
509 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
510 pci_read_config_word(chip->pci,
511 INTEL_SCH_HDA_DEVC, &snoop);
512 }
513 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
514 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
515 "Disabled" : "Enabled");
516 }
517 }
518
519 /*
520 * In BXT-P A0, HD-Audio DMA requests is later than expected,
521 * and makes an audio stream sensitive to system latencies when
522 * 24/32 bits are playing.
523 * Adjusting threshold of DMA fifo to force the DMA request
524 * sooner to improve latency tolerance at the expense of power.
525 */
bxt_reduce_dma_latency(struct azx * chip)526 static void bxt_reduce_dma_latency(struct azx *chip)
527 {
528 u32 val;
529
530 val = azx_readl(chip, SKL_EM4L);
531 val &= (0x3 << 20);
532 azx_writel(chip, SKL_EM4L, val);
533 }
534
hda_intel_init_chip(struct azx * chip,bool full_reset)535 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
536 {
537 struct hdac_bus *bus = azx_bus(chip);
538 struct pci_dev *pci = chip->pci;
539 u32 val;
540
541 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
542 snd_hdac_set_codec_wakeup(bus, true);
543 if (IS_SKL_PLUS(pci)) {
544 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
545 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
546 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
547 }
548 azx_init_chip(chip, full_reset);
549 if (IS_SKL_PLUS(pci)) {
550 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
551 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
552 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
553 }
554 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
555 snd_hdac_set_codec_wakeup(bus, false);
556
557 /* reduce dma latency to avoid noise */
558 if (IS_BXT(pci))
559 bxt_reduce_dma_latency(chip);
560 }
561
562 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)563 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
564 unsigned int pos)
565 {
566 struct snd_pcm_substream *substream = azx_dev->core.substream;
567 int stream = substream->stream;
568 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
569 int delay;
570
571 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
572 delay = pos - lpib_pos;
573 else
574 delay = lpib_pos - pos;
575 if (delay < 0) {
576 if (delay >= azx_dev->core.delay_negative_threshold)
577 delay = 0;
578 else
579 delay += azx_dev->core.bufsize;
580 }
581
582 if (delay >= azx_dev->core.period_bytes) {
583 dev_info(chip->card->dev,
584 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
585 delay, azx_dev->core.period_bytes);
586 delay = 0;
587 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
588 chip->get_delay[stream] = NULL;
589 }
590
591 return bytes_to_frames(substream->runtime, delay);
592 }
593
594 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
595
596 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)597 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
598 {
599 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
600 int ok;
601
602 ok = azx_position_ok(chip, azx_dev);
603 if (ok == 1) {
604 azx_dev->irq_pending = 0;
605 return ok;
606 } else if (ok == 0) {
607 /* bogus IRQ, process it later */
608 azx_dev->irq_pending = 1;
609 schedule_work(&hda->irq_pending_work);
610 }
611 return 0;
612 }
613
614 /* Enable/disable i915 display power for the link */
azx_intel_link_power(struct azx * chip,bool enable)615 static int azx_intel_link_power(struct azx *chip, bool enable)
616 {
617 struct hdac_bus *bus = azx_bus(chip);
618
619 return snd_hdac_display_power(bus, enable);
620 }
621
622 /*
623 * Check whether the current DMA position is acceptable for updating
624 * periods. Returns non-zero if it's OK.
625 *
626 * Many HD-audio controllers appear pretty inaccurate about
627 * the update-IRQ timing. The IRQ is issued before actually the
628 * data is processed. So, we need to process it afterwords in a
629 * workqueue.
630 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)631 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
632 {
633 struct snd_pcm_substream *substream = azx_dev->core.substream;
634 int stream = substream->stream;
635 u32 wallclk;
636 unsigned int pos;
637
638 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
639 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
640 return -1; /* bogus (too early) interrupt */
641
642 if (chip->get_position[stream])
643 pos = chip->get_position[stream](chip, azx_dev);
644 else { /* use the position buffer as default */
645 pos = azx_get_pos_posbuf(chip, azx_dev);
646 if (!pos || pos == (u32)-1) {
647 dev_info(chip->card->dev,
648 "Invalid position buffer, using LPIB read method instead.\n");
649 chip->get_position[stream] = azx_get_pos_lpib;
650 if (chip->get_position[0] == azx_get_pos_lpib &&
651 chip->get_position[1] == azx_get_pos_lpib)
652 azx_bus(chip)->use_posbuf = false;
653 pos = azx_get_pos_lpib(chip, azx_dev);
654 chip->get_delay[stream] = NULL;
655 } else {
656 chip->get_position[stream] = azx_get_pos_posbuf;
657 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
658 chip->get_delay[stream] = azx_get_delay_from_lpib;
659 }
660 }
661
662 if (pos >= azx_dev->core.bufsize)
663 pos = 0;
664
665 if (WARN_ONCE(!azx_dev->core.period_bytes,
666 "hda-intel: zero azx_dev->period_bytes"))
667 return -1; /* this shouldn't happen! */
668 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
669 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
670 /* NG - it's below the first next period boundary */
671 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
672 azx_dev->core.start_wallclk += wallclk;
673 return 1; /* OK, it's fine */
674 }
675
676 /*
677 * The work for pending PCM period updates.
678 */
azx_irq_pending_work(struct work_struct * work)679 static void azx_irq_pending_work(struct work_struct *work)
680 {
681 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
682 struct azx *chip = &hda->chip;
683 struct hdac_bus *bus = azx_bus(chip);
684 struct hdac_stream *s;
685 int pending, ok;
686
687 if (!hda->irq_pending_warned) {
688 dev_info(chip->card->dev,
689 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
690 chip->card->number);
691 hda->irq_pending_warned = 1;
692 }
693
694 for (;;) {
695 pending = 0;
696 spin_lock_irq(&bus->reg_lock);
697 list_for_each_entry(s, &bus->stream_list, list) {
698 struct azx_dev *azx_dev = stream_to_azx_dev(s);
699 if (!azx_dev->irq_pending ||
700 !s->substream ||
701 !s->running)
702 continue;
703 ok = azx_position_ok(chip, azx_dev);
704 if (ok > 0) {
705 azx_dev->irq_pending = 0;
706 spin_unlock(&bus->reg_lock);
707 snd_pcm_period_elapsed(s->substream);
708 spin_lock(&bus->reg_lock);
709 } else if (ok < 0) {
710 pending = 0; /* too early */
711 } else
712 pending++;
713 }
714 spin_unlock_irq(&bus->reg_lock);
715 if (!pending)
716 return;
717 msleep(1);
718 }
719 }
720
721 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)722 static void azx_clear_irq_pending(struct azx *chip)
723 {
724 struct hdac_bus *bus = azx_bus(chip);
725 struct hdac_stream *s;
726
727 spin_lock_irq(&bus->reg_lock);
728 list_for_each_entry(s, &bus->stream_list, list) {
729 struct azx_dev *azx_dev = stream_to_azx_dev(s);
730 azx_dev->irq_pending = 0;
731 }
732 spin_unlock_irq(&bus->reg_lock);
733 }
734
azx_acquire_irq(struct azx * chip,int do_disconnect)735 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
736 {
737 struct hdac_bus *bus = azx_bus(chip);
738
739 if (request_irq(chip->pci->irq, azx_interrupt,
740 chip->msi ? 0 : IRQF_SHARED,
741 KBUILD_MODNAME, chip)) {
742 dev_err(chip->card->dev,
743 "unable to grab IRQ %d, disabling device\n",
744 chip->pci->irq);
745 if (do_disconnect)
746 snd_card_disconnect(chip->card);
747 return -1;
748 }
749 bus->irq = chip->pci->irq;
750 pci_intx(chip->pci, !chip->msi);
751 return 0;
752 }
753
754 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)755 static unsigned int azx_via_get_position(struct azx *chip,
756 struct azx_dev *azx_dev)
757 {
758 unsigned int link_pos, mini_pos, bound_pos;
759 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
760 unsigned int fifo_size;
761
762 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
763 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
764 /* Playback, no problem using link position */
765 return link_pos;
766 }
767
768 /* Capture */
769 /* For new chipset,
770 * use mod to get the DMA position just like old chipset
771 */
772 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
773 mod_dma_pos %= azx_dev->core.period_bytes;
774
775 /* azx_dev->fifo_size can't get FIFO size of in stream.
776 * Get from base address + offset.
777 */
778 fifo_size = readw(azx_bus(chip)->remap_addr +
779 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
780
781 if (azx_dev->insufficient) {
782 /* Link position never gather than FIFO size */
783 if (link_pos <= fifo_size)
784 return 0;
785
786 azx_dev->insufficient = 0;
787 }
788
789 if (link_pos <= fifo_size)
790 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
791 else
792 mini_pos = link_pos - fifo_size;
793
794 /* Find nearest previous boudary */
795 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
796 mod_link_pos = link_pos % azx_dev->core.period_bytes;
797 if (mod_link_pos >= fifo_size)
798 bound_pos = link_pos - mod_link_pos;
799 else if (mod_dma_pos >= mod_mini_pos)
800 bound_pos = mini_pos - mod_mini_pos;
801 else {
802 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
803 if (bound_pos >= azx_dev->core.bufsize)
804 bound_pos = 0;
805 }
806
807 /* Calculate real DMA position we want */
808 return bound_pos + mod_dma_pos;
809 }
810
811 #ifdef CONFIG_PM
812 static DEFINE_MUTEX(card_list_lock);
813 static LIST_HEAD(card_list);
814
azx_add_card_list(struct azx * chip)815 static void azx_add_card_list(struct azx *chip)
816 {
817 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
818 mutex_lock(&card_list_lock);
819 list_add(&hda->list, &card_list);
820 mutex_unlock(&card_list_lock);
821 }
822
azx_del_card_list(struct azx * chip)823 static void azx_del_card_list(struct azx *chip)
824 {
825 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
826 mutex_lock(&card_list_lock);
827 list_del_init(&hda->list);
828 mutex_unlock(&card_list_lock);
829 }
830
831 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)832 static int param_set_xint(const char *val, const struct kernel_param *kp)
833 {
834 struct hda_intel *hda;
835 struct azx *chip;
836 int prev = power_save;
837 int ret = param_set_int(val, kp);
838
839 if (ret || prev == power_save)
840 return ret;
841
842 mutex_lock(&card_list_lock);
843 list_for_each_entry(hda, &card_list, list) {
844 chip = &hda->chip;
845 if (!hda->probe_continued || chip->disabled)
846 continue;
847 snd_hda_set_power_save(&chip->bus, power_save * 1000);
848 }
849 mutex_unlock(&card_list_lock);
850 return 0;
851 }
852 #else
853 #define azx_add_card_list(chip) /* NOP */
854 #define azx_del_card_list(chip) /* NOP */
855 #endif /* CONFIG_PM */
856
857 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
858 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
859 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
860 * BCLK = CDCLK * M / N
861 * The values will be lost when the display power well is disabled and need to
862 * be restored to avoid abnormal playback speed.
863 */
haswell_set_bclk(struct hda_intel * hda)864 static void haswell_set_bclk(struct hda_intel *hda)
865 {
866 struct azx *chip = &hda->chip;
867 int cdclk_freq;
868 unsigned int bclk_m, bclk_n;
869
870 if (!hda->need_i915_power)
871 return;
872
873 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
874 switch (cdclk_freq) {
875 case 337500:
876 bclk_m = 16;
877 bclk_n = 225;
878 break;
879
880 case 450000:
881 default: /* default CDCLK 450MHz */
882 bclk_m = 4;
883 bclk_n = 75;
884 break;
885
886 case 540000:
887 bclk_m = 4;
888 bclk_n = 90;
889 break;
890
891 case 675000:
892 bclk_m = 8;
893 bclk_n = 225;
894 break;
895 }
896
897 azx_writew(chip, HSW_EM4, bclk_m);
898 azx_writew(chip, HSW_EM5, bclk_n);
899 }
900
901 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
902 /*
903 * power management
904 */
azx_suspend(struct device * dev)905 static int azx_suspend(struct device *dev)
906 {
907 struct snd_card *card = dev_get_drvdata(dev);
908 struct azx *chip;
909 struct hda_intel *hda;
910 struct hdac_bus *bus;
911
912 if (!card)
913 return 0;
914
915 chip = card->private_data;
916 hda = container_of(chip, struct hda_intel, chip);
917 if (chip->disabled || hda->init_failed || !chip->running)
918 return 0;
919
920 bus = azx_bus(chip);
921 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
922 azx_clear_irq_pending(chip);
923 azx_stop_chip(chip);
924 azx_enter_link_reset(chip);
925 if (bus->irq >= 0) {
926 free_irq(bus->irq, chip);
927 bus->irq = -1;
928 }
929
930 if (chip->msi)
931 pci_disable_msi(chip->pci);
932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
933 && hda->need_i915_power)
934 snd_hdac_display_power(bus, false);
935
936 trace_azx_suspend(chip);
937 return 0;
938 }
939
azx_resume(struct device * dev)940 static int azx_resume(struct device *dev)
941 {
942 struct pci_dev *pci = to_pci_dev(dev);
943 struct snd_card *card = dev_get_drvdata(dev);
944 struct azx *chip;
945 struct hda_intel *hda;
946
947 if (!card)
948 return 0;
949
950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
952 if (chip->disabled || hda->init_failed || !chip->running)
953 return 0;
954
955 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
956 && hda->need_i915_power) {
957 snd_hdac_display_power(azx_bus(chip), true);
958 haswell_set_bclk(hda);
959 }
960 if (chip->msi)
961 if (pci_enable_msi(pci) < 0)
962 chip->msi = 0;
963 if (azx_acquire_irq(chip, 1) < 0)
964 return -EIO;
965 azx_init_pci(chip);
966
967 hda_intel_init_chip(chip, true);
968
969 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
970
971 trace_azx_resume(chip);
972 return 0;
973 }
974 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
975
976 #ifdef CONFIG_PM_SLEEP
977 /* put codec down to D3 at hibernation for Intel SKL+;
978 * otherwise BIOS may still access the codec and screw up the driver
979 */
azx_freeze_noirq(struct device * dev)980 static int azx_freeze_noirq(struct device *dev)
981 {
982 struct pci_dev *pci = to_pci_dev(dev);
983
984 if (IS_SKL_PLUS(pci))
985 pci_set_power_state(pci, PCI_D3hot);
986
987 return 0;
988 }
989
azx_thaw_noirq(struct device * dev)990 static int azx_thaw_noirq(struct device *dev)
991 {
992 struct pci_dev *pci = to_pci_dev(dev);
993
994 if (IS_SKL_PLUS(pci))
995 pci_set_power_state(pci, PCI_D0);
996
997 return 0;
998 }
999 #endif /* CONFIG_PM_SLEEP */
1000
1001 #ifdef CONFIG_PM
azx_runtime_suspend(struct device * dev)1002 static int azx_runtime_suspend(struct device *dev)
1003 {
1004 struct snd_card *card = dev_get_drvdata(dev);
1005 struct azx *chip;
1006 struct hda_intel *hda;
1007
1008 if (!card)
1009 return 0;
1010
1011 chip = card->private_data;
1012 hda = container_of(chip, struct hda_intel, chip);
1013 if (chip->disabled || hda->init_failed)
1014 return 0;
1015
1016 if (!azx_has_pm_runtime(chip))
1017 return 0;
1018
1019 /* enable controller wake up event */
1020 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1021 STATESTS_INT_MASK);
1022
1023 azx_stop_chip(chip);
1024 azx_enter_link_reset(chip);
1025 azx_clear_irq_pending(chip);
1026 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1027 && hda->need_i915_power)
1028 snd_hdac_display_power(azx_bus(chip), false);
1029
1030 trace_azx_runtime_suspend(chip);
1031 return 0;
1032 }
1033
azx_runtime_resume(struct device * dev)1034 static int azx_runtime_resume(struct device *dev)
1035 {
1036 struct snd_card *card = dev_get_drvdata(dev);
1037 struct azx *chip;
1038 struct hda_intel *hda;
1039 struct hdac_bus *bus;
1040 struct hda_codec *codec;
1041 int status;
1042
1043 if (!card)
1044 return 0;
1045
1046 chip = card->private_data;
1047 hda = container_of(chip, struct hda_intel, chip);
1048 if (chip->disabled || hda->init_failed)
1049 return 0;
1050
1051 if (!azx_has_pm_runtime(chip))
1052 return 0;
1053
1054 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1055 bus = azx_bus(chip);
1056 if (hda->need_i915_power) {
1057 snd_hdac_display_power(bus, true);
1058 haswell_set_bclk(hda);
1059 } else {
1060 /* toggle codec wakeup bit for STATESTS read */
1061 snd_hdac_set_codec_wakeup(bus, true);
1062 snd_hdac_set_codec_wakeup(bus, false);
1063 }
1064 }
1065
1066 /* Read STATESTS before controller reset */
1067 status = azx_readw(chip, STATESTS);
1068
1069 azx_init_pci(chip);
1070 hda_intel_init_chip(chip, true);
1071
1072 if (status) {
1073 list_for_each_codec(codec, &chip->bus)
1074 if (status & (1 << codec->addr))
1075 schedule_delayed_work(&codec->jackpoll_work,
1076 codec->jackpoll_interval);
1077 }
1078
1079 /* disable controller Wake Up event*/
1080 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1081 ~STATESTS_INT_MASK);
1082
1083 trace_azx_runtime_resume(chip);
1084 return 0;
1085 }
1086
azx_runtime_idle(struct device * dev)1087 static int azx_runtime_idle(struct device *dev)
1088 {
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip;
1091 struct hda_intel *hda;
1092
1093 if (!card)
1094 return 0;
1095
1096 chip = card->private_data;
1097 hda = container_of(chip, struct hda_intel, chip);
1098 if (chip->disabled || hda->init_failed)
1099 return 0;
1100
1101 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1102 azx_bus(chip)->codec_powered || !chip->running)
1103 return -EBUSY;
1104
1105 return 0;
1106 }
1107
1108 static const struct dev_pm_ops azx_pm = {
1109 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1110 #ifdef CONFIG_PM_SLEEP
1111 .freeze_noirq = azx_freeze_noirq,
1112 .thaw_noirq = azx_thaw_noirq,
1113 #endif
1114 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1115 };
1116
1117 #define AZX_PM_OPS &azx_pm
1118 #else
1119 #define AZX_PM_OPS NULL
1120 #endif /* CONFIG_PM */
1121
1122
1123 static int azx_probe_continue(struct azx *chip);
1124
1125 #ifdef SUPPORT_VGA_SWITCHEROO
1126 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1127
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1128 static void azx_vs_set_state(struct pci_dev *pci,
1129 enum vga_switcheroo_state state)
1130 {
1131 struct snd_card *card = pci_get_drvdata(pci);
1132 struct azx *chip = card->private_data;
1133 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1134 bool disabled;
1135
1136 wait_for_completion(&hda->probe_wait);
1137 if (hda->init_failed)
1138 return;
1139
1140 disabled = (state == VGA_SWITCHEROO_OFF);
1141 if (chip->disabled == disabled)
1142 return;
1143
1144 if (!hda->probe_continued) {
1145 chip->disabled = disabled;
1146 if (!disabled) {
1147 dev_info(chip->card->dev,
1148 "Start delayed initialization\n");
1149 if (azx_probe_continue(chip) < 0) {
1150 dev_err(chip->card->dev, "initialization error\n");
1151 hda->init_failed = true;
1152 }
1153 }
1154 } else {
1155 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1156 disabled ? "Disabling" : "Enabling");
1157 if (disabled) {
1158 pm_runtime_put_sync_suspend(card->dev);
1159 azx_suspend(card->dev);
1160 /* when we get suspended by vga_switcheroo we end up in D3cold,
1161 * however we have no ACPI handle, so pci/acpi can't put us there,
1162 * put ourselves there */
1163 pci->current_state = PCI_D3cold;
1164 chip->disabled = true;
1165 if (snd_hda_lock_devices(&chip->bus))
1166 dev_warn(chip->card->dev,
1167 "Cannot lock devices!\n");
1168 } else {
1169 snd_hda_unlock_devices(&chip->bus);
1170 pm_runtime_get_noresume(card->dev);
1171 chip->disabled = false;
1172 azx_resume(card->dev);
1173 }
1174 }
1175 }
1176
azx_vs_can_switch(struct pci_dev * pci)1177 static bool azx_vs_can_switch(struct pci_dev *pci)
1178 {
1179 struct snd_card *card = pci_get_drvdata(pci);
1180 struct azx *chip = card->private_data;
1181 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1182
1183 wait_for_completion(&hda->probe_wait);
1184 if (hda->init_failed)
1185 return false;
1186 if (chip->disabled || !hda->probe_continued)
1187 return true;
1188 if (snd_hda_lock_devices(&chip->bus))
1189 return false;
1190 snd_hda_unlock_devices(&chip->bus);
1191 return true;
1192 }
1193
init_vga_switcheroo(struct azx * chip)1194 static void init_vga_switcheroo(struct azx *chip)
1195 {
1196 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1197 struct pci_dev *p = get_bound_vga(chip->pci);
1198 if (p) {
1199 dev_info(chip->card->dev,
1200 "Handle vga_switcheroo audio client\n");
1201 hda->use_vga_switcheroo = 1;
1202 pci_dev_put(p);
1203 }
1204 }
1205
1206 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1207 .set_gpu_state = azx_vs_set_state,
1208 .can_switch = azx_vs_can_switch,
1209 };
1210
register_vga_switcheroo(struct azx * chip)1211 static int register_vga_switcheroo(struct azx *chip)
1212 {
1213 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1214 int err;
1215
1216 if (!hda->use_vga_switcheroo)
1217 return 0;
1218 /* FIXME: currently only handling DIS controller
1219 * is there any machine with two switchable HDMI audio controllers?
1220 */
1221 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1222 VGA_SWITCHEROO_DIS);
1223 if (err < 0)
1224 return err;
1225 hda->vga_switcheroo_registered = 1;
1226
1227 /* register as an optimus hdmi audio power domain */
1228 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1229 &hda->hdmi_pm_domain);
1230 return 0;
1231 }
1232 #else
1233 #define init_vga_switcheroo(chip) /* NOP */
1234 #define register_vga_switcheroo(chip) 0
1235 #define check_hdmi_disabled(pci) false
1236 #endif /* SUPPORT_VGA_SWITCHER */
1237
1238 /*
1239 * destructor
1240 */
azx_free(struct azx * chip)1241 static int azx_free(struct azx *chip)
1242 {
1243 struct pci_dev *pci = chip->pci;
1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1245 struct hdac_bus *bus = azx_bus(chip);
1246
1247 if (azx_has_pm_runtime(chip) && chip->running)
1248 pm_runtime_get_noresume(&pci->dev);
1249
1250 azx_del_card_list(chip);
1251
1252 hda->init_failed = 1; /* to be sure */
1253 complete_all(&hda->probe_wait);
1254
1255 if (use_vga_switcheroo(hda)) {
1256 if (chip->disabled && hda->probe_continued)
1257 snd_hda_unlock_devices(&chip->bus);
1258 if (hda->vga_switcheroo_registered)
1259 vga_switcheroo_unregister_client(chip->pci);
1260 }
1261
1262 if (bus->chip_init) {
1263 azx_clear_irq_pending(chip);
1264 azx_stop_all_streams(chip);
1265 azx_stop_chip(chip);
1266 }
1267
1268 if (bus->irq >= 0)
1269 free_irq(bus->irq, (void*)chip);
1270 if (chip->msi)
1271 pci_disable_msi(chip->pci);
1272 iounmap(bus->remap_addr);
1273
1274 azx_free_stream_pages(chip);
1275 azx_free_streams(chip);
1276 snd_hdac_bus_exit(bus);
1277
1278 if (chip->region_requested)
1279 pci_release_regions(chip->pci);
1280
1281 pci_disable_device(chip->pci);
1282 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1283 release_firmware(chip->fw);
1284 #endif
1285
1286 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1287 if (hda->need_i915_power)
1288 snd_hdac_display_power(bus, false);
1289 snd_hdac_i915_exit(bus);
1290 }
1291 kfree(hda);
1292
1293 return 0;
1294 }
1295
azx_dev_disconnect(struct snd_device * device)1296 static int azx_dev_disconnect(struct snd_device *device)
1297 {
1298 struct azx *chip = device->device_data;
1299
1300 chip->bus.shutdown = 1;
1301 return 0;
1302 }
1303
azx_dev_free(struct snd_device * device)1304 static int azx_dev_free(struct snd_device *device)
1305 {
1306 return azx_free(device->device_data);
1307 }
1308
1309 #ifdef SUPPORT_VGA_SWITCHEROO
1310 /*
1311 * Check of disabled HDMI controller by vga_switcheroo
1312 */
get_bound_vga(struct pci_dev * pci)1313 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1314 {
1315 struct pci_dev *p;
1316
1317 /* check only discrete GPU */
1318 switch (pci->vendor) {
1319 case PCI_VENDOR_ID_ATI:
1320 case PCI_VENDOR_ID_AMD:
1321 case PCI_VENDOR_ID_NVIDIA:
1322 if (pci->devfn == 1) {
1323 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1324 pci->bus->number, 0);
1325 if (p) {
1326 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1327 return p;
1328 pci_dev_put(p);
1329 }
1330 }
1331 break;
1332 }
1333 return NULL;
1334 }
1335
check_hdmi_disabled(struct pci_dev * pci)1336 static bool check_hdmi_disabled(struct pci_dev *pci)
1337 {
1338 bool vga_inactive = false;
1339 struct pci_dev *p = get_bound_vga(pci);
1340
1341 if (p) {
1342 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1343 vga_inactive = true;
1344 pci_dev_put(p);
1345 }
1346 return vga_inactive;
1347 }
1348 #endif /* SUPPORT_VGA_SWITCHEROO */
1349
1350 /*
1351 * white/black-listing for position_fix
1352 */
1353 static struct snd_pci_quirk position_fix_list[] = {
1354 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1355 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1356 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1357 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1358 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1359 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1360 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1361 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1362 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1363 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1364 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1365 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1366 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1367 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1368 {}
1369 };
1370
check_position_fix(struct azx * chip,int fix)1371 static int check_position_fix(struct azx *chip, int fix)
1372 {
1373 const struct snd_pci_quirk *q;
1374
1375 switch (fix) {
1376 case POS_FIX_AUTO:
1377 case POS_FIX_LPIB:
1378 case POS_FIX_POSBUF:
1379 case POS_FIX_VIACOMBO:
1380 case POS_FIX_COMBO:
1381 return fix;
1382 }
1383
1384 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1385 if (q) {
1386 dev_info(chip->card->dev,
1387 "position_fix set to %d for device %04x:%04x\n",
1388 q->value, q->subvendor, q->subdevice);
1389 return q->value;
1390 }
1391
1392 /* Check VIA/ATI HD Audio Controller exist */
1393 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1394 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1395 return POS_FIX_VIACOMBO;
1396 }
1397 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1398 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1399 return POS_FIX_LPIB;
1400 }
1401 return POS_FIX_AUTO;
1402 }
1403
assign_position_fix(struct azx * chip,int fix)1404 static void assign_position_fix(struct azx *chip, int fix)
1405 {
1406 static azx_get_pos_callback_t callbacks[] = {
1407 [POS_FIX_AUTO] = NULL,
1408 [POS_FIX_LPIB] = azx_get_pos_lpib,
1409 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1410 [POS_FIX_VIACOMBO] = azx_via_get_position,
1411 [POS_FIX_COMBO] = azx_get_pos_lpib,
1412 };
1413
1414 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1415
1416 /* combo mode uses LPIB only for playback */
1417 if (fix == POS_FIX_COMBO)
1418 chip->get_position[1] = NULL;
1419
1420 if (fix == POS_FIX_POSBUF &&
1421 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1422 chip->get_delay[0] = chip->get_delay[1] =
1423 azx_get_delay_from_lpib;
1424 }
1425
1426 }
1427
1428 /*
1429 * black-lists for probe_mask
1430 */
1431 static struct snd_pci_quirk probe_mask_list[] = {
1432 /* Thinkpad often breaks the controller communication when accessing
1433 * to the non-working (or non-existing) modem codec slot.
1434 */
1435 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1436 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1437 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1438 /* broken BIOS */
1439 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1440 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1441 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1442 /* forced codec slots */
1443 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1444 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1445 /* WinFast VP200 H (Teradici) user reported broken communication */
1446 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1447 {}
1448 };
1449
1450 #define AZX_FORCE_CODEC_MASK 0x100
1451
check_probe_mask(struct azx * chip,int dev)1452 static void check_probe_mask(struct azx *chip, int dev)
1453 {
1454 const struct snd_pci_quirk *q;
1455
1456 chip->codec_probe_mask = probe_mask[dev];
1457 if (chip->codec_probe_mask == -1) {
1458 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1459 if (q) {
1460 dev_info(chip->card->dev,
1461 "probe_mask set to 0x%x for device %04x:%04x\n",
1462 q->value, q->subvendor, q->subdevice);
1463 chip->codec_probe_mask = q->value;
1464 }
1465 }
1466
1467 /* check forced option */
1468 if (chip->codec_probe_mask != -1 &&
1469 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1470 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1471 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1472 (int)azx_bus(chip)->codec_mask);
1473 }
1474 }
1475
1476 /*
1477 * white/black-list for enable_msi
1478 */
1479 static struct snd_pci_quirk msi_black_list[] = {
1480 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1481 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1482 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1483 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1484 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1485 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1486 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1487 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1488 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1489 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1490 {}
1491 };
1492
check_msi(struct azx * chip)1493 static void check_msi(struct azx *chip)
1494 {
1495 const struct snd_pci_quirk *q;
1496
1497 if (enable_msi >= 0) {
1498 chip->msi = !!enable_msi;
1499 return;
1500 }
1501 chip->msi = 1; /* enable MSI as default */
1502 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1503 if (q) {
1504 dev_info(chip->card->dev,
1505 "msi for device %04x:%04x set to %d\n",
1506 q->subvendor, q->subdevice, q->value);
1507 chip->msi = q->value;
1508 return;
1509 }
1510
1511 /* NVidia chipsets seem to cause troubles with MSI */
1512 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1513 dev_info(chip->card->dev, "Disabling MSI\n");
1514 chip->msi = 0;
1515 }
1516 }
1517
1518 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1519 static void azx_check_snoop_available(struct azx *chip)
1520 {
1521 int snoop = hda_snoop;
1522
1523 if (snoop >= 0) {
1524 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1525 snoop ? "snoop" : "non-snoop");
1526 chip->snoop = snoop;
1527 return;
1528 }
1529
1530 snoop = true;
1531 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1532 chip->driver_type == AZX_DRIVER_VIA) {
1533 /* force to non-snoop mode for a new VIA controller
1534 * when BIOS is set
1535 */
1536 u8 val;
1537 pci_read_config_byte(chip->pci, 0x42, &val);
1538 if (!(val & 0x80) && chip->pci->revision == 0x30)
1539 snoop = false;
1540 }
1541
1542 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1543 snoop = false;
1544
1545 chip->snoop = snoop;
1546 if (!snoop)
1547 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1548 }
1549
azx_probe_work(struct work_struct * work)1550 static void azx_probe_work(struct work_struct *work)
1551 {
1552 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1553 azx_probe_continue(&hda->chip);
1554 }
1555
1556 /*
1557 * constructor
1558 */
1559 static const struct hdac_io_ops pci_hda_io_ops;
1560 static const struct hda_controller_ops pci_hda_ops;
1561
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1562 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1563 int dev, unsigned int driver_caps,
1564 struct azx **rchip)
1565 {
1566 static struct snd_device_ops ops = {
1567 .dev_disconnect = azx_dev_disconnect,
1568 .dev_free = azx_dev_free,
1569 };
1570 struct hda_intel *hda;
1571 struct azx *chip;
1572 int err;
1573
1574 *rchip = NULL;
1575
1576 err = pci_enable_device(pci);
1577 if (err < 0)
1578 return err;
1579
1580 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1581 if (!hda) {
1582 pci_disable_device(pci);
1583 return -ENOMEM;
1584 }
1585
1586 chip = &hda->chip;
1587 mutex_init(&chip->open_mutex);
1588 chip->card = card;
1589 chip->pci = pci;
1590 chip->ops = &pci_hda_ops;
1591 chip->driver_caps = driver_caps;
1592 chip->driver_type = driver_caps & 0xff;
1593 check_msi(chip);
1594 chip->dev_index = dev;
1595 chip->jackpoll_ms = jackpoll_ms;
1596 INIT_LIST_HEAD(&chip->pcm_list);
1597 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1598 INIT_LIST_HEAD(&hda->list);
1599 init_vga_switcheroo(chip);
1600 init_completion(&hda->probe_wait);
1601
1602 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1603
1604 check_probe_mask(chip, dev);
1605
1606 chip->single_cmd = single_cmd;
1607 azx_check_snoop_available(chip);
1608
1609 if (bdl_pos_adj[dev] < 0) {
1610 switch (chip->driver_type) {
1611 case AZX_DRIVER_ICH:
1612 case AZX_DRIVER_PCH:
1613 bdl_pos_adj[dev] = 1;
1614 break;
1615 default:
1616 bdl_pos_adj[dev] = 32;
1617 break;
1618 }
1619 }
1620 chip->bdl_pos_adj = bdl_pos_adj;
1621
1622 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1623 if (err < 0) {
1624 kfree(hda);
1625 pci_disable_device(pci);
1626 return err;
1627 }
1628
1629 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1630 if (err < 0) {
1631 dev_err(card->dev, "Error creating device [card]!\n");
1632 azx_free(chip);
1633 return err;
1634 }
1635
1636 /* continue probing in work context as may trigger request module */
1637 INIT_WORK(&hda->probe_work, azx_probe_work);
1638
1639 *rchip = chip;
1640
1641 return 0;
1642 }
1643
azx_first_init(struct azx * chip)1644 static int azx_first_init(struct azx *chip)
1645 {
1646 int dev = chip->dev_index;
1647 struct pci_dev *pci = chip->pci;
1648 struct snd_card *card = chip->card;
1649 struct hdac_bus *bus = azx_bus(chip);
1650 int err;
1651 unsigned short gcap;
1652 unsigned int dma_bits = 64;
1653
1654 #if BITS_PER_LONG != 64
1655 /* Fix up base address on ULI M5461 */
1656 if (chip->driver_type == AZX_DRIVER_ULI) {
1657 u16 tmp3;
1658 pci_read_config_word(pci, 0x40, &tmp3);
1659 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1660 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1661 }
1662 #endif
1663
1664 err = pci_request_regions(pci, "ICH HD audio");
1665 if (err < 0)
1666 return err;
1667 chip->region_requested = 1;
1668
1669 bus->addr = pci_resource_start(pci, 0);
1670 bus->remap_addr = pci_ioremap_bar(pci, 0);
1671 if (bus->remap_addr == NULL) {
1672 dev_err(card->dev, "ioremap error\n");
1673 return -ENXIO;
1674 }
1675
1676 if (chip->msi) {
1677 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1678 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1679 pci->no_64bit_msi = true;
1680 }
1681 if (pci_enable_msi(pci) < 0)
1682 chip->msi = 0;
1683 }
1684
1685 if (azx_acquire_irq(chip, 0) < 0)
1686 return -EBUSY;
1687
1688 pci_set_master(pci);
1689 synchronize_irq(bus->irq);
1690
1691 gcap = azx_readw(chip, GCAP);
1692 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1693
1694 /* AMD devices support 40 or 48bit DMA, take the safe one */
1695 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1696 dma_bits = 40;
1697
1698 /* disable SB600 64bit support for safety */
1699 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1700 struct pci_dev *p_smbus;
1701 dma_bits = 40;
1702 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1703 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1704 NULL);
1705 if (p_smbus) {
1706 if (p_smbus->revision < 0x30)
1707 gcap &= ~AZX_GCAP_64OK;
1708 pci_dev_put(p_smbus);
1709 }
1710 }
1711
1712 /* disable 64bit DMA address on some devices */
1713 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1714 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1715 gcap &= ~AZX_GCAP_64OK;
1716 }
1717
1718 /* disable buffer size rounding to 128-byte multiples if supported */
1719 if (align_buffer_size >= 0)
1720 chip->align_buffer_size = !!align_buffer_size;
1721 else {
1722 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1723 chip->align_buffer_size = 0;
1724 else
1725 chip->align_buffer_size = 1;
1726 }
1727
1728 /* allow 64bit DMA address if supported by H/W */
1729 if (!(gcap & AZX_GCAP_64OK))
1730 dma_bits = 32;
1731 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1732 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1733 } else {
1734 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1735 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1736 }
1737
1738 /* read number of streams from GCAP register instead of using
1739 * hardcoded value
1740 */
1741 chip->capture_streams = (gcap >> 8) & 0x0f;
1742 chip->playback_streams = (gcap >> 12) & 0x0f;
1743 if (!chip->playback_streams && !chip->capture_streams) {
1744 /* gcap didn't give any info, switching to old method */
1745
1746 switch (chip->driver_type) {
1747 case AZX_DRIVER_ULI:
1748 chip->playback_streams = ULI_NUM_PLAYBACK;
1749 chip->capture_streams = ULI_NUM_CAPTURE;
1750 break;
1751 case AZX_DRIVER_ATIHDMI:
1752 case AZX_DRIVER_ATIHDMI_NS:
1753 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1754 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1755 break;
1756 case AZX_DRIVER_GENERIC:
1757 default:
1758 chip->playback_streams = ICH6_NUM_PLAYBACK;
1759 chip->capture_streams = ICH6_NUM_CAPTURE;
1760 break;
1761 }
1762 }
1763 chip->capture_index_offset = 0;
1764 chip->playback_index_offset = chip->capture_streams;
1765 chip->num_streams = chip->playback_streams + chip->capture_streams;
1766
1767 /* initialize streams */
1768 err = azx_init_streams(chip);
1769 if (err < 0)
1770 return err;
1771
1772 err = azx_alloc_stream_pages(chip);
1773 if (err < 0)
1774 return err;
1775
1776 /* initialize chip */
1777 azx_init_pci(chip);
1778
1779 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1780 struct hda_intel *hda;
1781
1782 hda = container_of(chip, struct hda_intel, chip);
1783 haswell_set_bclk(hda);
1784 }
1785
1786 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1787
1788 /* codec detection */
1789 if (!azx_bus(chip)->codec_mask) {
1790 dev_err(card->dev, "no codecs found!\n");
1791 return -ENODEV;
1792 }
1793
1794 strcpy(card->driver, "HDA-Intel");
1795 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1796 sizeof(card->shortname));
1797 snprintf(card->longname, sizeof(card->longname),
1798 "%s at 0x%lx irq %i",
1799 card->shortname, bus->addr, bus->irq);
1800
1801 return 0;
1802 }
1803
1804 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1805 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)1806 static void azx_firmware_cb(const struct firmware *fw, void *context)
1807 {
1808 struct snd_card *card = context;
1809 struct azx *chip = card->private_data;
1810 struct pci_dev *pci = chip->pci;
1811
1812 if (!fw) {
1813 dev_err(card->dev, "Cannot load firmware, aborting\n");
1814 goto error;
1815 }
1816
1817 chip->fw = fw;
1818 if (!chip->disabled) {
1819 /* continue probing */
1820 if (azx_probe_continue(chip))
1821 goto error;
1822 }
1823 return; /* OK */
1824
1825 error:
1826 snd_card_free(card);
1827 pci_set_drvdata(pci, NULL);
1828 }
1829 #endif
1830
1831 /*
1832 * HDA controller ops.
1833 */
1834
1835 /* PCI register access. */
pci_azx_writel(u32 value,u32 __iomem * addr)1836 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1837 {
1838 writel(value, addr);
1839 }
1840
pci_azx_readl(u32 __iomem * addr)1841 static u32 pci_azx_readl(u32 __iomem *addr)
1842 {
1843 return readl(addr);
1844 }
1845
pci_azx_writew(u16 value,u16 __iomem * addr)1846 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1847 {
1848 writew(value, addr);
1849 }
1850
pci_azx_readw(u16 __iomem * addr)1851 static u16 pci_azx_readw(u16 __iomem *addr)
1852 {
1853 return readw(addr);
1854 }
1855
pci_azx_writeb(u8 value,u8 __iomem * addr)1856 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1857 {
1858 writeb(value, addr);
1859 }
1860
pci_azx_readb(u8 __iomem * addr)1861 static u8 pci_azx_readb(u8 __iomem *addr)
1862 {
1863 return readb(addr);
1864 }
1865
disable_msi_reset_irq(struct azx * chip)1866 static int disable_msi_reset_irq(struct azx *chip)
1867 {
1868 struct hdac_bus *bus = azx_bus(chip);
1869 int err;
1870
1871 free_irq(bus->irq, chip);
1872 bus->irq = -1;
1873 pci_disable_msi(chip->pci);
1874 chip->msi = 0;
1875 err = azx_acquire_irq(chip, 1);
1876 if (err < 0)
1877 return err;
1878
1879 return 0;
1880 }
1881
1882 /* DMA page allocation helpers. */
dma_alloc_pages(struct hdac_bus * bus,int type,size_t size,struct snd_dma_buffer * buf)1883 static int dma_alloc_pages(struct hdac_bus *bus,
1884 int type,
1885 size_t size,
1886 struct snd_dma_buffer *buf)
1887 {
1888 struct azx *chip = bus_to_azx(bus);
1889 int err;
1890
1891 err = snd_dma_alloc_pages(type,
1892 bus->dev,
1893 size, buf);
1894 if (err < 0)
1895 return err;
1896 mark_pages_wc(chip, buf, true);
1897 return 0;
1898 }
1899
dma_free_pages(struct hdac_bus * bus,struct snd_dma_buffer * buf)1900 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1901 {
1902 struct azx *chip = bus_to_azx(bus);
1903
1904 mark_pages_wc(chip, buf, false);
1905 snd_dma_free_pages(buf);
1906 }
1907
substream_alloc_pages(struct azx * chip,struct snd_pcm_substream * substream,size_t size)1908 static int substream_alloc_pages(struct azx *chip,
1909 struct snd_pcm_substream *substream,
1910 size_t size)
1911 {
1912 struct azx_dev *azx_dev = get_azx_dev(substream);
1913 int ret;
1914
1915 mark_runtime_wc(chip, azx_dev, substream, false);
1916 ret = snd_pcm_lib_malloc_pages(substream, size);
1917 if (ret < 0)
1918 return ret;
1919 mark_runtime_wc(chip, azx_dev, substream, true);
1920 return 0;
1921 }
1922
substream_free_pages(struct azx * chip,struct snd_pcm_substream * substream)1923 static int substream_free_pages(struct azx *chip,
1924 struct snd_pcm_substream *substream)
1925 {
1926 struct azx_dev *azx_dev = get_azx_dev(substream);
1927 mark_runtime_wc(chip, azx_dev, substream, false);
1928 return snd_pcm_lib_free_pages(substream);
1929 }
1930
pcm_mmap_prepare(struct snd_pcm_substream * substream,struct vm_area_struct * area)1931 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1932 struct vm_area_struct *area)
1933 {
1934 #ifdef CONFIG_X86
1935 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1936 struct azx *chip = apcm->chip;
1937 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1938 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1939 #endif
1940 }
1941
1942 static const struct hdac_io_ops pci_hda_io_ops = {
1943 .reg_writel = pci_azx_writel,
1944 .reg_readl = pci_azx_readl,
1945 .reg_writew = pci_azx_writew,
1946 .reg_readw = pci_azx_readw,
1947 .reg_writeb = pci_azx_writeb,
1948 .reg_readb = pci_azx_readb,
1949 .dma_alloc_pages = dma_alloc_pages,
1950 .dma_free_pages = dma_free_pages,
1951 };
1952
1953 static const struct hda_controller_ops pci_hda_ops = {
1954 .disable_msi_reset_irq = disable_msi_reset_irq,
1955 .substream_alloc_pages = substream_alloc_pages,
1956 .substream_free_pages = substream_free_pages,
1957 .pcm_mmap_prepare = pcm_mmap_prepare,
1958 .position_check = azx_position_check,
1959 .link_power = azx_intel_link_power,
1960 };
1961
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1962 static int azx_probe(struct pci_dev *pci,
1963 const struct pci_device_id *pci_id)
1964 {
1965 static int dev;
1966 struct snd_card *card;
1967 struct hda_intel *hda;
1968 struct azx *chip;
1969 bool schedule_probe;
1970 int err;
1971
1972 if (dev >= SNDRV_CARDS)
1973 return -ENODEV;
1974 if (!enable[dev]) {
1975 dev++;
1976 return -ENOENT;
1977 }
1978
1979 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1980 0, &card);
1981 if (err < 0) {
1982 dev_err(&pci->dev, "Error creating card!\n");
1983 return err;
1984 }
1985
1986 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1987 if (err < 0)
1988 goto out_free;
1989 card->private_data = chip;
1990 hda = container_of(chip, struct hda_intel, chip);
1991
1992 pci_set_drvdata(pci, card);
1993
1994 err = register_vga_switcheroo(chip);
1995 if (err < 0) {
1996 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1997 goto out_free;
1998 }
1999
2000 if (check_hdmi_disabled(pci)) {
2001 dev_info(card->dev, "VGA controller is disabled\n");
2002 dev_info(card->dev, "Delaying initialization\n");
2003 chip->disabled = true;
2004 }
2005
2006 schedule_probe = !chip->disabled;
2007
2008 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2009 if (patch[dev] && *patch[dev]) {
2010 dev_info(card->dev, "Applying patch firmware '%s'\n",
2011 patch[dev]);
2012 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2013 &pci->dev, GFP_KERNEL, card,
2014 azx_firmware_cb);
2015 if (err < 0)
2016 goto out_free;
2017 schedule_probe = false; /* continued in azx_firmware_cb() */
2018 }
2019 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2020
2021 #ifndef CONFIG_SND_HDA_I915
2022 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2023 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2024 #endif
2025
2026 if (schedule_probe)
2027 schedule_work(&hda->probe_work);
2028
2029 dev++;
2030 if (chip->disabled)
2031 complete_all(&hda->probe_wait);
2032 return 0;
2033
2034 out_free:
2035 snd_card_free(card);
2036 return err;
2037 }
2038
2039 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2040 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2041 [AZX_DRIVER_NVIDIA] = 8,
2042 [AZX_DRIVER_TERA] = 1,
2043 };
2044
azx_probe_continue(struct azx * chip)2045 static int azx_probe_continue(struct azx *chip)
2046 {
2047 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2048 struct hdac_bus *bus = azx_bus(chip);
2049 struct pci_dev *pci = chip->pci;
2050 int dev = chip->dev_index;
2051 int err;
2052
2053 hda->probe_continued = 1;
2054
2055 /* Request display power well for the HDA controller or codec. For
2056 * Haswell/Broadwell, both the display HDA controller and codec need
2057 * this power. For other platforms, like Baytrail/Braswell, only the
2058 * display codec needs the power and it can be released after probe.
2059 */
2060 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2061 /* HSW/BDW controllers need this power */
2062 if (CONTROLLER_IN_GPU(pci))
2063 hda->need_i915_power = 1;
2064
2065 err = snd_hdac_i915_init(bus);
2066 if (err < 0) {
2067 /* if the controller is bound only with HDMI/DP
2068 * (for HSW and BDW), we need to abort the probe;
2069 * for other chips, still continue probing as other
2070 * codecs can be on the same link.
2071 */
2072 if (CONTROLLER_IN_GPU(pci))
2073 goto out_free;
2074 else
2075 goto skip_i915;
2076 }
2077
2078 err = snd_hdac_display_power(bus, true);
2079 if (err < 0) {
2080 dev_err(chip->card->dev,
2081 "Cannot turn on display power on i915\n");
2082 goto i915_power_fail;
2083 }
2084 }
2085
2086 skip_i915:
2087 err = azx_first_init(chip);
2088 if (err < 0)
2089 goto out_free;
2090
2091 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2092 chip->beep_mode = beep_mode[dev];
2093 #endif
2094
2095 /* create codec instances */
2096 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2097 if (err < 0)
2098 goto out_free;
2099
2100 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2101 if (chip->fw) {
2102 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2103 chip->fw->data);
2104 if (err < 0)
2105 goto out_free;
2106 #ifndef CONFIG_PM
2107 release_firmware(chip->fw); /* no longer needed */
2108 chip->fw = NULL;
2109 #endif
2110 }
2111 #endif
2112 if ((probe_only[dev] & 1) == 0) {
2113 err = azx_codec_configure(chip);
2114 if (err < 0)
2115 goto out_free;
2116 }
2117
2118 err = snd_card_register(chip->card);
2119 if (err < 0)
2120 goto out_free;
2121
2122 chip->running = 1;
2123 azx_add_card_list(chip);
2124 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2125 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2126 pm_runtime_put_noidle(&pci->dev);
2127
2128 out_free:
2129 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2130 && !hda->need_i915_power)
2131 snd_hdac_display_power(bus, false);
2132
2133 i915_power_fail:
2134 if (err < 0)
2135 hda->init_failed = 1;
2136 complete_all(&hda->probe_wait);
2137 return err;
2138 }
2139
azx_remove(struct pci_dev * pci)2140 static void azx_remove(struct pci_dev *pci)
2141 {
2142 struct snd_card *card = pci_get_drvdata(pci);
2143 struct azx *chip;
2144 struct hda_intel *hda;
2145
2146 if (card) {
2147 /* cancel the pending probing work */
2148 chip = card->private_data;
2149 hda = container_of(chip, struct hda_intel, chip);
2150 cancel_work_sync(&hda->probe_work);
2151
2152 snd_card_free(card);
2153 }
2154 }
2155
azx_shutdown(struct pci_dev * pci)2156 static void azx_shutdown(struct pci_dev *pci)
2157 {
2158 struct snd_card *card = pci_get_drvdata(pci);
2159 struct azx *chip;
2160
2161 if (!card)
2162 return;
2163 chip = card->private_data;
2164 if (chip && chip->running)
2165 azx_stop_chip(chip);
2166 }
2167
2168 /* PCI IDs */
2169 static const struct pci_device_id azx_ids[] = {
2170 /* CPT */
2171 { PCI_DEVICE(0x8086, 0x1c20),
2172 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2173 /* PBG */
2174 { PCI_DEVICE(0x8086, 0x1d20),
2175 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2176 /* Panther Point */
2177 { PCI_DEVICE(0x8086, 0x1e20),
2178 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2179 /* Lynx Point */
2180 { PCI_DEVICE(0x8086, 0x8c20),
2181 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2182 /* 9 Series */
2183 { PCI_DEVICE(0x8086, 0x8ca0),
2184 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2185 /* Wellsburg */
2186 { PCI_DEVICE(0x8086, 0x8d20),
2187 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2188 { PCI_DEVICE(0x8086, 0x8d21),
2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2190 /* Lewisburg */
2191 { PCI_DEVICE(0x8086, 0xa1f0),
2192 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2193 { PCI_DEVICE(0x8086, 0xa270),
2194 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2195 /* Lynx Point-LP */
2196 { PCI_DEVICE(0x8086, 0x9c20),
2197 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2198 /* Lynx Point-LP */
2199 { PCI_DEVICE(0x8086, 0x9c21),
2200 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2201 /* Wildcat Point-LP */
2202 { PCI_DEVICE(0x8086, 0x9ca0),
2203 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2204 /* Sunrise Point */
2205 { PCI_DEVICE(0x8086, 0xa170),
2206 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2207 /* Sunrise Point-LP */
2208 { PCI_DEVICE(0x8086, 0x9d70),
2209 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2210 /* Kabylake */
2211 { PCI_DEVICE(0x8086, 0xa171),
2212 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2213 /* Kabylake-LP */
2214 { PCI_DEVICE(0x8086, 0x9d71),
2215 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2216 /* Broxton-P(Apollolake) */
2217 { PCI_DEVICE(0x8086, 0x5a98),
2218 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2219 /* Broxton-T */
2220 { PCI_DEVICE(0x8086, 0x1a98),
2221 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2222 /* Haswell */
2223 { PCI_DEVICE(0x8086, 0x0a0c),
2224 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2225 { PCI_DEVICE(0x8086, 0x0c0c),
2226 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2227 { PCI_DEVICE(0x8086, 0x0d0c),
2228 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2229 /* Broadwell */
2230 { PCI_DEVICE(0x8086, 0x160c),
2231 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2232 /* 5 Series/3400 */
2233 { PCI_DEVICE(0x8086, 0x3b56),
2234 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2235 /* Poulsbo */
2236 { PCI_DEVICE(0x8086, 0x811b),
2237 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2238 /* Oaktrail */
2239 { PCI_DEVICE(0x8086, 0x080a),
2240 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2241 /* BayTrail */
2242 { PCI_DEVICE(0x8086, 0x0f04),
2243 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2244 /* Braswell */
2245 { PCI_DEVICE(0x8086, 0x2284),
2246 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2247 /* ICH6 */
2248 { PCI_DEVICE(0x8086, 0x2668),
2249 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2250 /* ICH7 */
2251 { PCI_DEVICE(0x8086, 0x27d8),
2252 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2253 /* ESB2 */
2254 { PCI_DEVICE(0x8086, 0x269a),
2255 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2256 /* ICH8 */
2257 { PCI_DEVICE(0x8086, 0x284b),
2258 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2259 /* ICH9 */
2260 { PCI_DEVICE(0x8086, 0x293e),
2261 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2262 /* ICH9 */
2263 { PCI_DEVICE(0x8086, 0x293f),
2264 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2265 /* ICH10 */
2266 { PCI_DEVICE(0x8086, 0x3a3e),
2267 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2268 /* ICH10 */
2269 { PCI_DEVICE(0x8086, 0x3a6e),
2270 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2271 /* Generic Intel */
2272 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2273 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2274 .class_mask = 0xffffff,
2275 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2276 /* ATI SB 450/600/700/800/900 */
2277 { PCI_DEVICE(0x1002, 0x437b),
2278 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2279 { PCI_DEVICE(0x1002, 0x4383),
2280 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2281 /* AMD Hudson */
2282 { PCI_DEVICE(0x1022, 0x780d),
2283 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2284 /* ATI HDMI */
2285 { PCI_DEVICE(0x1002, 0x1308),
2286 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2287 { PCI_DEVICE(0x1002, 0x157a),
2288 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2289 { PCI_DEVICE(0x1002, 0x793b),
2290 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2291 { PCI_DEVICE(0x1002, 0x7919),
2292 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2293 { PCI_DEVICE(0x1002, 0x960f),
2294 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2295 { PCI_DEVICE(0x1002, 0x970f),
2296 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2297 { PCI_DEVICE(0x1002, 0x9840),
2298 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2299 { PCI_DEVICE(0x1002, 0xaa00),
2300 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2301 { PCI_DEVICE(0x1002, 0xaa08),
2302 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2303 { PCI_DEVICE(0x1002, 0xaa10),
2304 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2305 { PCI_DEVICE(0x1002, 0xaa18),
2306 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307 { PCI_DEVICE(0x1002, 0xaa20),
2308 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309 { PCI_DEVICE(0x1002, 0xaa28),
2310 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311 { PCI_DEVICE(0x1002, 0xaa30),
2312 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313 { PCI_DEVICE(0x1002, 0xaa38),
2314 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315 { PCI_DEVICE(0x1002, 0xaa40),
2316 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317 { PCI_DEVICE(0x1002, 0xaa48),
2318 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319 { PCI_DEVICE(0x1002, 0xaa50),
2320 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321 { PCI_DEVICE(0x1002, 0xaa58),
2322 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323 { PCI_DEVICE(0x1002, 0xaa60),
2324 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325 { PCI_DEVICE(0x1002, 0xaa68),
2326 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327 { PCI_DEVICE(0x1002, 0xaa80),
2328 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2329 { PCI_DEVICE(0x1002, 0xaa88),
2330 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2331 { PCI_DEVICE(0x1002, 0xaa90),
2332 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2333 { PCI_DEVICE(0x1002, 0xaa98),
2334 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2335 { PCI_DEVICE(0x1002, 0x9902),
2336 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2337 { PCI_DEVICE(0x1002, 0xaaa0),
2338 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2339 { PCI_DEVICE(0x1002, 0xaaa8),
2340 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2341 { PCI_DEVICE(0x1002, 0xaab0),
2342 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2343 { PCI_DEVICE(0x1002, 0xaac0),
2344 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2345 { PCI_DEVICE(0x1002, 0xaac8),
2346 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2347 { PCI_DEVICE(0x1002, 0xaad8),
2348 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2349 { PCI_DEVICE(0x1002, 0xaae8),
2350 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2351 /* VIA VT8251/VT8237A */
2352 { PCI_DEVICE(0x1106, 0x3288),
2353 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2354 /* VIA GFX VT7122/VX900 */
2355 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2356 /* VIA GFX VT6122/VX11 */
2357 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2358 /* SIS966 */
2359 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2360 /* ULI M5461 */
2361 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2362 /* NVIDIA MCP */
2363 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2364 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2365 .class_mask = 0xffffff,
2366 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2367 /* Teradici */
2368 { PCI_DEVICE(0x6549, 0x1200),
2369 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2370 { PCI_DEVICE(0x6549, 0x2200),
2371 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2372 /* Creative X-Fi (CA0110-IBG) */
2373 /* CTHDA chips */
2374 { PCI_DEVICE(0x1102, 0x0010),
2375 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2376 { PCI_DEVICE(0x1102, 0x0012),
2377 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2378 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2379 /* the following entry conflicts with snd-ctxfi driver,
2380 * as ctxfi driver mutates from HD-audio to native mode with
2381 * a special command sequence.
2382 */
2383 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2384 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2385 .class_mask = 0xffffff,
2386 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2387 AZX_DCAPS_NO_64BIT |
2388 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2389 #else
2390 /* this entry seems still valid -- i.e. without emu20kx chip */
2391 { PCI_DEVICE(0x1102, 0x0009),
2392 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2393 AZX_DCAPS_NO_64BIT |
2394 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2395 #endif
2396 /* CM8888 */
2397 { PCI_DEVICE(0x13f6, 0x5011),
2398 .driver_data = AZX_DRIVER_CMEDIA |
2399 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2400 /* Vortex86MX */
2401 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2402 /* VMware HDAudio */
2403 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2404 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2405 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2406 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2407 .class_mask = 0xffffff,
2408 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2409 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2410 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2411 .class_mask = 0xffffff,
2412 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2413 { 0, }
2414 };
2415 MODULE_DEVICE_TABLE(pci, azx_ids);
2416
2417 /* pci_driver definition */
2418 static struct pci_driver azx_driver = {
2419 .name = KBUILD_MODNAME,
2420 .id_table = azx_ids,
2421 .probe = azx_probe,
2422 .remove = azx_remove,
2423 .shutdown = azx_shutdown,
2424 .driver = {
2425 .pm = AZX_PM_OPS,
2426 },
2427 };
2428
2429 module_pci_driver(azx_driver);
2430