1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef FIJI_PP_SMC_H 25 #define FIJI_PP_SMC_H 26 27 #pragma pack(push, 1) 28 29 #define PPSMC_SWSTATE_FLAG_DC 0x01 30 #define PPSMC_SWSTATE_FLAG_UVD 0x02 31 #define PPSMC_SWSTATE_FLAG_VCE 0x04 32 33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 36 37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04 40 41 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 42 43 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 44 #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 45 46 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 47 #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 48 49 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 50 #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 51 52 #define PPSMC_DPM2FLAGS_TDPCLMP 0x01 53 #define PPSMC_DPM2FLAGS_PWRSHFT 0x02 54 #define PPSMC_DPM2FLAGS_OCP 0x04 55 56 #define PPSMC_DISPLAY_WATERMARK_LOW 0 57 #define PPSMC_DISPLAY_WATERMARK_HIGH 1 58 59 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 60 #define PPSMC_STATEFLAG_POWERBOOST 0x02 61 #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 62 #define PPSMC_STATEFLAG_POWERSHIFT 0x08 63 #define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 64 #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 65 #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 66 67 #define FDO_MODE_HARDWARE 0 68 #define FDO_MODE_PIECE_WISE_LINEAR 1 69 70 enum FAN_CONTROL { 71 FAN_CONTROL_FUZZY, 72 FAN_CONTROL_TABLE 73 }; 74 75 //Gemini Modes 76 #define PPSMC_GeminiModeNone 0 //Single GPU board 77 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 78 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 79 80 #define PPSMC_Result_OK ((uint16_t)0x01) 81 #define PPSMC_Result_NoMore ((uint16_t)0x02) 82 #define PPSMC_Result_NotNow ((uint16_t)0x03) 83 #define PPSMC_Result_Failed ((uint16_t)0xFF) 84 #define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) 85 #define PPSMC_Result_UnknownVT ((uint16_t)0xFD) 86 87 typedef uint16_t PPSMC_Result; 88 89 #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) 90 91 #define PPSMC_MSG_Halt ((uint16_t)0x10) 92 #define PPSMC_MSG_Resume ((uint16_t)0x11) 93 #define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) 94 #define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) 95 #define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) 96 #define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) 97 #define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) 98 #define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) 99 #define PPSMC_MSG_LevelUp ((uint16_t)0x18) 100 #define PPSMC_MSG_LevelDown ((uint16_t)0x19) 101 #define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) 102 #define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) 103 #define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) 104 #define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) 105 #define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) 106 #define PPSMC_MSG_ForceHigh ((uint16_t)0x42) 107 #define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) 108 #define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) 109 #define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) 110 #define PPSMC_MSG_EnableCac ((uint16_t)0x53) 111 #define PPSMC_MSG_DisableCac ((uint16_t)0x54) 112 #define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) 113 #define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) 114 #define PPSMC_CACHistoryStart ((uint16_t)0x57) 115 #define PPSMC_CACHistoryStop ((uint16_t)0x58) 116 #define PPSMC_TDPClampingActive ((uint16_t)0x59) 117 #define PPSMC_TDPClampingInactive ((uint16_t)0x5A) 118 #define PPSMC_StartFanControl ((uint16_t)0x5B) 119 #define PPSMC_StopFanControl ((uint16_t)0x5C) 120 #define PPSMC_NoDisplay ((uint16_t)0x5D) 121 #define PPSMC_HasDisplay ((uint16_t)0x5E) 122 #define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) 123 #define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) 124 #define PPSMC_MSG_EnableULV ((uint16_t)0x62) 125 #define PPSMC_MSG_DisableULV ((uint16_t)0x63) 126 #define PPSMC_MSG_EnterULV ((uint16_t)0x64) 127 #define PPSMC_MSG_ExitULV ((uint16_t)0x65) 128 #define PPSMC_PowerShiftActive ((uint16_t)0x6A) 129 #define PPSMC_PowerShiftInactive ((uint16_t)0x6B) 130 #define PPSMC_OCPActive ((uint16_t)0x6C) 131 #define PPSMC_OCPInactive ((uint16_t)0x6D) 132 #define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) 133 #define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) 134 #define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) 135 #define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) 136 #define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) 137 #define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) 138 #define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) 139 #define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) 140 #define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) 141 #define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) 142 #define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) 143 #define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) 144 #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) 145 #define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) 146 #define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) 147 #define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) 148 #define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) 149 #define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) 150 #define PPSMC_FlushDataCache ((uint16_t)0x80) 151 #define PPSMC_FlushInstrCache ((uint16_t)0x81) 152 #define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) 153 #define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) 154 #define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) 155 #define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) 156 #define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) 157 #define PPSMC_MSG_EnableDTE ((uint16_t)0x87) 158 #define PPSMC_MSG_DisableDTE ((uint16_t)0x88) 159 #define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) 160 #define PPSMC_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) 161 #define PPSMC_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) 162 #define PPSMC_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) 163 164 #define PPSMC_MSG_BREAK ((uint16_t)0xF8) 165 166 #define PPSMC_MSG_Test ((uint16_t)0x100) 167 #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t)0x250) 168 #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t)0x251) 169 #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t)0x252) 170 #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t)0x253) 171 #define PPSMC_MSG_LoadUcodes ((uint16_t)0x254) 172 173 typedef uint16_t PPSMC_Msg; 174 175 #define PPSMC_EVENT_STATUS_THERMAL 0x00000001 176 #define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 177 #define PPSMC_EVENT_STATUS_DC 0x00000004 178 #define PPSMC_EVENT_STATUS_GPIO17 0x00000008 179 180 #pragma pack(pop) 181 182 #endif 183