1 /* 2 * The following devices are accessible using this driver using 3 * GPIO_MAJOR (120) and a couple of minor numbers. 4 * 5 * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): 6 * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction 7 * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction 8 * /dev/leds minor 2, Access to leds depending on kernelconfig 9 * /dev/gpiog minor 3 10 * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG 11 * g1-g7 and g25-g31 is both input and outputs but on different pins 12 * Also note that some bits change pins depending on what interfaces 13 * are enabled. 14 */ 15 #ifndef _ASM_ETRAXGPIO_H 16 #define _ASM_ETRAXGPIO_H 17 18 #define GPIO_MINOR_FIRST 0 19 20 #define ETRAXGPIO_IOCTYPE 43 21 22 /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ 23 #define GPIO_MINOR_A 0 24 #define GPIO_MINOR_B 1 25 #define GPIO_MINOR_LEDS 2 26 #define GPIO_MINOR_G 3 27 #define GPIO_MINOR_LAST 3 28 #define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST 29 30 31 /* supported ioctl _IOC_NR's */ 32 33 #define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ 34 #define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ 35 #define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ 36 37 /* the alarm is waited for by select() */ 38 39 #define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ 40 #define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ 41 #define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ 42 43 /* LED ioctl */ 44 #define IO_LEDACTIVE_SET 0x7 /* set active led 45 * 0=off, 1=green, 2=red, 3=yellow */ 46 47 /* GPIO direction ioctl's */ 48 #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ 49 #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, 50 returns mask with current inputs (obsolete) */ 51 #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, 52 returns mask with current outputs (obsolete)*/ 53 54 /* LED ioctl extended */ 55 #define IO_LED_SETBIT 0xB 56 #define IO_LED_CLRBIT 0xC 57 58 /* SHUTDOWN ioctl */ 59 #define IO_SHUTDOWN 0xD 60 #define IO_GET_PWR_BT 0xE 61 62 /* Bit toggling in driver settings */ 63 /* bit set in low byte0 is CLK mask (0x00FF), 64 bit set in byte1 is DATA mask (0xFF00) 65 msb, data_mask[7:0] , clk_mask[7:0] 66 */ 67 #define IO_CFG_WRITE_MODE 0xF 68 #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ 69 ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) 70 71 /* The following 4 ioctl's take a pointer as argument and handles 72 * 32 bit ports (port G) properly. 73 * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT 74 */ 75 #define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ 76 #define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ 77 #define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ 78 /* *arg updated with current input pins. */ 79 #define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ 80 /* *arg updated with current output pins. */ 81 82 #endif 83