1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
54 #include <linux/mm.h>
55 #include <linux/vmalloc.h>
56 #include <linux/delay.h>
57 #include <linux/interrupt.h>
58 #include <linux/uaccess.h>
59 #include <linux/fb.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/ioport.h>
63 #include <linux/console.h>
64 #include <linux/backlight.h>
65 #include <asm/io.h>
66
67 #ifdef CONFIG_PPC_PMAC
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
70 #include <asm/prom.h>
71 #include <asm/pci-bridge.h>
72 #include "../macmodes.h"
73 #endif
74
75 #ifdef CONFIG_PMAC_BACKLIGHT
76 #include <asm/backlight.h>
77 #endif
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
82
83 #ifdef CONFIG_MTRR
84 #include <asm/mtrr.h>
85 #endif
86
87 #include <video/aty128.h>
88
89 /* Debug flag */
90 #undef DEBUG
91
92 #ifdef DEBUG
93 #define DBG(fmt, args...) \
94 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
95 #else
96 #define DBG(fmt, args...)
97 #endif
98
99 #ifndef CONFIG_PPC_PMAC
100 /* default mode */
101 static struct fb_var_screeninfo default_var = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107 };
108
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119 };
120 #endif /* CONFIG_PPC_PMAC */
121
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137 };
138
139 /* Chip generations */
140 enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149 };
150
151 /* Must match above enum */
152 static char * const r128_family[] = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161 };
162
163 /*
164 * PCI driver prototypes
165 */
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
172
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270 };
271
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274 static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = aty128_remove,
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281 };
282
283 /* packed BIOS settings */
284 #ifndef CONFIG_PPC
285 typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
310
311 /* onboard memory information */
312 struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324 };
325
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 = {
328 .ML = 4,
329 .MB = 4,
330 .Trcd = 3,
331 .Trp = 3,
332 .Twr = 1,
333 .CL = 3,
334 .Tr2w = 1,
335 .LoopLatency = 16,
336 .DspOn = 30,
337 .Rloop = 16,
338 .name = "128-bit SDR SGRAM (1:1)",
339 };
340
341 static const struct aty128_meminfo sdr_64 = {
342 .ML = 4,
343 .MB = 8,
344 .Trcd = 3,
345 .Trp = 3,
346 .Twr = 1,
347 .CL = 3,
348 .Tr2w = 1,
349 .LoopLatency = 17,
350 .DspOn = 46,
351 .Rloop = 17,
352 .name = "64-bit SDR SGRAM (1:1)",
353 };
354
355 static const struct aty128_meminfo sdr_sgram = {
356 .ML = 4,
357 .MB = 4,
358 .Trcd = 1,
359 .Trp = 2,
360 .Twr = 1,
361 .CL = 2,
362 .Tr2w = 1,
363 .LoopLatency = 16,
364 .DspOn = 24,
365 .Rloop = 16,
366 .name = "64-bit SDR SGRAM (2:1)",
367 };
368
369 static const struct aty128_meminfo ddr_sgram = {
370 .ML = 4,
371 .MB = 4,
372 .Trcd = 3,
373 .Trp = 3,
374 .Twr = 2,
375 .CL = 3,
376 .Tr2w = 1,
377 .LoopLatency = 16,
378 .DspOn = 31,
379 .Rloop = 16,
380 .name = "64-bit DDR SGRAM",
381 };
382
383 static struct fb_fix_screeninfo aty128fb_fix = {
384 .id = "ATY Rage128",
385 .type = FB_TYPE_PACKED_PIXELS,
386 .visual = FB_VISUAL_PSEUDOCOLOR,
387 .xpanstep = 8,
388 .ypanstep = 1,
389 .mmio_len = 0x2000,
390 .accel = FB_ACCEL_ATI_RAGE128,
391 };
392
393 static char *mode_option = NULL;
394
395 #ifdef CONFIG_PPC_PMAC
396 static int default_vmode = VMODE_1024_768_60;
397 static int default_cmode = CMODE_8;
398 #endif
399
400 static int default_crt_on = 0;
401 static int default_lcd_on = 1;
402
403 #ifdef CONFIG_MTRR
404 static bool mtrr = true;
405 #endif
406
407 #ifdef CONFIG_FB_ATY128_BACKLIGHT
408 #ifdef CONFIG_PMAC_BACKLIGHT
409 static int backlight = 1;
410 #else
411 static int backlight = 0;
412 #endif
413 #endif
414
415 /* PLL constants */
416 struct aty128_constants {
417 u32 ref_clk;
418 u32 ppll_min;
419 u32 ppll_max;
420 u32 ref_divider;
421 u32 xclk;
422 u32 fifo_width;
423 u32 fifo_depth;
424 };
425
426 struct aty128_crtc {
427 u32 gen_cntl;
428 u32 h_total, h_sync_strt_wid;
429 u32 v_total, v_sync_strt_wid;
430 u32 pitch;
431 u32 offset, offset_cntl;
432 u32 xoffset, yoffset;
433 u32 vxres, vyres;
434 u32 depth, bpp;
435 };
436
437 struct aty128_pll {
438 u32 post_divider;
439 u32 feedback_divider;
440 u32 vclk;
441 };
442
443 struct aty128_ddafifo {
444 u32 dda_config;
445 u32 dda_on_off;
446 };
447
448 /* register values for a specific mode */
449 struct aty128fb_par {
450 struct aty128_crtc crtc;
451 struct aty128_pll pll;
452 struct aty128_ddafifo fifo_reg;
453 u32 accel_flags;
454 struct aty128_constants constants; /* PLL and others */
455 void __iomem *regbase; /* remapped mmio */
456 u32 vram_size; /* onboard video ram */
457 int chip_gen;
458 const struct aty128_meminfo *mem; /* onboard mem info */
459 #ifdef CONFIG_MTRR
460 struct { int vram; int vram_valid; } mtrr;
461 #endif
462 int blitter_may_be_busy;
463 int fifo_slots; /* free slots in FIFO (64 max) */
464
465 int crt_on, lcd_on;
466 struct pci_dev *pdev;
467 struct fb_info *next;
468 int asleep;
469 int lock_blank;
470
471 u8 red[32]; /* see aty128fb_setcolreg */
472 u8 green[64];
473 u8 blue[32];
474 u32 pseudo_palette[16]; /* used for TRUECOLOR */
475 };
476
477
478 #define round_div(n, d) ((n+(d/2))/d)
479
480 static int aty128fb_check_var(struct fb_var_screeninfo *var,
481 struct fb_info *info);
482 static int aty128fb_set_par(struct fb_info *info);
483 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
484 u_int transp, struct fb_info *info);
485 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
486 struct fb_info *fb);
487 static int aty128fb_blank(int blank, struct fb_info *fb);
488 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
489 static int aty128fb_sync(struct fb_info *info);
490
491 /*
492 * Internal routines
493 */
494
495 static int aty128_encode_var(struct fb_var_screeninfo *var,
496 const struct aty128fb_par *par);
497 static int aty128_decode_var(struct fb_var_screeninfo *var,
498 struct aty128fb_par *par);
499 #if 0
500 static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios);
501 static void __iomem *aty128_map_ROM(struct pci_dev *pdev,
502 const struct aty128fb_par *par);
503 #endif
504 static void aty128_timings(struct aty128fb_par *par);
505 static void aty128_init_engine(struct aty128fb_par *par);
506 static void aty128_reset_engine(const struct aty128fb_par *par);
507 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
508 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
509 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
510 static void wait_for_idle(struct aty128fb_par *par);
511 static u32 depth_to_dst(u32 depth);
512
513 #ifdef CONFIG_FB_ATY128_BACKLIGHT
514 static void aty128_bl_set_power(struct fb_info *info, int power);
515 #endif
516
517 #define BIOS_IN8(v) (readb(bios + (v)))
518 #define BIOS_IN16(v) (readb(bios + (v)) | \
519 (readb(bios + (v) + 1) << 8))
520 #define BIOS_IN32(v) (readb(bios + (v)) | \
521 (readb(bios + (v) + 1) << 8) | \
522 (readb(bios + (v) + 2) << 16) | \
523 (readb(bios + (v) + 3) << 24))
524
525
526 static struct fb_ops aty128fb_ops = {
527 .owner = THIS_MODULE,
528 .fb_check_var = aty128fb_check_var,
529 .fb_set_par = aty128fb_set_par,
530 .fb_setcolreg = aty128fb_setcolreg,
531 .fb_pan_display = aty128fb_pan_display,
532 .fb_blank = aty128fb_blank,
533 .fb_ioctl = aty128fb_ioctl,
534 .fb_sync = aty128fb_sync,
535 .fb_fillrect = cfb_fillrect,
536 .fb_copyarea = cfb_copyarea,
537 .fb_imageblit = cfb_imageblit,
538 };
539
540 /*
541 * Functions to read from/write to the mmio registers
542 * - endian conversions may possibly be avoided by
543 * using the other register aperture. TODO.
544 */
_aty_ld_le32(volatile unsigned int regindex,const struct aty128fb_par * par)545 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
546 const struct aty128fb_par *par)
547 {
548 return readl (par->regbase + regindex);
549 }
550
_aty_st_le32(volatile unsigned int regindex,u32 val,const struct aty128fb_par * par)551 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
552 const struct aty128fb_par *par)
553 {
554 writel (val, par->regbase + regindex);
555 }
556
_aty_ld_8(unsigned int regindex,const struct aty128fb_par * par)557 static inline u8 _aty_ld_8(unsigned int regindex,
558 const struct aty128fb_par *par)
559 {
560 return readb (par->regbase + regindex);
561 }
562
_aty_st_8(unsigned int regindex,u8 val,const struct aty128fb_par * par)563 static inline void _aty_st_8(unsigned int regindex, u8 val,
564 const struct aty128fb_par *par)
565 {
566 writeb (val, par->regbase + regindex);
567 }
568
569 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
570 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
571 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
572 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
573
574 /*
575 * Functions to read from/write to the pll registers
576 */
577
578 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
579 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
580
581
_aty_ld_pll(unsigned int pll_index,const struct aty128fb_par * par)582 static u32 _aty_ld_pll(unsigned int pll_index,
583 const struct aty128fb_par *par)
584 {
585 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
586 return aty_ld_le32(CLOCK_CNTL_DATA);
587 }
588
589
_aty_st_pll(unsigned int pll_index,u32 val,const struct aty128fb_par * par)590 static void _aty_st_pll(unsigned int pll_index, u32 val,
591 const struct aty128fb_par *par)
592 {
593 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
594 aty_st_le32(CLOCK_CNTL_DATA, val);
595 }
596
597
598 /* return true when the PLL has completed an atomic update */
aty_pll_readupdate(const struct aty128fb_par * par)599 static int aty_pll_readupdate(const struct aty128fb_par *par)
600 {
601 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
602 }
603
604
aty_pll_wait_readupdate(const struct aty128fb_par * par)605 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
606 {
607 unsigned long timeout = jiffies + HZ/100; // should be more than enough
608 int reset = 1;
609
610 while (time_before(jiffies, timeout))
611 if (aty_pll_readupdate(par)) {
612 reset = 0;
613 break;
614 }
615
616 if (reset) /* reset engine?? */
617 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
618 }
619
620
621 /* tell PLL to update */
aty_pll_writeupdate(const struct aty128fb_par * par)622 static void aty_pll_writeupdate(const struct aty128fb_par *par)
623 {
624 aty_pll_wait_readupdate(par);
625
626 aty_st_pll(PPLL_REF_DIV,
627 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
628 }
629
630
631 /* write to the scratch register to test r/w functionality */
register_test(const struct aty128fb_par * par)632 static int register_test(const struct aty128fb_par *par)
633 {
634 u32 val;
635 int flag = 0;
636
637 val = aty_ld_le32(BIOS_0_SCRATCH);
638
639 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
640 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
641 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
642
643 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
644 flag = 1;
645 }
646
647 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
648 return flag;
649 }
650
651
652 /*
653 * Accelerator engine functions
654 */
do_wait_for_fifo(u16 entries,struct aty128fb_par * par)655 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
656 {
657 int i;
658
659 for (;;) {
660 for (i = 0; i < 2000000; i++) {
661 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
662 if (par->fifo_slots >= entries)
663 return;
664 }
665 aty128_reset_engine(par);
666 }
667 }
668
669
wait_for_idle(struct aty128fb_par * par)670 static void wait_for_idle(struct aty128fb_par *par)
671 {
672 int i;
673
674 do_wait_for_fifo(64, par);
675
676 for (;;) {
677 for (i = 0; i < 2000000; i++) {
678 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
679 aty128_flush_pixel_cache(par);
680 par->blitter_may_be_busy = 0;
681 return;
682 }
683 }
684 aty128_reset_engine(par);
685 }
686 }
687
688
wait_for_fifo(u16 entries,struct aty128fb_par * par)689 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
690 {
691 if (par->fifo_slots < entries)
692 do_wait_for_fifo(64, par);
693 par->fifo_slots -= entries;
694 }
695
696
aty128_flush_pixel_cache(const struct aty128fb_par * par)697 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
698 {
699 int i;
700 u32 tmp;
701
702 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
703 tmp &= ~(0x00ff);
704 tmp |= 0x00ff;
705 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
706
707 for (i = 0; i < 2000000; i++)
708 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
709 break;
710 }
711
712
aty128_reset_engine(const struct aty128fb_par * par)713 static void aty128_reset_engine(const struct aty128fb_par *par)
714 {
715 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
716
717 aty128_flush_pixel_cache(par);
718
719 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
720 mclk_cntl = aty_ld_pll(MCLK_CNTL);
721
722 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
723
724 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
725 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
726 aty_ld_le32(GEN_RESET_CNTL);
727 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
728 aty_ld_le32(GEN_RESET_CNTL);
729
730 aty_st_pll(MCLK_CNTL, mclk_cntl);
731 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
732 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
733
734 /* use old pio mode */
735 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
736
737 DBG("engine reset");
738 }
739
740
aty128_init_engine(struct aty128fb_par * par)741 static void aty128_init_engine(struct aty128fb_par *par)
742 {
743 u32 pitch_value;
744
745 wait_for_idle(par);
746
747 /* 3D scaler not spoken here */
748 wait_for_fifo(1, par);
749 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
750
751 aty128_reset_engine(par);
752
753 pitch_value = par->crtc.pitch;
754 if (par->crtc.bpp == 24) {
755 pitch_value = pitch_value * 3;
756 }
757
758 wait_for_fifo(4, par);
759 /* setup engine offset registers */
760 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
761
762 /* setup engine pitch registers */
763 aty_st_le32(DEFAULT_PITCH, pitch_value);
764
765 /* set the default scissor register to max dimensions */
766 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
767
768 /* set the drawing controls registers */
769 aty_st_le32(DP_GUI_MASTER_CNTL,
770 GMC_SRC_PITCH_OFFSET_DEFAULT |
771 GMC_DST_PITCH_OFFSET_DEFAULT |
772 GMC_SRC_CLIP_DEFAULT |
773 GMC_DST_CLIP_DEFAULT |
774 GMC_BRUSH_SOLIDCOLOR |
775 (depth_to_dst(par->crtc.depth) << 8) |
776 GMC_SRC_DSTCOLOR |
777 GMC_BYTE_ORDER_MSB_TO_LSB |
778 GMC_DP_CONVERSION_TEMP_6500 |
779 ROP3_PATCOPY |
780 GMC_DP_SRC_RECT |
781 GMC_3D_FCN_EN_CLR |
782 GMC_DST_CLR_CMP_FCN_CLEAR |
783 GMC_AUX_CLIP_CLEAR |
784 GMC_WRITE_MASK_SET);
785
786 wait_for_fifo(8, par);
787 /* clear the line drawing registers */
788 aty_st_le32(DST_BRES_ERR, 0);
789 aty_st_le32(DST_BRES_INC, 0);
790 aty_st_le32(DST_BRES_DEC, 0);
791
792 /* set brush color registers */
793 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
794 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
795
796 /* set source color registers */
797 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
798 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
799
800 /* default write mask */
801 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
802
803 /* Wait for all the writes to be completed before returning */
804 wait_for_idle(par);
805 }
806
807
808 /* convert depth values to their register representation */
depth_to_dst(u32 depth)809 static u32 depth_to_dst(u32 depth)
810 {
811 if (depth <= 8)
812 return DST_8BPP;
813 else if (depth <= 15)
814 return DST_15BPP;
815 else if (depth == 16)
816 return DST_16BPP;
817 else if (depth <= 24)
818 return DST_24BPP;
819 else if (depth <= 32)
820 return DST_32BPP;
821
822 return -EINVAL;
823 }
824
825 /*
826 * PLL informations retreival
827 */
828
829
830 #ifndef __sparc__
aty128_map_ROM(const struct aty128fb_par * par,struct pci_dev * dev)831 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
832 struct pci_dev *dev)
833 {
834 u16 dptr;
835 u8 rom_type;
836 void __iomem *bios;
837 size_t rom_size;
838
839 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
840 unsigned int temp;
841 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
842 temp &= 0x00ffffffu;
843 temp |= 0x04 << 24;
844 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
845 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
846
847 bios = pci_map_rom(dev, &rom_size);
848
849 if (!bios) {
850 printk(KERN_ERR "aty128fb: ROM failed to map\n");
851 return NULL;
852 }
853
854 /* Very simple test to make sure it appeared */
855 if (BIOS_IN16(0) != 0xaa55) {
856 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
857 " be 0xaa55\n", BIOS_IN16(0));
858 goto failed;
859 }
860
861 /* Look for the PCI data to check the ROM type */
862 dptr = BIOS_IN16(0x18);
863
864 /* Check the PCI data signature. If it's wrong, we still assume a normal
865 * x86 ROM for now, until I've verified this works everywhere.
866 * The goal here is more to phase out Open Firmware images.
867 *
868 * Currently, we only look at the first PCI data, we could iteratre and
869 * deal with them all, and we should use fb_bios_start relative to start
870 * of image and not relative start of ROM, but so far, I never found a
871 * dual-image ATI card.
872 *
873 * typedef struct {
874 * u32 signature; + 0x00
875 * u16 vendor; + 0x04
876 * u16 device; + 0x06
877 * u16 reserved_1; + 0x08
878 * u16 dlen; + 0x0a
879 * u8 drevision; + 0x0c
880 * u8 class_hi; + 0x0d
881 * u16 class_lo; + 0x0e
882 * u16 ilen; + 0x10
883 * u16 irevision; + 0x12
884 * u8 type; + 0x14
885 * u8 indicator; + 0x15
886 * u16 reserved_2; + 0x16
887 * } pci_data_t;
888 */
889 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
890 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
891 BIOS_IN32(dptr));
892 goto anyway;
893 }
894 rom_type = BIOS_IN8(dptr + 0x14);
895 switch(rom_type) {
896 case 0:
897 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
898 break;
899 case 1:
900 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
901 goto failed;
902 case 2:
903 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
904 goto failed;
905 default:
906 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
907 rom_type);
908 goto failed;
909 }
910 anyway:
911 return bios;
912
913 failed:
914 pci_unmap_rom(dev, bios);
915 return NULL;
916 }
917
aty128_get_pllinfo(struct aty128fb_par * par,unsigned char __iomem * bios)918 static void aty128_get_pllinfo(struct aty128fb_par *par,
919 unsigned char __iomem *bios)
920 {
921 unsigned int bios_hdr;
922 unsigned int bios_pll;
923
924 bios_hdr = BIOS_IN16(0x48);
925 bios_pll = BIOS_IN16(bios_hdr + 0x30);
926
927 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
928 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
929 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
930 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
931 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
932
933 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
934 par->constants.ppll_max, par->constants.ppll_min,
935 par->constants.xclk, par->constants.ref_divider,
936 par->constants.ref_clk);
937
938 }
939
940 #ifdef CONFIG_X86
aty128_find_mem_vbios(struct aty128fb_par * par)941 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
942 {
943 /* I simplified this code as we used to miss the signatures in
944 * a lot of case. It's now closer to XFree, we just don't check
945 * for signatures at all... Something better will have to be done
946 * if we end up having conflicts
947 */
948 u32 segstart;
949 unsigned char __iomem *rom_base = NULL;
950
951 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
952 rom_base = ioremap(segstart, 0x10000);
953 if (rom_base == NULL)
954 return NULL;
955 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
956 break;
957 iounmap(rom_base);
958 rom_base = NULL;
959 }
960 return rom_base;
961 }
962 #endif
963 #endif /* ndef(__sparc__) */
964
965 /* fill in known card constants if pll_block is not available */
aty128_timings(struct aty128fb_par * par)966 static void aty128_timings(struct aty128fb_par *par)
967 {
968 #ifdef CONFIG_PPC
969 /* instead of a table lookup, assume OF has properly
970 * setup the PLL registers and use their values
971 * to set the XCLK values and reference divider values */
972
973 u32 x_mpll_ref_fb_div;
974 u32 xclk_cntl;
975 u32 Nx, M;
976 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
977 #endif
978
979 if (!par->constants.ref_clk)
980 par->constants.ref_clk = 2950;
981
982 #ifdef CONFIG_PPC
983 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
984 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
985 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
986 M = x_mpll_ref_fb_div & 0x0000ff;
987
988 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
989 (M * PostDivSet[xclk_cntl]));
990
991 par->constants.ref_divider =
992 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
993 #endif
994
995 if (!par->constants.ref_divider) {
996 par->constants.ref_divider = 0x3b;
997
998 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
999 aty_pll_writeupdate(par);
1000 }
1001 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
1002 aty_pll_writeupdate(par);
1003
1004 /* from documentation */
1005 if (!par->constants.ppll_min)
1006 par->constants.ppll_min = 12500;
1007 if (!par->constants.ppll_max)
1008 par->constants.ppll_max = 25000; /* 23000 on some cards? */
1009 if (!par->constants.xclk)
1010 par->constants.xclk = 0x1d4d; /* same as mclk */
1011
1012 par->constants.fifo_width = 128;
1013 par->constants.fifo_depth = 32;
1014
1015 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1016 case 0:
1017 par->mem = &sdr_128;
1018 break;
1019 case 1:
1020 par->mem = &sdr_sgram;
1021 break;
1022 case 2:
1023 par->mem = &ddr_sgram;
1024 break;
1025 default:
1026 par->mem = &sdr_sgram;
1027 }
1028 }
1029
1030
1031
1032 /*
1033 * CRTC programming
1034 */
1035
1036 /* Program the CRTC registers */
aty128_set_crtc(const struct aty128_crtc * crtc,const struct aty128fb_par * par)1037 static void aty128_set_crtc(const struct aty128_crtc *crtc,
1038 const struct aty128fb_par *par)
1039 {
1040 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
1041 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
1042 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1043 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1044 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1045 aty_st_le32(CRTC_PITCH, crtc->pitch);
1046 aty_st_le32(CRTC_OFFSET, crtc->offset);
1047 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1048 /* Disable ATOMIC updating. Is this the right place? */
1049 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1050 }
1051
1052
aty128_var_to_crtc(const struct fb_var_screeninfo * var,struct aty128_crtc * crtc,const struct aty128fb_par * par)1053 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1054 struct aty128_crtc *crtc,
1055 const struct aty128fb_par *par)
1056 {
1057 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1058 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1059 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1060 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1061 u32 depth, bytpp;
1062 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1063
1064 /* input */
1065 xres = var->xres;
1066 yres = var->yres;
1067 vxres = var->xres_virtual;
1068 vyres = var->yres_virtual;
1069 xoffset = var->xoffset;
1070 yoffset = var->yoffset;
1071 bpp = var->bits_per_pixel;
1072 left = var->left_margin;
1073 right = var->right_margin;
1074 upper = var->upper_margin;
1075 lower = var->lower_margin;
1076 hslen = var->hsync_len;
1077 vslen = var->vsync_len;
1078 sync = var->sync;
1079 vmode = var->vmode;
1080
1081 if (bpp != 16)
1082 depth = bpp;
1083 else
1084 depth = (var->green.length == 6) ? 16 : 15;
1085
1086 /* check for mode eligibility
1087 * accept only non interlaced modes */
1088 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1089 return -EINVAL;
1090
1091 /* convert (and round up) and validate */
1092 xres = (xres + 7) & ~7;
1093 xoffset = (xoffset + 7) & ~7;
1094
1095 if (vxres < xres + xoffset)
1096 vxres = xres + xoffset;
1097
1098 if (vyres < yres + yoffset)
1099 vyres = yres + yoffset;
1100
1101 /* convert depth into ATI register depth */
1102 dst = depth_to_dst(depth);
1103
1104 if (dst == -EINVAL) {
1105 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1106 return -EINVAL;
1107 }
1108
1109 /* convert register depth to bytes per pixel */
1110 bytpp = mode_bytpp[dst];
1111
1112 /* make sure there is enough video ram for the mode */
1113 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1114 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1115 return -EINVAL;
1116 }
1117
1118 h_disp = (xres >> 3) - 1;
1119 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1120
1121 v_disp = yres - 1;
1122 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1123
1124 /* check to make sure h_total and v_total are in range */
1125 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1126 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1127 return -EINVAL;
1128 }
1129
1130 h_sync_wid = (hslen + 7) >> 3;
1131 if (h_sync_wid == 0)
1132 h_sync_wid = 1;
1133 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1134 h_sync_wid = 0x3f;
1135
1136 h_sync_strt = (h_disp << 3) + right;
1137
1138 v_sync_wid = vslen;
1139 if (v_sync_wid == 0)
1140 v_sync_wid = 1;
1141 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1142 v_sync_wid = 0x1f;
1143
1144 v_sync_strt = v_disp + lower;
1145
1146 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1147 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1148
1149 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1150
1151 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1152
1153 crtc->h_total = h_total | (h_disp << 16);
1154 crtc->v_total = v_total | (v_disp << 16);
1155
1156 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1157 (h_sync_pol << 23);
1158 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1159 (v_sync_pol << 23);
1160
1161 crtc->pitch = vxres >> 3;
1162
1163 crtc->offset = 0;
1164
1165 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1166 crtc->offset_cntl = 0x00010000;
1167 else
1168 crtc->offset_cntl = 0;
1169
1170 crtc->vxres = vxres;
1171 crtc->vyres = vyres;
1172 crtc->xoffset = xoffset;
1173 crtc->yoffset = yoffset;
1174 crtc->depth = depth;
1175 crtc->bpp = bpp;
1176
1177 return 0;
1178 }
1179
1180
aty128_pix_width_to_var(int pix_width,struct fb_var_screeninfo * var)1181 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1182 {
1183
1184 /* fill in pixel info */
1185 var->red.msb_right = 0;
1186 var->green.msb_right = 0;
1187 var->blue.offset = 0;
1188 var->blue.msb_right = 0;
1189 var->transp.offset = 0;
1190 var->transp.length = 0;
1191 var->transp.msb_right = 0;
1192 switch (pix_width) {
1193 case CRTC_PIX_WIDTH_8BPP:
1194 var->bits_per_pixel = 8;
1195 var->red.offset = 0;
1196 var->red.length = 8;
1197 var->green.offset = 0;
1198 var->green.length = 8;
1199 var->blue.length = 8;
1200 break;
1201 case CRTC_PIX_WIDTH_15BPP:
1202 var->bits_per_pixel = 16;
1203 var->red.offset = 10;
1204 var->red.length = 5;
1205 var->green.offset = 5;
1206 var->green.length = 5;
1207 var->blue.length = 5;
1208 break;
1209 case CRTC_PIX_WIDTH_16BPP:
1210 var->bits_per_pixel = 16;
1211 var->red.offset = 11;
1212 var->red.length = 5;
1213 var->green.offset = 5;
1214 var->green.length = 6;
1215 var->blue.length = 5;
1216 break;
1217 case CRTC_PIX_WIDTH_24BPP:
1218 var->bits_per_pixel = 24;
1219 var->red.offset = 16;
1220 var->red.length = 8;
1221 var->green.offset = 8;
1222 var->green.length = 8;
1223 var->blue.length = 8;
1224 break;
1225 case CRTC_PIX_WIDTH_32BPP:
1226 var->bits_per_pixel = 32;
1227 var->red.offset = 16;
1228 var->red.length = 8;
1229 var->green.offset = 8;
1230 var->green.length = 8;
1231 var->blue.length = 8;
1232 var->transp.offset = 24;
1233 var->transp.length = 8;
1234 break;
1235 default:
1236 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1237 return -EINVAL;
1238 }
1239
1240 return 0;
1241 }
1242
1243
aty128_crtc_to_var(const struct aty128_crtc * crtc,struct fb_var_screeninfo * var)1244 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1245 struct fb_var_screeninfo *var)
1246 {
1247 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1248 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1249 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1250 u32 pix_width;
1251
1252 /* fun with masking */
1253 h_total = crtc->h_total & 0x1ff;
1254 h_disp = (crtc->h_total >> 16) & 0xff;
1255 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1256 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1257 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1258 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1259 v_total = crtc->v_total & 0x7ff;
1260 v_disp = (crtc->v_total >> 16) & 0x7ff;
1261 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1262 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1263 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1264 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1265 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1266
1267 /* do conversions */
1268 xres = (h_disp + 1) << 3;
1269 yres = v_disp + 1;
1270 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1271 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1272 hslen = h_sync_wid << 3;
1273 upper = v_total - v_sync_strt - v_sync_wid;
1274 lower = v_sync_strt - v_disp;
1275 vslen = v_sync_wid;
1276 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1277 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1278 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1279
1280 aty128_pix_width_to_var(pix_width, var);
1281
1282 var->xres = xres;
1283 var->yres = yres;
1284 var->xres_virtual = crtc->vxres;
1285 var->yres_virtual = crtc->vyres;
1286 var->xoffset = crtc->xoffset;
1287 var->yoffset = crtc->yoffset;
1288 var->left_margin = left;
1289 var->right_margin = right;
1290 var->upper_margin = upper;
1291 var->lower_margin = lower;
1292 var->hsync_len = hslen;
1293 var->vsync_len = vslen;
1294 var->sync = sync;
1295 var->vmode = FB_VMODE_NONINTERLACED;
1296
1297 return 0;
1298 }
1299
aty128_set_crt_enable(struct aty128fb_par * par,int on)1300 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1301 {
1302 if (on) {
1303 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1304 CRT_CRTC_ON);
1305 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1306 DAC_PALETTE2_SNOOP_EN));
1307 } else
1308 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1309 ~CRT_CRTC_ON);
1310 }
1311
aty128_set_lcd_enable(struct aty128fb_par * par,int on)1312 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1313 {
1314 u32 reg;
1315 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1316 struct fb_info *info = pci_get_drvdata(par->pdev);
1317 #endif
1318
1319 if (on) {
1320 reg = aty_ld_le32(LVDS_GEN_CNTL);
1321 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1322 reg &= ~LVDS_DISPLAY_DIS;
1323 aty_st_le32(LVDS_GEN_CNTL, reg);
1324 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1325 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1326 #endif
1327 } else {
1328 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1329 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1330 #endif
1331 reg = aty_ld_le32(LVDS_GEN_CNTL);
1332 reg |= LVDS_DISPLAY_DIS;
1333 aty_st_le32(LVDS_GEN_CNTL, reg);
1334 mdelay(100);
1335 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1336 aty_st_le32(LVDS_GEN_CNTL, reg);
1337 }
1338 }
1339
aty128_set_pll(struct aty128_pll * pll,const struct aty128fb_par * par)1340 static void aty128_set_pll(struct aty128_pll *pll,
1341 const struct aty128fb_par *par)
1342 {
1343 u32 div3;
1344
1345 unsigned char post_conv[] = /* register values for post dividers */
1346 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1347
1348 /* select PPLL_DIV_3 */
1349 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1350
1351 /* reset PLL */
1352 aty_st_pll(PPLL_CNTL,
1353 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1354
1355 /* write the reference divider */
1356 aty_pll_wait_readupdate(par);
1357 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1358 aty_pll_writeupdate(par);
1359
1360 div3 = aty_ld_pll(PPLL_DIV_3);
1361 div3 &= ~PPLL_FB3_DIV_MASK;
1362 div3 |= pll->feedback_divider;
1363 div3 &= ~PPLL_POST3_DIV_MASK;
1364 div3 |= post_conv[pll->post_divider] << 16;
1365
1366 /* write feedback and post dividers */
1367 aty_pll_wait_readupdate(par);
1368 aty_st_pll(PPLL_DIV_3, div3);
1369 aty_pll_writeupdate(par);
1370
1371 aty_pll_wait_readupdate(par);
1372 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1373 aty_pll_writeupdate(par);
1374
1375 /* clear the reset, just in case */
1376 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1377 }
1378
1379
aty128_var_to_pll(u32 period_in_ps,struct aty128_pll * pll,const struct aty128fb_par * par)1380 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1381 const struct aty128fb_par *par)
1382 {
1383 const struct aty128_constants c = par->constants;
1384 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1385 u32 output_freq;
1386 u32 vclk; /* in .01 MHz */
1387 int i = 0;
1388 u32 n, d;
1389
1390 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1391
1392 /* adjust pixel clock if necessary */
1393 if (vclk > c.ppll_max)
1394 vclk = c.ppll_max;
1395 if (vclk * 12 < c.ppll_min)
1396 vclk = c.ppll_min/12;
1397
1398 /* now, find an acceptable divider */
1399 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1400 output_freq = post_dividers[i] * vclk;
1401 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1402 pll->post_divider = post_dividers[i];
1403 break;
1404 }
1405 }
1406
1407 if (i == ARRAY_SIZE(post_dividers))
1408 return -EINVAL;
1409
1410 /* calculate feedback divider */
1411 n = c.ref_divider * output_freq;
1412 d = c.ref_clk;
1413
1414 pll->feedback_divider = round_div(n, d);
1415 pll->vclk = vclk;
1416
1417 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1418 "vclk_per: %d\n", pll->post_divider,
1419 pll->feedback_divider, vclk, output_freq,
1420 c.ref_divider, period_in_ps);
1421
1422 return 0;
1423 }
1424
1425
aty128_pll_to_var(const struct aty128_pll * pll,struct fb_var_screeninfo * var)1426 static int aty128_pll_to_var(const struct aty128_pll *pll,
1427 struct fb_var_screeninfo *var)
1428 {
1429 var->pixclock = 100000000 / pll->vclk;
1430
1431 return 0;
1432 }
1433
1434
aty128_set_fifo(const struct aty128_ddafifo * dsp,const struct aty128fb_par * par)1435 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1436 const struct aty128fb_par *par)
1437 {
1438 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1439 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1440 }
1441
1442
aty128_ddafifo(struct aty128_ddafifo * dsp,const struct aty128_pll * pll,u32 depth,const struct aty128fb_par * par)1443 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1444 const struct aty128_pll *pll,
1445 u32 depth,
1446 const struct aty128fb_par *par)
1447 {
1448 const struct aty128_meminfo *m = par->mem;
1449 u32 xclk = par->constants.xclk;
1450 u32 fifo_width = par->constants.fifo_width;
1451 u32 fifo_depth = par->constants.fifo_depth;
1452 s32 x, b, p, ron, roff;
1453 u32 n, d, bpp;
1454
1455 /* round up to multiple of 8 */
1456 bpp = (depth+7) & ~7;
1457
1458 n = xclk * fifo_width;
1459 d = pll->vclk * bpp;
1460 x = round_div(n, d);
1461
1462 ron = 4 * m->MB +
1463 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1464 2 * m->Trp +
1465 m->Twr +
1466 m->CL +
1467 m->Tr2w +
1468 x;
1469
1470 DBG("x %x\n", x);
1471
1472 b = 0;
1473 while (x) {
1474 x >>= 1;
1475 b++;
1476 }
1477 p = b + 1;
1478
1479 ron <<= (11 - p);
1480
1481 n <<= (11 - p);
1482 x = round_div(n, d);
1483 roff = x * (fifo_depth - 4);
1484
1485 if ((ron + m->Rloop) >= roff) {
1486 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1487 return -EINVAL;
1488 }
1489
1490 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1491 p, m->Rloop, x, ron, roff);
1492
1493 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1494 dsp->dda_on_off = ron << 16 | roff;
1495
1496 return 0;
1497 }
1498
1499
1500 /*
1501 * This actually sets the video mode.
1502 */
aty128fb_set_par(struct fb_info * info)1503 static int aty128fb_set_par(struct fb_info *info)
1504 {
1505 struct aty128fb_par *par = info->par;
1506 u32 config;
1507 int err;
1508
1509 if ((err = aty128_decode_var(&info->var, par)) != 0)
1510 return err;
1511
1512 if (par->blitter_may_be_busy)
1513 wait_for_idle(par);
1514
1515 /* clear all registers that may interfere with mode setting */
1516 aty_st_le32(OVR_CLR, 0);
1517 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1518 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1519 aty_st_le32(OV0_SCALE_CNTL, 0);
1520 aty_st_le32(MPP_TB_CONFIG, 0);
1521 aty_st_le32(MPP_GP_CONFIG, 0);
1522 aty_st_le32(SUBPIC_CNTL, 0);
1523 aty_st_le32(VIPH_CONTROL, 0);
1524 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1525 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1526 aty_st_le32(CAP0_TRIG_CNTL, 0);
1527 aty_st_le32(CAP1_TRIG_CNTL, 0);
1528
1529 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1530
1531 aty128_set_crtc(&par->crtc, par);
1532 aty128_set_pll(&par->pll, par);
1533 aty128_set_fifo(&par->fifo_reg, par);
1534
1535 config = aty_ld_le32(CNFG_CNTL) & ~3;
1536
1537 #if defined(__BIG_ENDIAN)
1538 if (par->crtc.bpp == 32)
1539 config |= 2; /* make aperture do 32 bit swapping */
1540 else if (par->crtc.bpp == 16)
1541 config |= 1; /* make aperture do 16 bit swapping */
1542 #endif
1543
1544 aty_st_le32(CNFG_CNTL, config);
1545 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1546
1547 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1548 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1549 : FB_VISUAL_DIRECTCOLOR;
1550
1551 if (par->chip_gen == rage_M3) {
1552 aty128_set_crt_enable(par, par->crt_on);
1553 aty128_set_lcd_enable(par, par->lcd_on);
1554 }
1555 if (par->accel_flags & FB_ACCELF_TEXT)
1556 aty128_init_engine(par);
1557
1558 #ifdef CONFIG_BOOTX_TEXT
1559 btext_update_display(info->fix.smem_start,
1560 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1561 ((par->crtc.v_total>>16) & 0x7ff)+1,
1562 par->crtc.bpp,
1563 par->crtc.vxres*par->crtc.bpp/8);
1564 #endif /* CONFIG_BOOTX_TEXT */
1565
1566 return 0;
1567 }
1568
1569 /*
1570 * encode/decode the User Defined Part of the Display
1571 */
1572
aty128_decode_var(struct fb_var_screeninfo * var,struct aty128fb_par * par)1573 static int aty128_decode_var(struct fb_var_screeninfo *var,
1574 struct aty128fb_par *par)
1575 {
1576 int err;
1577 struct aty128_crtc crtc;
1578 struct aty128_pll pll;
1579 struct aty128_ddafifo fifo_reg;
1580
1581 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1582 return err;
1583
1584 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1585 return err;
1586
1587 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1588 return err;
1589
1590 par->crtc = crtc;
1591 par->pll = pll;
1592 par->fifo_reg = fifo_reg;
1593 par->accel_flags = var->accel_flags;
1594
1595 return 0;
1596 }
1597
1598
aty128_encode_var(struct fb_var_screeninfo * var,const struct aty128fb_par * par)1599 static int aty128_encode_var(struct fb_var_screeninfo *var,
1600 const struct aty128fb_par *par)
1601 {
1602 int err;
1603
1604 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1605 return err;
1606
1607 if ((err = aty128_pll_to_var(&par->pll, var)))
1608 return err;
1609
1610 var->nonstd = 0;
1611 var->activate = 0;
1612
1613 var->height = -1;
1614 var->width = -1;
1615 var->accel_flags = par->accel_flags;
1616
1617 return 0;
1618 }
1619
1620
aty128fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)1621 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1622 struct fb_info *info)
1623 {
1624 struct aty128fb_par par;
1625 int err;
1626
1627 par = *(struct aty128fb_par *)info->par;
1628 if ((err = aty128_decode_var(var, &par)) != 0)
1629 return err;
1630 aty128_encode_var(var, &par);
1631 return 0;
1632 }
1633
1634
1635 /*
1636 * Pan or Wrap the Display
1637 */
aty128fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * fb)1638 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1639 struct fb_info *fb)
1640 {
1641 struct aty128fb_par *par = fb->par;
1642 u32 xoffset, yoffset;
1643 u32 offset;
1644 u32 xres, yres;
1645
1646 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1647 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1648
1649 xoffset = (var->xoffset +7) & ~7;
1650 yoffset = var->yoffset;
1651
1652 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1653 return -EINVAL;
1654
1655 par->crtc.xoffset = xoffset;
1656 par->crtc.yoffset = yoffset;
1657
1658 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1659 & ~7;
1660
1661 if (par->crtc.bpp == 24)
1662 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1663
1664 aty_st_le32(CRTC_OFFSET, offset);
1665
1666 return 0;
1667 }
1668
1669
1670 /*
1671 * Helper function to store a single palette register
1672 */
aty128_st_pal(u_int regno,u_int red,u_int green,u_int blue,struct aty128fb_par * par)1673 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1674 struct aty128fb_par *par)
1675 {
1676 if (par->chip_gen == rage_M3) {
1677 #if 0
1678 /* Note: For now, on M3, we set palette on both heads, which may
1679 * be useless. Can someone with a M3 check this ?
1680 *
1681 * This code would still be useful if using the second CRTC to
1682 * do mirroring
1683 */
1684
1685 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1686 DAC_PALETTE_ACCESS_CNTL);
1687 aty_st_8(PALETTE_INDEX, regno);
1688 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1689 #endif
1690 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1691 ~DAC_PALETTE_ACCESS_CNTL);
1692 }
1693
1694 aty_st_8(PALETTE_INDEX, regno);
1695 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1696 }
1697
aty128fb_sync(struct fb_info * info)1698 static int aty128fb_sync(struct fb_info *info)
1699 {
1700 struct aty128fb_par *par = info->par;
1701
1702 if (par->blitter_may_be_busy)
1703 wait_for_idle(par);
1704 return 0;
1705 }
1706
1707 #ifndef MODULE
aty128fb_setup(char * options)1708 static int aty128fb_setup(char *options)
1709 {
1710 char *this_opt;
1711
1712 if (!options || !*options)
1713 return 0;
1714
1715 while ((this_opt = strsep(&options, ",")) != NULL) {
1716 if (!strncmp(this_opt, "lcd:", 4)) {
1717 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1718 continue;
1719 } else if (!strncmp(this_opt, "crt:", 4)) {
1720 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1721 continue;
1722 } else if (!strncmp(this_opt, "backlight:", 10)) {
1723 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1724 backlight = simple_strtoul(this_opt+10, NULL, 0);
1725 #endif
1726 continue;
1727 }
1728 #ifdef CONFIG_MTRR
1729 if(!strncmp(this_opt, "nomtrr", 6)) {
1730 mtrr = 0;
1731 continue;
1732 }
1733 #endif
1734 #ifdef CONFIG_PPC_PMAC
1735 /* vmode and cmode deprecated */
1736 if (!strncmp(this_opt, "vmode:", 6)) {
1737 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1738 if (vmode > 0 && vmode <= VMODE_MAX)
1739 default_vmode = vmode;
1740 continue;
1741 } else if (!strncmp(this_opt, "cmode:", 6)) {
1742 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1743 switch (cmode) {
1744 case 0:
1745 case 8:
1746 default_cmode = CMODE_8;
1747 break;
1748 case 15:
1749 case 16:
1750 default_cmode = CMODE_16;
1751 break;
1752 case 24:
1753 case 32:
1754 default_cmode = CMODE_32;
1755 break;
1756 }
1757 continue;
1758 }
1759 #endif /* CONFIG_PPC_PMAC */
1760 mode_option = this_opt;
1761 }
1762 return 0;
1763 }
1764 #endif /* MODULE */
1765
1766 /* Backlight */
1767 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1768 #define MAX_LEVEL 0xFF
1769
aty128_bl_get_level_brightness(struct aty128fb_par * par,int level)1770 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1771 int level)
1772 {
1773 struct fb_info *info = pci_get_drvdata(par->pdev);
1774 int atylevel;
1775
1776 /* Get and convert the value */
1777 /* No locking of bl_curve since we read a single value */
1778 atylevel = MAX_LEVEL -
1779 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1780
1781 if (atylevel < 0)
1782 atylevel = 0;
1783 else if (atylevel > MAX_LEVEL)
1784 atylevel = MAX_LEVEL;
1785
1786 return atylevel;
1787 }
1788
1789 /* We turn off the LCD completely instead of just dimming the backlight.
1790 * This provides greater power saving and the display is useless without
1791 * backlight anyway
1792 */
1793 #define BACKLIGHT_LVDS_OFF
1794 /* That one prevents proper CRT output with LCD off */
1795 #undef BACKLIGHT_DAC_OFF
1796
aty128_bl_update_status(struct backlight_device * bd)1797 static int aty128_bl_update_status(struct backlight_device *bd)
1798 {
1799 struct aty128fb_par *par = bl_get_data(bd);
1800 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1801 int level;
1802
1803 if (bd->props.power != FB_BLANK_UNBLANK ||
1804 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1805 !par->lcd_on)
1806 level = 0;
1807 else
1808 level = bd->props.brightness;
1809
1810 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1811 if (level > 0) {
1812 reg |= LVDS_DIGION;
1813 if (!(reg & LVDS_ON)) {
1814 reg &= ~LVDS_BLON;
1815 aty_st_le32(LVDS_GEN_CNTL, reg);
1816 aty_ld_le32(LVDS_GEN_CNTL);
1817 mdelay(10);
1818 reg |= LVDS_BLON;
1819 aty_st_le32(LVDS_GEN_CNTL, reg);
1820 }
1821 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1822 reg |= (aty128_bl_get_level_brightness(par, level) <<
1823 LVDS_BL_MOD_LEVEL_SHIFT);
1824 #ifdef BACKLIGHT_LVDS_OFF
1825 reg |= LVDS_ON | LVDS_EN;
1826 reg &= ~LVDS_DISPLAY_DIS;
1827 #endif
1828 aty_st_le32(LVDS_GEN_CNTL, reg);
1829 #ifdef BACKLIGHT_DAC_OFF
1830 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1831 #endif
1832 } else {
1833 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1834 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1835 LVDS_BL_MOD_LEVEL_SHIFT);
1836 #ifdef BACKLIGHT_LVDS_OFF
1837 reg |= LVDS_DISPLAY_DIS;
1838 aty_st_le32(LVDS_GEN_CNTL, reg);
1839 aty_ld_le32(LVDS_GEN_CNTL);
1840 udelay(10);
1841 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1842 #endif
1843 aty_st_le32(LVDS_GEN_CNTL, reg);
1844 #ifdef BACKLIGHT_DAC_OFF
1845 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1846 #endif
1847 }
1848
1849 return 0;
1850 }
1851
1852 static const struct backlight_ops aty128_bl_data = {
1853 .update_status = aty128_bl_update_status,
1854 };
1855
aty128_bl_set_power(struct fb_info * info,int power)1856 static void aty128_bl_set_power(struct fb_info *info, int power)
1857 {
1858 if (info->bl_dev) {
1859 info->bl_dev->props.power = power;
1860 backlight_update_status(info->bl_dev);
1861 }
1862 }
1863
aty128_bl_init(struct aty128fb_par * par)1864 static void aty128_bl_init(struct aty128fb_par *par)
1865 {
1866 struct backlight_properties props;
1867 struct fb_info *info = pci_get_drvdata(par->pdev);
1868 struct backlight_device *bd;
1869 char name[12];
1870
1871 /* Could be extended to Rage128Pro LVDS output too */
1872 if (par->chip_gen != rage_M3)
1873 return;
1874
1875 #ifdef CONFIG_PMAC_BACKLIGHT
1876 if (!pmac_has_backlight_type("ati"))
1877 return;
1878 #endif
1879
1880 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1881
1882 memset(&props, 0, sizeof(struct backlight_properties));
1883 props.type = BACKLIGHT_RAW;
1884 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1885 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1886 &props);
1887 if (IS_ERR(bd)) {
1888 info->bl_dev = NULL;
1889 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1890 goto error;
1891 }
1892
1893 info->bl_dev = bd;
1894 fb_bl_default_curve(info, 0,
1895 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1896 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1897
1898 bd->props.brightness = bd->props.max_brightness;
1899 bd->props.power = FB_BLANK_UNBLANK;
1900 backlight_update_status(bd);
1901
1902 printk("aty128: Backlight initialized (%s)\n", name);
1903
1904 return;
1905
1906 error:
1907 return;
1908 }
1909
aty128_bl_exit(struct backlight_device * bd)1910 static void aty128_bl_exit(struct backlight_device *bd)
1911 {
1912 backlight_device_unregister(bd);
1913 printk("aty128: Backlight unloaded\n");
1914 }
1915 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1916
1917 /*
1918 * Initialisation
1919 */
1920
1921 #ifdef CONFIG_PPC_PMAC__disabled
aty128_early_resume(void * data)1922 static void aty128_early_resume(void *data)
1923 {
1924 struct aty128fb_par *par = data;
1925
1926 if (!console_trylock())
1927 return;
1928 pci_restore_state(par->pdev);
1929 aty128_do_resume(par->pdev);
1930 console_unlock();
1931 }
1932 #endif /* CONFIG_PPC_PMAC */
1933
aty128_init(struct pci_dev * pdev,const struct pci_device_id * ent)1934 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1935 {
1936 struct fb_info *info = pci_get_drvdata(pdev);
1937 struct aty128fb_par *par = info->par;
1938 struct fb_var_screeninfo var;
1939 char video_card[50];
1940 u8 chip_rev;
1941 u32 dac;
1942
1943 /* Get the chip revision */
1944 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1945
1946 strcpy(video_card, "Rage128 XX ");
1947 video_card[8] = ent->device >> 8;
1948 video_card[9] = ent->device & 0xFF;
1949
1950 /* range check to make sure */
1951 if (ent->driver_data < ARRAY_SIZE(r128_family))
1952 strlcat(video_card, r128_family[ent->driver_data],
1953 sizeof(video_card));
1954
1955 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1956
1957 if (par->vram_size % (1024 * 1024) == 0)
1958 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1959 else
1960 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1961
1962 par->chip_gen = ent->driver_data;
1963
1964 /* fill in info */
1965 info->fbops = &aty128fb_ops;
1966 info->flags = FBINFO_FLAG_DEFAULT;
1967
1968 par->lcd_on = default_lcd_on;
1969 par->crt_on = default_crt_on;
1970
1971 var = default_var;
1972 #ifdef CONFIG_PPC_PMAC
1973 if (machine_is(powermac)) {
1974 /* Indicate sleep capability */
1975 if (par->chip_gen == rage_M3) {
1976 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1977 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1978 * among others we now rely on the PCI core restoring the config space
1979 * for us, which isn't the case with that hack, and that code path causes
1980 * various things to be called with interrupts off while they shouldn't.
1981 * I'm leaving the code in as it can be useful for debugging purposes
1982 */
1983 pmac_set_early_video_resume(aty128_early_resume, par);
1984 #endif
1985 }
1986
1987 /* Find default mode */
1988 if (mode_option) {
1989 if (!mac_find_mode(&var, info, mode_option, 8))
1990 var = default_var;
1991 } else {
1992 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1993 default_vmode = VMODE_1024_768_60;
1994
1995 /* iMacs need that resolution
1996 * PowerMac2,1 first r128 iMacs
1997 * PowerMac2,2 summer 2000 iMacs
1998 * PowerMac4,1 january 2001 iMacs "flower power"
1999 */
2000 if (of_machine_is_compatible("PowerMac2,1") ||
2001 of_machine_is_compatible("PowerMac2,2") ||
2002 of_machine_is_compatible("PowerMac4,1"))
2003 default_vmode = VMODE_1024_768_75;
2004
2005 /* iBook SE */
2006 if (of_machine_is_compatible("PowerBook2,2"))
2007 default_vmode = VMODE_800_600_60;
2008
2009 /* PowerBook Firewire (Pismo), iBook Dual USB */
2010 if (of_machine_is_compatible("PowerBook3,1") ||
2011 of_machine_is_compatible("PowerBook4,1"))
2012 default_vmode = VMODE_1024_768_60;
2013
2014 /* PowerBook Titanium */
2015 if (of_machine_is_compatible("PowerBook3,2"))
2016 default_vmode = VMODE_1152_768_60;
2017
2018 if (default_cmode > 16)
2019 default_cmode = CMODE_32;
2020 else if (default_cmode > 8)
2021 default_cmode = CMODE_16;
2022 else
2023 default_cmode = CMODE_8;
2024
2025 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2026 var = default_var;
2027 }
2028 } else
2029 #endif /* CONFIG_PPC_PMAC */
2030 {
2031 if (mode_option)
2032 if (fb_find_mode(&var, info, mode_option, NULL,
2033 0, &defaultmode, 8) == 0)
2034 var = default_var;
2035 }
2036
2037 var.accel_flags &= ~FB_ACCELF_TEXT;
2038 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
2039
2040 if (aty128fb_check_var(&var, info)) {
2041 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2042 return 0;
2043 }
2044
2045 /* setup the DAC the way we like it */
2046 dac = aty_ld_le32(DAC_CNTL);
2047 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2048 dac |= DAC_MASK;
2049 if (par->chip_gen == rage_M3)
2050 dac |= DAC_PALETTE2_SNOOP_EN;
2051 aty_st_le32(DAC_CNTL, dac);
2052
2053 /* turn off bus mastering, just in case */
2054 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2055
2056 info->var = var;
2057 fb_alloc_cmap(&info->cmap, 256, 0);
2058
2059 var.activate = FB_ACTIVATE_NOW;
2060
2061 aty128_init_engine(par);
2062
2063 par->pdev = pdev;
2064 par->asleep = 0;
2065 par->lock_blank = 0;
2066
2067 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2068 if (backlight)
2069 aty128_bl_init(par);
2070 #endif
2071
2072 if (register_framebuffer(info) < 0)
2073 return 0;
2074
2075 fb_info(info, "%s frame buffer device on %s\n",
2076 info->fix.id, video_card);
2077
2078 return 1; /* success! */
2079 }
2080
2081 #ifdef CONFIG_PCI
2082 /* register a card ++ajoshi */
aty128_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2083 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2084 {
2085 unsigned long fb_addr, reg_addr;
2086 struct aty128fb_par *par;
2087 struct fb_info *info;
2088 int err;
2089 #ifndef __sparc__
2090 void __iomem *bios = NULL;
2091 #endif
2092
2093 /* Enable device in PCI config */
2094 if ((err = pci_enable_device(pdev))) {
2095 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2096 err);
2097 return -ENODEV;
2098 }
2099
2100 fb_addr = pci_resource_start(pdev, 0);
2101 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2102 "aty128fb FB")) {
2103 printk(KERN_ERR "aty128fb: cannot reserve frame "
2104 "buffer memory\n");
2105 return -ENODEV;
2106 }
2107
2108 reg_addr = pci_resource_start(pdev, 2);
2109 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2110 "aty128fb MMIO")) {
2111 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2112 goto err_free_fb;
2113 }
2114
2115 /* We have the resources. Now virtualize them */
2116 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2117 if (info == NULL) {
2118 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2119 goto err_free_mmio;
2120 }
2121 par = info->par;
2122
2123 info->pseudo_palette = par->pseudo_palette;
2124
2125 /* Virtualize mmio region */
2126 info->fix.mmio_start = reg_addr;
2127 par->regbase = pci_ioremap_bar(pdev, 2);
2128 if (!par->regbase)
2129 goto err_free_info;
2130
2131 /* Grab memory size from the card */
2132 // How does this relate to the resource length from the PCI hardware?
2133 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2134
2135 /* Virtualize the framebuffer */
2136 info->screen_base = ioremap(fb_addr, par->vram_size);
2137 if (!info->screen_base)
2138 goto err_unmap_out;
2139
2140 /* Set up info->fix */
2141 info->fix = aty128fb_fix;
2142 info->fix.smem_start = fb_addr;
2143 info->fix.smem_len = par->vram_size;
2144 info->fix.mmio_start = reg_addr;
2145
2146 /* If we can't test scratch registers, something is seriously wrong */
2147 if (!register_test(par)) {
2148 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2149 goto err_out;
2150 }
2151
2152 #ifndef __sparc__
2153 bios = aty128_map_ROM(par, pdev);
2154 #ifdef CONFIG_X86
2155 if (bios == NULL)
2156 bios = aty128_find_mem_vbios(par);
2157 #endif
2158 if (bios == NULL)
2159 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2160 else {
2161 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2162 aty128_get_pllinfo(par, bios);
2163 pci_unmap_rom(pdev, bios);
2164 }
2165 #endif /* __sparc__ */
2166
2167 aty128_timings(par);
2168 pci_set_drvdata(pdev, info);
2169
2170 if (!aty128_init(pdev, ent))
2171 goto err_out;
2172
2173 #ifdef CONFIG_MTRR
2174 if (mtrr) {
2175 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2176 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2177 par->mtrr.vram_valid = 1;
2178 /* let there be speed */
2179 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2180 }
2181 #endif /* CONFIG_MTRR */
2182 return 0;
2183
2184 err_out:
2185 iounmap(info->screen_base);
2186 err_unmap_out:
2187 iounmap(par->regbase);
2188 err_free_info:
2189 framebuffer_release(info);
2190 err_free_mmio:
2191 release_mem_region(pci_resource_start(pdev, 2),
2192 pci_resource_len(pdev, 2));
2193 err_free_fb:
2194 release_mem_region(pci_resource_start(pdev, 0),
2195 pci_resource_len(pdev, 0));
2196 return -ENODEV;
2197 }
2198
aty128_remove(struct pci_dev * pdev)2199 static void aty128_remove(struct pci_dev *pdev)
2200 {
2201 struct fb_info *info = pci_get_drvdata(pdev);
2202 struct aty128fb_par *par;
2203
2204 if (!info)
2205 return;
2206
2207 par = info->par;
2208
2209 unregister_framebuffer(info);
2210
2211 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2212 aty128_bl_exit(info->bl_dev);
2213 #endif
2214
2215 #ifdef CONFIG_MTRR
2216 if (par->mtrr.vram_valid)
2217 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2218 par->vram_size);
2219 #endif /* CONFIG_MTRR */
2220 iounmap(par->regbase);
2221 iounmap(info->screen_base);
2222
2223 release_mem_region(pci_resource_start(pdev, 0),
2224 pci_resource_len(pdev, 0));
2225 release_mem_region(pci_resource_start(pdev, 2),
2226 pci_resource_len(pdev, 2));
2227 framebuffer_release(info);
2228 }
2229 #endif /* CONFIG_PCI */
2230
2231
2232
2233 /*
2234 * Blank the display.
2235 */
aty128fb_blank(int blank,struct fb_info * fb)2236 static int aty128fb_blank(int blank, struct fb_info *fb)
2237 {
2238 struct aty128fb_par *par = fb->par;
2239 u8 state;
2240
2241 if (par->lock_blank || par->asleep)
2242 return 0;
2243
2244 switch (blank) {
2245 case FB_BLANK_NORMAL:
2246 state = 4;
2247 break;
2248 case FB_BLANK_VSYNC_SUSPEND:
2249 state = 6;
2250 break;
2251 case FB_BLANK_HSYNC_SUSPEND:
2252 state = 5;
2253 break;
2254 case FB_BLANK_POWERDOWN:
2255 state = 7;
2256 break;
2257 case FB_BLANK_UNBLANK:
2258 default:
2259 state = 0;
2260 break;
2261 }
2262 aty_st_8(CRTC_EXT_CNTL+1, state);
2263
2264 if (par->chip_gen == rage_M3) {
2265 aty128_set_crt_enable(par, par->crt_on && !blank);
2266 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2267 }
2268
2269 return 0;
2270 }
2271
2272 /*
2273 * Set a single color register. The values supplied are already
2274 * rounded down to the hardware's capabilities (according to the
2275 * entries in the var structure). Return != 0 for invalid regno.
2276 */
aty128fb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * info)2277 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2278 u_int transp, struct fb_info *info)
2279 {
2280 struct aty128fb_par *par = info->par;
2281
2282 if (regno > 255
2283 || (par->crtc.depth == 16 && regno > 63)
2284 || (par->crtc.depth == 15 && regno > 31))
2285 return 1;
2286
2287 red >>= 8;
2288 green >>= 8;
2289 blue >>= 8;
2290
2291 if (regno < 16) {
2292 int i;
2293 u32 *pal = info->pseudo_palette;
2294
2295 switch (par->crtc.depth) {
2296 case 15:
2297 pal[regno] = (regno << 10) | (regno << 5) | regno;
2298 break;
2299 case 16:
2300 pal[regno] = (regno << 11) | (regno << 6) | regno;
2301 break;
2302 case 24:
2303 pal[regno] = (regno << 16) | (regno << 8) | regno;
2304 break;
2305 case 32:
2306 i = (regno << 8) | regno;
2307 pal[regno] = (i << 16) | i;
2308 break;
2309 }
2310 }
2311
2312 if (par->crtc.depth == 16 && regno > 0) {
2313 /*
2314 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2315 * have 32 slots for R and B values but 64 slots for G values.
2316 * Thus the R and B values go in one slot but the G value
2317 * goes in a different slot, and we have to avoid disturbing
2318 * the other fields in the slots we touch.
2319 */
2320 par->green[regno] = green;
2321 if (regno < 32) {
2322 par->red[regno] = red;
2323 par->blue[regno] = blue;
2324 aty128_st_pal(regno * 8, red, par->green[regno*2],
2325 blue, par);
2326 }
2327 red = par->red[regno/2];
2328 blue = par->blue[regno/2];
2329 regno <<= 2;
2330 } else if (par->crtc.bpp == 16)
2331 regno <<= 3;
2332 aty128_st_pal(regno, red, green, blue, par);
2333
2334 return 0;
2335 }
2336
2337 #define ATY_MIRROR_LCD_ON 0x00000001
2338 #define ATY_MIRROR_CRT_ON 0x00000002
2339
2340 /* out param: u32* backlight value: 0 to 15 */
2341 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2342 /* in param: u32* backlight value: 0 to 15 */
2343 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2344
aty128fb_ioctl(struct fb_info * info,u_int cmd,u_long arg)2345 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2346 {
2347 struct aty128fb_par *par = info->par;
2348 u32 value;
2349 int rc;
2350
2351 switch (cmd) {
2352 case FBIO_ATY128_SET_MIRROR:
2353 if (par->chip_gen != rage_M3)
2354 return -EINVAL;
2355 rc = get_user(value, (__u32 __user *)arg);
2356 if (rc)
2357 return rc;
2358 par->lcd_on = (value & 0x01) != 0;
2359 par->crt_on = (value & 0x02) != 0;
2360 if (!par->crt_on && !par->lcd_on)
2361 par->lcd_on = 1;
2362 aty128_set_crt_enable(par, par->crt_on);
2363 aty128_set_lcd_enable(par, par->lcd_on);
2364 return 0;
2365 case FBIO_ATY128_GET_MIRROR:
2366 if (par->chip_gen != rage_M3)
2367 return -EINVAL;
2368 value = (par->crt_on << 1) | par->lcd_on;
2369 return put_user(value, (__u32 __user *)arg);
2370 }
2371 return -EINVAL;
2372 }
2373
2374 #if 0
2375 /*
2376 * Accelerated functions
2377 */
2378
2379 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2380 u_int width, u_int height,
2381 struct fb_info_aty128 *par)
2382 {
2383 u32 save_dp_datatype, save_dp_cntl, dstval;
2384
2385 if (!width || !height)
2386 return;
2387
2388 dstval = depth_to_dst(par->current_par.crtc.depth);
2389 if (dstval == DST_24BPP) {
2390 srcx *= 3;
2391 dstx *= 3;
2392 width *= 3;
2393 } else if (dstval == -EINVAL) {
2394 printk("aty128fb: invalid depth or RGBA\n");
2395 return;
2396 }
2397
2398 wait_for_fifo(2, par);
2399 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2400 save_dp_cntl = aty_ld_le32(DP_CNTL);
2401
2402 wait_for_fifo(6, par);
2403 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2404 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2405 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2406 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2407
2408 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2409 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2410
2411 par->blitter_may_be_busy = 1;
2412
2413 wait_for_fifo(2, par);
2414 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2415 aty_st_le32(DP_CNTL, save_dp_cntl);
2416 }
2417
2418
2419 /*
2420 * Text mode accelerated functions
2421 */
2422
2423 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy,
2424 int dx, int height, int width)
2425 {
2426 sx *= fontwidth(p);
2427 sy *= fontheight(p);
2428 dx *= fontwidth(p);
2429 dy *= fontheight(p);
2430 width *= fontwidth(p);
2431 height *= fontheight(p);
2432
2433 aty128_rectcopy(sx, sy, dx, dy, width, height,
2434 (struct fb_info_aty128 *)p->fb_info);
2435 }
2436 #endif /* 0 */
2437
aty128_set_suspend(struct aty128fb_par * par,int suspend)2438 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2439 {
2440 u32 pmgt;
2441 struct pci_dev *pdev = par->pdev;
2442
2443 if (!par->pdev->pm_cap)
2444 return;
2445
2446 /* Set the chip into the appropriate suspend mode (we use D2,
2447 * D3 would require a complete re-initialisation of the chip,
2448 * including PCI config registers, clocks, AGP configuration, ...)
2449 *
2450 * For resume, the core will have already brought us back to D0
2451 */
2452 if (suspend) {
2453 /* Make sure CRTC2 is reset. Remove that the day we decide to
2454 * actually use CRTC2 and replace it with real code for disabling
2455 * the CRTC2 output during sleep
2456 */
2457 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2458 ~(CRTC2_EN));
2459
2460 /* Set the power management mode to be PCI based */
2461 /* Use this magic value for now */
2462 pmgt = 0x0c005407;
2463 aty_st_pll(POWER_MANAGEMENT, pmgt);
2464 (void)aty_ld_pll(POWER_MANAGEMENT);
2465 aty_st_le32(BUS_CNTL1, 0x00000010);
2466 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2467 mdelay(100);
2468
2469 /* Switch PCI power management to D2 */
2470 pci_set_power_state(pdev, PCI_D2);
2471 }
2472 }
2473
aty128_pci_suspend(struct pci_dev * pdev,pm_message_t state)2474 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2475 {
2476 struct fb_info *info = pci_get_drvdata(pdev);
2477 struct aty128fb_par *par = info->par;
2478
2479 /* Because we may change PCI D state ourselves, we need to
2480 * first save the config space content so the core can
2481 * restore it properly on resume.
2482 */
2483 pci_save_state(pdev);
2484
2485 /* We don't do anything but D2, for now we return 0, but
2486 * we may want to change that. How do we know if the BIOS
2487 * can properly take care of D3 ? Also, with swsusp, we
2488 * know we'll be rebooted, ...
2489 */
2490 #ifndef CONFIG_PPC_PMAC
2491 /* HACK ALERT ! Once I find a proper way to say to each driver
2492 * individually what will happen with it's PCI slot, I'll change
2493 * that. On laptops, the AGP slot is just unclocked, so D2 is
2494 * expected, while on desktops, the card is powered off
2495 */
2496 return 0;
2497 #endif /* CONFIG_PPC_PMAC */
2498
2499 if (state.event == pdev->dev.power.power_state.event)
2500 return 0;
2501
2502 printk(KERN_DEBUG "aty128fb: suspending...\n");
2503
2504 console_lock();
2505
2506 fb_set_suspend(info, 1);
2507
2508 /* Make sure engine is reset */
2509 wait_for_idle(par);
2510 aty128_reset_engine(par);
2511 wait_for_idle(par);
2512
2513 /* Blank display and LCD */
2514 aty128fb_blank(FB_BLANK_POWERDOWN, info);
2515
2516 /* Sleep */
2517 par->asleep = 1;
2518 par->lock_blank = 1;
2519
2520 #ifdef CONFIG_PPC_PMAC
2521 /* On powermac, we have hooks to properly suspend/resume AGP now,
2522 * use them here. We'll ultimately need some generic support here,
2523 * but the generic code isn't quite ready for that yet
2524 */
2525 pmac_suspend_agp_for_card(pdev);
2526 #endif /* CONFIG_PPC_PMAC */
2527
2528 /* We need a way to make sure the fbdev layer will _not_ touch the
2529 * framebuffer before we put the chip to suspend state. On 2.4, I
2530 * used dummy fb ops, 2.5 need proper support for this at the
2531 * fbdev level
2532 */
2533 if (state.event != PM_EVENT_ON)
2534 aty128_set_suspend(par, 1);
2535
2536 console_unlock();
2537
2538 pdev->dev.power.power_state = state;
2539
2540 return 0;
2541 }
2542
aty128_do_resume(struct pci_dev * pdev)2543 static int aty128_do_resume(struct pci_dev *pdev)
2544 {
2545 struct fb_info *info = pci_get_drvdata(pdev);
2546 struct aty128fb_par *par = info->par;
2547
2548 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2549 return 0;
2550
2551 /* PCI state will have been restored by the core, so
2552 * we should be in D0 now with our config space fully
2553 * restored
2554 */
2555
2556 /* Wakeup chip */
2557 aty128_set_suspend(par, 0);
2558 par->asleep = 0;
2559
2560 /* Restore display & engine */
2561 aty128_reset_engine(par);
2562 wait_for_idle(par);
2563 aty128fb_set_par(info);
2564 fb_pan_display(info, &info->var);
2565 fb_set_cmap(&info->cmap, info);
2566
2567 /* Refresh */
2568 fb_set_suspend(info, 0);
2569
2570 /* Unblank */
2571 par->lock_blank = 0;
2572 aty128fb_blank(0, info);
2573
2574 #ifdef CONFIG_PPC_PMAC
2575 /* On powermac, we have hooks to properly suspend/resume AGP now,
2576 * use them here. We'll ultimately need some generic support here,
2577 * but the generic code isn't quite ready for that yet
2578 */
2579 pmac_resume_agp_for_card(pdev);
2580 #endif /* CONFIG_PPC_PMAC */
2581
2582 pdev->dev.power.power_state = PMSG_ON;
2583
2584 printk(KERN_DEBUG "aty128fb: resumed !\n");
2585
2586 return 0;
2587 }
2588
aty128_pci_resume(struct pci_dev * pdev)2589 static int aty128_pci_resume(struct pci_dev *pdev)
2590 {
2591 int rc;
2592
2593 console_lock();
2594 rc = aty128_do_resume(pdev);
2595 console_unlock();
2596
2597 return rc;
2598 }
2599
2600
aty128fb_init(void)2601 static int aty128fb_init(void)
2602 {
2603 #ifndef MODULE
2604 char *option = NULL;
2605
2606 if (fb_get_options("aty128fb", &option))
2607 return -ENODEV;
2608 aty128fb_setup(option);
2609 #endif
2610
2611 return pci_register_driver(&aty128fb_driver);
2612 }
2613
aty128fb_exit(void)2614 static void __exit aty128fb_exit(void)
2615 {
2616 pci_unregister_driver(&aty128fb_driver);
2617 }
2618
2619 module_init(aty128fb_init);
2620
2621 module_exit(aty128fb_exit);
2622
2623 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2624 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2625 MODULE_LICENSE("GPL");
2626 module_param(mode_option, charp, 0);
2627 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2628 #ifdef CONFIG_MTRR
2629 module_param_named(nomtrr, mtrr, invbool, 0);
2630 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2631 #endif
2632
2633