1 /**
2 * APM X-Gene PCIe Driver
3 *
4 * Copyright (c) 2014 Applied Micro Circuits Corporation.
5 *
6 * Author: Tanmay Inamdar <tinamdar@apm.com>.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/io.h>
22 #include <linux/jiffies.h>
23 #include <linux/memblock.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32
33 #define PCIECORE_CTLANDSTATUS 0x50
34 #define PIM1_1L 0x80
35 #define IBAR2 0x98
36 #define IR2MSK 0x9c
37 #define PIM2_1L 0xa0
38 #define IBAR3L 0xb4
39 #define IR3MSKL 0xbc
40 #define PIM3_1L 0xc4
41 #define OMR1BARL 0x100
42 #define OMR2BARL 0x118
43 #define OMR3BARL 0x130
44 #define CFGBARL 0x154
45 #define CFGBARH 0x158
46 #define CFGCTL 0x15c
47 #define RTDID 0x160
48 #define BRIDGE_CFG_0 0x2000
49 #define BRIDGE_CFG_4 0x2010
50 #define BRIDGE_STATUS_0 0x2600
51
52 #define LINK_UP_MASK 0x00000100
53 #define AXI_EP_CFG_ACCESS 0x10000
54 #define EN_COHERENCY 0xF0000000
55 #define EN_REG 0x00000001
56 #define OB_LO_IO 0x00000002
57 #define XGENE_PCIE_VENDORID 0x10E8
58 #define XGENE_PCIE_DEVICEID 0xE004
59 #define SZ_1T (SZ_1G*1024ULL)
60 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
61
62 #define ROOT_CAP_AND_CTRL 0x5C
63
64 /* PCIe IP version */
65 #define XGENE_PCIE_IP_VER_UNKN 0
66 #define XGENE_PCIE_IP_VER_1 1
67
68 struct xgene_pcie_port {
69 struct device_node *node;
70 struct device *dev;
71 struct clk *clk;
72 void __iomem *csr_base;
73 void __iomem *cfg_base;
74 unsigned long cfg_addr;
75 bool link_up;
76 u32 version;
77 };
78
pcie_bar_low_val(u32 addr,u32 flags)79 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
80 {
81 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
82 }
83
84 /*
85 * When the address bit [17:16] is 2'b01, the Configuration access will be
86 * treated as Type 1 and it will be forwarded to external PCIe device.
87 */
xgene_pcie_get_cfg_base(struct pci_bus * bus)88 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
89 {
90 struct xgene_pcie_port *port = bus->sysdata;
91
92 if (bus->number >= (bus->primary + 1))
93 return port->cfg_base + AXI_EP_CFG_ACCESS;
94
95 return port->cfg_base;
96 }
97
98 /*
99 * For Configuration request, RTDID register is used as Bus Number,
100 * Device Number and Function number of the header fields.
101 */
xgene_pcie_set_rtdid_reg(struct pci_bus * bus,uint devfn)102 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
103 {
104 struct xgene_pcie_port *port = bus->sysdata;
105 unsigned int b, d, f;
106 u32 rtdid_val = 0;
107
108 b = bus->number;
109 d = PCI_SLOT(devfn);
110 f = PCI_FUNC(devfn);
111
112 if (!pci_is_root_bus(bus))
113 rtdid_val = (b << 8) | (d << 3) | f;
114
115 writel(rtdid_val, port->csr_base + RTDID);
116 /* read the register back to ensure flush */
117 readl(port->csr_base + RTDID);
118 }
119
120 /*
121 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
122 * the translation from PCI bus to native BUS. Entire DDR region
123 * is mapped into PCIe space using these registers, so it can be
124 * reached by DMA from EP devices. The BAR0/1 of bridge should be
125 * hidden during enumeration to avoid the sizing and resource allocation
126 * by PCIe core.
127 */
xgene_pcie_hide_rc_bars(struct pci_bus * bus,int offset)128 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
129 {
130 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
131 (offset == PCI_BASE_ADDRESS_1)))
132 return true;
133
134 return false;
135 }
136
xgene_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int offset)137 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
138 int offset)
139 {
140 if ((pci_is_root_bus(bus) && devfn != 0) ||
141 xgene_pcie_hide_rc_bars(bus, offset))
142 return NULL;
143
144 xgene_pcie_set_rtdid_reg(bus, devfn);
145 return xgene_pcie_get_cfg_base(bus) + offset;
146 }
147
xgene_pcie_config_read32(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)148 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
149 int where, int size, u32 *val)
150 {
151 struct xgene_pcie_port *port = bus->sysdata;
152
153 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
154 PCIBIOS_SUCCESSFUL)
155 return PCIBIOS_DEVICE_NOT_FOUND;
156
157 /*
158 * The v1 controller has a bug in its Configuration Request
159 * Retry Status (CRS) logic: when CRS is enabled and we read the
160 * Vendor and Device ID of a non-existent device, the controller
161 * fabricates return data of 0xFFFF0001 ("device exists but is not
162 * ready") instead of 0xFFFFFFFF ("device does not exist"). This
163 * causes the PCI core to retry the read until it times out.
164 * Avoid this by not claiming to support CRS.
165 */
166 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
167 ((where & ~0x3) == ROOT_CAP_AND_CTRL))
168 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
169
170 if (size <= 2)
171 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
172
173 return PCIBIOS_SUCCESSFUL;
174 }
175
176 static struct pci_ops xgene_pcie_ops = {
177 .map_bus = xgene_pcie_map_bus,
178 .read = xgene_pcie_config_read32,
179 .write = pci_generic_config_write32,
180 };
181
xgene_pcie_set_ib_mask(void __iomem * csr_base,u32 addr,u32 flags,u64 size)182 static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
183 u32 flags, u64 size)
184 {
185 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
186 u32 val32 = 0;
187 u32 val;
188
189 val32 = readl(csr_base + addr);
190 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
191 writel(val, csr_base + addr);
192
193 val32 = readl(csr_base + addr + 0x04);
194 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
195 writel(val, csr_base + addr + 0x04);
196
197 val32 = readl(csr_base + addr + 0x04);
198 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
199 writel(val, csr_base + addr + 0x04);
200
201 val32 = readl(csr_base + addr + 0x08);
202 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
203 writel(val, csr_base + addr + 0x08);
204
205 return mask;
206 }
207
xgene_pcie_linkup(struct xgene_pcie_port * port,u32 * lanes,u32 * speed)208 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
209 u32 *lanes, u32 *speed)
210 {
211 void __iomem *csr_base = port->csr_base;
212 u32 val32;
213
214 port->link_up = false;
215 val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
216 if (val32 & LINK_UP_MASK) {
217 port->link_up = true;
218 *speed = PIPE_PHY_RATE_RD(val32);
219 val32 = readl(csr_base + BRIDGE_STATUS_0);
220 *lanes = val32 >> 26;
221 }
222 }
223
xgene_pcie_init_port(struct xgene_pcie_port * port)224 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
225 {
226 int rc;
227
228 port->clk = clk_get(port->dev, NULL);
229 if (IS_ERR(port->clk)) {
230 dev_err(port->dev, "clock not available\n");
231 return -ENODEV;
232 }
233
234 rc = clk_prepare_enable(port->clk);
235 if (rc) {
236 dev_err(port->dev, "clock enable failed\n");
237 return rc;
238 }
239
240 return 0;
241 }
242
xgene_pcie_map_reg(struct xgene_pcie_port * port,struct platform_device * pdev)243 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
244 struct platform_device *pdev)
245 {
246 struct resource *res;
247
248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
249 port->csr_base = devm_ioremap_resource(port->dev, res);
250 if (IS_ERR(port->csr_base))
251 return PTR_ERR(port->csr_base);
252
253 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
254 port->cfg_base = devm_ioremap_resource(port->dev, res);
255 if (IS_ERR(port->cfg_base))
256 return PTR_ERR(port->cfg_base);
257 port->cfg_addr = res->start;
258
259 return 0;
260 }
261
xgene_pcie_setup_ob_reg(struct xgene_pcie_port * port,struct resource * res,u32 offset,u64 cpu_addr,u64 pci_addr)262 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
263 struct resource *res, u32 offset,
264 u64 cpu_addr, u64 pci_addr)
265 {
266 void __iomem *base = port->csr_base + offset;
267 resource_size_t size = resource_size(res);
268 u64 restype = resource_type(res);
269 u64 mask = 0;
270 u32 min_size;
271 u32 flag = EN_REG;
272
273 if (restype == IORESOURCE_MEM) {
274 min_size = SZ_128M;
275 } else {
276 min_size = 128;
277 flag |= OB_LO_IO;
278 }
279
280 if (size >= min_size)
281 mask = ~(size - 1) | flag;
282 else
283 dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
284 (u64)size, min_size);
285
286 writel(lower_32_bits(cpu_addr), base);
287 writel(upper_32_bits(cpu_addr), base + 0x04);
288 writel(lower_32_bits(mask), base + 0x08);
289 writel(upper_32_bits(mask), base + 0x0c);
290 writel(lower_32_bits(pci_addr), base + 0x10);
291 writel(upper_32_bits(pci_addr), base + 0x14);
292 }
293
xgene_pcie_setup_cfg_reg(void __iomem * csr_base,u64 addr)294 static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
295 {
296 writel(lower_32_bits(addr), csr_base + CFGBARL);
297 writel(upper_32_bits(addr), csr_base + CFGBARH);
298 writel(EN_REG, csr_base + CFGCTL);
299 }
300
xgene_pcie_map_ranges(struct xgene_pcie_port * port,struct list_head * res,resource_size_t io_base)301 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
302 struct list_head *res,
303 resource_size_t io_base)
304 {
305 struct resource_entry *window;
306 struct device *dev = port->dev;
307 int ret;
308
309 resource_list_for_each_entry(window, res) {
310 struct resource *res = window->res;
311 u64 restype = resource_type(res);
312
313 dev_dbg(port->dev, "%pR\n", res);
314
315 switch (restype) {
316 case IORESOURCE_IO:
317 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
318 res->start - window->offset);
319 ret = pci_remap_iospace(res, io_base);
320 if (ret < 0)
321 return ret;
322 break;
323 case IORESOURCE_MEM:
324 if (res->flags & IORESOURCE_PREFETCH)
325 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
326 res->start,
327 res->start -
328 window->offset);
329 else
330 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
331 res->start,
332 res->start -
333 window->offset);
334 break;
335 case IORESOURCE_BUS:
336 break;
337 default:
338 dev_err(dev, "invalid resource %pR\n", res);
339 return -EINVAL;
340 }
341 }
342 xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);
343
344 return 0;
345 }
346
xgene_pcie_setup_pims(void * addr,u64 pim,u64 size)347 static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
348 {
349 writel(lower_32_bits(pim), addr);
350 writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04);
351 writel(lower_32_bits(size), addr + 0x10);
352 writel(upper_32_bits(size), addr + 0x14);
353 }
354
355 /*
356 * X-Gene PCIe support maximum 3 inbound memory regions
357 * This function helps to select a region based on size of region
358 */
xgene_pcie_select_ib_reg(u8 * ib_reg_mask,u64 size)359 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
360 {
361 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
362 *ib_reg_mask |= (1 << 1);
363 return 1;
364 }
365
366 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
367 *ib_reg_mask |= (1 << 0);
368 return 0;
369 }
370
371 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
372 *ib_reg_mask |= (1 << 2);
373 return 2;
374 }
375
376 return -EINVAL;
377 }
378
xgene_pcie_setup_ib_reg(struct xgene_pcie_port * port,struct of_pci_range * range,u8 * ib_reg_mask)379 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
380 struct of_pci_range *range, u8 *ib_reg_mask)
381 {
382 void __iomem *csr_base = port->csr_base;
383 void __iomem *cfg_base = port->cfg_base;
384 void *bar_addr;
385 void *pim_addr;
386 u64 cpu_addr = range->cpu_addr;
387 u64 pci_addr = range->pci_addr;
388 u64 size = range->size;
389 u64 mask = ~(size - 1) | EN_REG;
390 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
391 u32 bar_low;
392 int region;
393
394 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
395 if (region < 0) {
396 dev_warn(port->dev, "invalid pcie dma-range config\n");
397 return;
398 }
399
400 if (range->flags & IORESOURCE_PREFETCH)
401 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
402
403 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
404 switch (region) {
405 case 0:
406 xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
407 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
408 writel(bar_low, bar_addr);
409 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
410 pim_addr = csr_base + PIM1_1L;
411 break;
412 case 1:
413 bar_addr = csr_base + IBAR2;
414 writel(bar_low, bar_addr);
415 writel(lower_32_bits(mask), csr_base + IR2MSK);
416 pim_addr = csr_base + PIM2_1L;
417 break;
418 case 2:
419 bar_addr = csr_base + IBAR3L;
420 writel(bar_low, bar_addr);
421 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
422 writel(lower_32_bits(mask), csr_base + IR3MSKL);
423 writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
424 pim_addr = csr_base + PIM3_1L;
425 break;
426 }
427
428 xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
429 }
430
pci_dma_range_parser_init(struct of_pci_range_parser * parser,struct device_node * node)431 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
432 struct device_node *node)
433 {
434 const int na = 3, ns = 2;
435 int rlen;
436
437 parser->node = node;
438 parser->pna = of_n_addr_cells(node);
439 parser->np = parser->pna + na + ns;
440
441 parser->range = of_get_property(node, "dma-ranges", &rlen);
442 if (!parser->range)
443 return -ENOENT;
444 parser->end = parser->range + rlen / sizeof(__be32);
445
446 return 0;
447 }
448
xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port * port)449 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
450 {
451 struct device_node *np = port->node;
452 struct of_pci_range range;
453 struct of_pci_range_parser parser;
454 struct device *dev = port->dev;
455 u8 ib_reg_mask = 0;
456
457 if (pci_dma_range_parser_init(&parser, np)) {
458 dev_err(dev, "missing dma-ranges property\n");
459 return -EINVAL;
460 }
461
462 /* Get the dma-ranges from DT */
463 for_each_of_pci_range(&parser, &range) {
464 u64 end = range.cpu_addr + range.size - 1;
465
466 dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
467 range.flags, range.cpu_addr, end, range.pci_addr);
468 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
469 }
470 return 0;
471 }
472
473 /* clear BAR configuration which was done by firmware */
xgene_pcie_clear_config(struct xgene_pcie_port * port)474 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
475 {
476 int i;
477
478 for (i = PIM1_1L; i <= CFGCTL; i += 4)
479 writel(0x0, port->csr_base + i);
480 }
481
xgene_pcie_setup(struct xgene_pcie_port * port,struct list_head * res,resource_size_t io_base)482 static int xgene_pcie_setup(struct xgene_pcie_port *port,
483 struct list_head *res,
484 resource_size_t io_base)
485 {
486 u32 val, lanes = 0, speed = 0;
487 int ret;
488
489 xgene_pcie_clear_config(port);
490
491 /* setup the vendor and device IDs correctly */
492 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
493 writel(val, port->csr_base + BRIDGE_CFG_0);
494
495 ret = xgene_pcie_map_ranges(port, res, io_base);
496 if (ret)
497 return ret;
498
499 ret = xgene_pcie_parse_map_dma_ranges(port);
500 if (ret)
501 return ret;
502
503 xgene_pcie_linkup(port, &lanes, &speed);
504 if (!port->link_up)
505 dev_info(port->dev, "(rc) link down\n");
506 else
507 dev_info(port->dev, "(rc) x%d gen-%d link up\n",
508 lanes, speed + 1);
509 return 0;
510 }
511
xgene_pcie_probe_bridge(struct platform_device * pdev)512 static int xgene_pcie_probe_bridge(struct platform_device *pdev)
513 {
514 struct device_node *dn = pdev->dev.of_node;
515 struct xgene_pcie_port *port;
516 resource_size_t iobase = 0;
517 struct pci_bus *bus;
518 int ret;
519 LIST_HEAD(res);
520
521 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
522 if (!port)
523 return -ENOMEM;
524 port->node = of_node_get(pdev->dev.of_node);
525 port->dev = &pdev->dev;
526
527 port->version = XGENE_PCIE_IP_VER_UNKN;
528 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
529 port->version = XGENE_PCIE_IP_VER_1;
530
531 ret = xgene_pcie_map_reg(port, pdev);
532 if (ret)
533 return ret;
534
535 ret = xgene_pcie_init_port(port);
536 if (ret)
537 return ret;
538
539 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
540 if (ret)
541 return ret;
542
543 ret = xgene_pcie_setup(port, &res, iobase);
544 if (ret)
545 return ret;
546
547 bus = pci_create_root_bus(&pdev->dev, 0,
548 &xgene_pcie_ops, port, &res);
549 if (!bus)
550 return -ENOMEM;
551
552 pci_scan_child_bus(bus);
553 pci_assign_unassigned_bus_resources(bus);
554 pci_bus_add_devices(bus);
555
556 platform_set_drvdata(pdev, port);
557 return 0;
558 }
559
560 static const struct of_device_id xgene_pcie_match_table[] = {
561 {.compatible = "apm,xgene-pcie",},
562 {},
563 };
564
565 static struct platform_driver xgene_pcie_driver = {
566 .driver = {
567 .name = "xgene-pcie",
568 .of_match_table = of_match_ptr(xgene_pcie_match_table),
569 },
570 .probe = xgene_pcie_probe_bridge,
571 };
572 module_platform_driver(xgene_pcie_driver);
573
574 MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
575 MODULE_DESCRIPTION("APM X-Gene PCIe driver");
576 MODULE_LICENSE("GPL v2");
577