1 /*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
31 #include <linux/sizes.h>
32
33 /* Controller needs driver to swap endian */
34 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
35 /* Controller needs 4x internal clock */
36 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
37 /*
38 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
39 * trigger data transfer even though extern data will not transferred.
40 */
41 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 /* Controller cannot wake up from wait mode, TKT245618 */
43 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
44
45 /* The registers */
46 #define QUADSPI_MCR 0x00
47 #define QUADSPI_MCR_RESERVED_SHIFT 16
48 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
49 #define QUADSPI_MCR_MDIS_SHIFT 14
50 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
51 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
52 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
53 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
54 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
55 #define QUADSPI_MCR_DDR_EN_SHIFT 7
56 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
57 #define QUADSPI_MCR_END_CFG_SHIFT 2
58 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
59 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
60 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
61 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
62 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
63
64 #define QUADSPI_IPCR 0x08
65 #define QUADSPI_IPCR_SEQID_SHIFT 24
66 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
67
68 #define QUADSPI_BUF0CR 0x10
69 #define QUADSPI_BUF1CR 0x14
70 #define QUADSPI_BUF2CR 0x18
71 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
72
73 #define QUADSPI_BUF3CR 0x1c
74 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
75 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
76 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
77 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
78
79 #define QUADSPI_BFGENCR 0x20
80 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
81 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
82 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
83 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
84
85 #define QUADSPI_BUF0IND 0x30
86 #define QUADSPI_BUF1IND 0x34
87 #define QUADSPI_BUF2IND 0x38
88 #define QUADSPI_SFAR 0x100
89
90 #define QUADSPI_SMPR 0x108
91 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
92 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
93 #define QUADSPI_SMPR_FSDLY_SHIFT 6
94 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
95 #define QUADSPI_SMPR_FSPHS_SHIFT 5
96 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
97 #define QUADSPI_SMPR_HSENA_SHIFT 0
98 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
99
100 #define QUADSPI_RBSR 0x10c
101 #define QUADSPI_RBSR_RDBFL_SHIFT 8
102 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
103
104 #define QUADSPI_RBCT 0x110
105 #define QUADSPI_RBCT_WMRK_MASK 0x1F
106 #define QUADSPI_RBCT_RXBRD_SHIFT 8
107 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
108
109 #define QUADSPI_TBSR 0x150
110 #define QUADSPI_TBDR 0x154
111 #define QUADSPI_SR 0x15c
112 #define QUADSPI_SR_IP_ACC_SHIFT 1
113 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
114 #define QUADSPI_SR_AHB_ACC_SHIFT 2
115 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
116
117 #define QUADSPI_FR 0x160
118 #define QUADSPI_FR_TFF_MASK 0x1
119
120 #define QUADSPI_SFA1AD 0x180
121 #define QUADSPI_SFA2AD 0x184
122 #define QUADSPI_SFB1AD 0x188
123 #define QUADSPI_SFB2AD 0x18c
124 #define QUADSPI_RBDR 0x200
125
126 #define QUADSPI_LUTKEY 0x300
127 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
128
129 #define QUADSPI_LCKCR 0x304
130 #define QUADSPI_LCKER_LOCK 0x1
131 #define QUADSPI_LCKER_UNLOCK 0x2
132
133 #define QUADSPI_RSER 0x164
134 #define QUADSPI_RSER_TFIE (0x1 << 0)
135
136 #define QUADSPI_LUT_BASE 0x310
137
138 /*
139 * The definition of the LUT register shows below:
140 *
141 * ---------------------------------------------------
142 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
143 * ---------------------------------------------------
144 */
145 #define OPRND0_SHIFT 0
146 #define PAD0_SHIFT 8
147 #define INSTR0_SHIFT 10
148 #define OPRND1_SHIFT 16
149
150 /* Instruction set for the LUT register. */
151 #define LUT_STOP 0
152 #define LUT_CMD 1
153 #define LUT_ADDR 2
154 #define LUT_DUMMY 3
155 #define LUT_MODE 4
156 #define LUT_MODE2 5
157 #define LUT_MODE4 6
158 #define LUT_FSL_READ 7
159 #define LUT_FSL_WRITE 8
160 #define LUT_JMP_ON_CS 9
161 #define LUT_ADDR_DDR 10
162 #define LUT_MODE_DDR 11
163 #define LUT_MODE2_DDR 12
164 #define LUT_MODE4_DDR 13
165 #define LUT_FSL_READ_DDR 14
166 #define LUT_FSL_WRITE_DDR 15
167 #define LUT_DATA_LEARN 16
168
169 /*
170 * The PAD definitions for LUT register.
171 *
172 * The pad stands for the lines number of IO[0:3].
173 * For example, the Quad read need four IO lines, so you should
174 * set LUT_PAD4 which means we use four IO lines.
175 */
176 #define LUT_PAD1 0
177 #define LUT_PAD2 1
178 #define LUT_PAD4 2
179
180 /* Oprands for the LUT register. */
181 #define ADDR24BIT 0x18
182 #define ADDR32BIT 0x20
183
184 /* Macros for constructing the LUT register. */
185 #define LUT0(ins, pad, opr) \
186 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
187 ((LUT_##ins) << INSTR0_SHIFT))
188
189 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
190
191 /* other macros for LUT register. */
192 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
193 #define QUADSPI_LUT_NUM 64
194
195 /* SEQID -- we can have 16 seqids at most. */
196 #define SEQID_QUAD_READ 0
197 #define SEQID_WREN 1
198 #define SEQID_WRDI 2
199 #define SEQID_RDSR 3
200 #define SEQID_SE 4
201 #define SEQID_CHIP_ERASE 5
202 #define SEQID_PP 6
203 #define SEQID_RDID 7
204 #define SEQID_WRSR 8
205 #define SEQID_RDCR 9
206 #define SEQID_EN4B 10
207 #define SEQID_BRWR 11
208
209 #define QUADSPI_MIN_IOMAP SZ_4M
210
211 enum fsl_qspi_devtype {
212 FSL_QUADSPI_VYBRID,
213 FSL_QUADSPI_IMX6SX,
214 FSL_QUADSPI_IMX7D,
215 FSL_QUADSPI_IMX6UL,
216 };
217
218 struct fsl_qspi_devtype_data {
219 enum fsl_qspi_devtype devtype;
220 int rxfifo;
221 int txfifo;
222 int ahb_buf_size;
223 int driver_data;
224 };
225
226 static struct fsl_qspi_devtype_data vybrid_data = {
227 .devtype = FSL_QUADSPI_VYBRID,
228 .rxfifo = 128,
229 .txfifo = 64,
230 .ahb_buf_size = 1024,
231 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
232 };
233
234 static struct fsl_qspi_devtype_data imx6sx_data = {
235 .devtype = FSL_QUADSPI_IMX6SX,
236 .rxfifo = 128,
237 .txfifo = 512,
238 .ahb_buf_size = 1024,
239 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
240 | QUADSPI_QUIRK_TKT245618,
241 };
242
243 static struct fsl_qspi_devtype_data imx7d_data = {
244 .devtype = FSL_QUADSPI_IMX7D,
245 .rxfifo = 512,
246 .txfifo = 512,
247 .ahb_buf_size = 1024,
248 .driver_data = QUADSPI_QUIRK_TKT253890
249 | QUADSPI_QUIRK_4X_INT_CLK,
250 };
251
252 static struct fsl_qspi_devtype_data imx6ul_data = {
253 .devtype = FSL_QUADSPI_IMX6UL,
254 .rxfifo = 128,
255 .txfifo = 512,
256 .ahb_buf_size = 1024,
257 .driver_data = QUADSPI_QUIRK_TKT253890
258 | QUADSPI_QUIRK_4X_INT_CLK,
259 };
260
261 #define FSL_QSPI_MAX_CHIP 4
262 struct fsl_qspi {
263 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
264 void __iomem *iobase;
265 void __iomem *ahb_addr;
266 u32 memmap_phy;
267 u32 memmap_offs;
268 u32 memmap_len;
269 struct clk *clk, *clk_en;
270 struct device *dev;
271 struct completion c;
272 struct fsl_qspi_devtype_data *devtype_data;
273 u32 nor_size;
274 u32 nor_num;
275 u32 clk_rate;
276 unsigned int chip_base_addr; /* We may support two chips. */
277 bool has_second_chip;
278 struct mutex lock;
279 struct pm_qos_request pm_qos_req;
280 };
281
needs_swap_endian(struct fsl_qspi * q)282 static inline int needs_swap_endian(struct fsl_qspi *q)
283 {
284 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
285 }
286
needs_4x_clock(struct fsl_qspi * q)287 static inline int needs_4x_clock(struct fsl_qspi *q)
288 {
289 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
290 }
291
needs_fill_txfifo(struct fsl_qspi * q)292 static inline int needs_fill_txfifo(struct fsl_qspi *q)
293 {
294 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
295 }
296
needs_wakeup_wait_mode(struct fsl_qspi * q)297 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
298 {
299 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
300 }
301
302 /*
303 * An IC bug makes us to re-arrange the 32-bit data.
304 * The following chips, such as IMX6SLX, have fixed this bug.
305 */
fsl_qspi_endian_xchg(struct fsl_qspi * q,u32 a)306 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
307 {
308 return needs_swap_endian(q) ? __swab32(a) : a;
309 }
310
fsl_qspi_unlock_lut(struct fsl_qspi * q)311 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
312 {
313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
315 }
316
fsl_qspi_lock_lut(struct fsl_qspi * q)317 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
318 {
319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
321 }
322
fsl_qspi_irq_handler(int irq,void * dev_id)323 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
324 {
325 struct fsl_qspi *q = dev_id;
326 u32 reg;
327
328 /* clear interrupt */
329 reg = readl(q->iobase + QUADSPI_FR);
330 writel(reg, q->iobase + QUADSPI_FR);
331
332 if (reg & QUADSPI_FR_TFF_MASK)
333 complete(&q->c);
334
335 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
336 return IRQ_HANDLED;
337 }
338
fsl_qspi_init_lut(struct fsl_qspi * q)339 static void fsl_qspi_init_lut(struct fsl_qspi *q)
340 {
341 void __iomem *base = q->iobase;
342 int rxfifo = q->devtype_data->rxfifo;
343 u32 lut_base;
344 u8 cmd, addrlen, dummy;
345 int i;
346
347 fsl_qspi_unlock_lut(q);
348
349 /* Clear all the LUT table */
350 for (i = 0; i < QUADSPI_LUT_NUM; i++)
351 writel(0, base + QUADSPI_LUT_BASE + i * 4);
352
353 /* Quad Read */
354 lut_base = SEQID_QUAD_READ * 4;
355
356 if (q->nor_size <= SZ_16M) {
357 cmd = SPINOR_OP_READ_1_1_4;
358 addrlen = ADDR24BIT;
359 dummy = 8;
360 } else {
361 /* use the 4-byte address */
362 cmd = SPINOR_OP_READ_1_1_4;
363 addrlen = ADDR32BIT;
364 dummy = 8;
365 }
366
367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
368 base + QUADSPI_LUT(lut_base));
369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
370 base + QUADSPI_LUT(lut_base + 1));
371
372 /* Write enable */
373 lut_base = SEQID_WREN * 4;
374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
375
376 /* Page Program */
377 lut_base = SEQID_PP * 4;
378
379 if (q->nor_size <= SZ_16M) {
380 cmd = SPINOR_OP_PP;
381 addrlen = ADDR24BIT;
382 } else {
383 /* use the 4-byte address */
384 cmd = SPINOR_OP_PP;
385 addrlen = ADDR32BIT;
386 }
387
388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
389 base + QUADSPI_LUT(lut_base));
390 writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
391
392 /* Read Status */
393 lut_base = SEQID_RDSR * 4;
394 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
395 base + QUADSPI_LUT(lut_base));
396
397 /* Erase a sector */
398 lut_base = SEQID_SE * 4;
399
400 cmd = q->nor[0].erase_opcode;
401 addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
402
403 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
404 base + QUADSPI_LUT(lut_base));
405
406 /* Erase the whole chip */
407 lut_base = SEQID_CHIP_ERASE * 4;
408 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
409 base + QUADSPI_LUT(lut_base));
410
411 /* READ ID */
412 lut_base = SEQID_RDID * 4;
413 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
414 base + QUADSPI_LUT(lut_base));
415
416 /* Write Register */
417 lut_base = SEQID_WRSR * 4;
418 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
419 base + QUADSPI_LUT(lut_base));
420
421 /* Read Configuration Register */
422 lut_base = SEQID_RDCR * 4;
423 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
424 base + QUADSPI_LUT(lut_base));
425
426 /* Write disable */
427 lut_base = SEQID_WRDI * 4;
428 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
429
430 /* Enter 4 Byte Mode (Micron) */
431 lut_base = SEQID_EN4B * 4;
432 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
433
434 /* Enter 4 Byte Mode (Spansion) */
435 lut_base = SEQID_BRWR * 4;
436 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
437
438 fsl_qspi_lock_lut(q);
439 }
440
441 /* Get the SEQID for the command */
fsl_qspi_get_seqid(struct fsl_qspi * q,u8 cmd)442 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
443 {
444 switch (cmd) {
445 case SPINOR_OP_READ_1_1_4:
446 return SEQID_QUAD_READ;
447 case SPINOR_OP_WREN:
448 return SEQID_WREN;
449 case SPINOR_OP_WRDI:
450 return SEQID_WRDI;
451 case SPINOR_OP_RDSR:
452 return SEQID_RDSR;
453 case SPINOR_OP_SE:
454 return SEQID_SE;
455 case SPINOR_OP_CHIP_ERASE:
456 return SEQID_CHIP_ERASE;
457 case SPINOR_OP_PP:
458 return SEQID_PP;
459 case SPINOR_OP_RDID:
460 return SEQID_RDID;
461 case SPINOR_OP_WRSR:
462 return SEQID_WRSR;
463 case SPINOR_OP_RDCR:
464 return SEQID_RDCR;
465 case SPINOR_OP_EN4B:
466 return SEQID_EN4B;
467 case SPINOR_OP_BRWR:
468 return SEQID_BRWR;
469 default:
470 if (cmd == q->nor[0].erase_opcode)
471 return SEQID_SE;
472 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
473 break;
474 }
475 return -EINVAL;
476 }
477
478 static int
fsl_qspi_runcmd(struct fsl_qspi * q,u8 cmd,unsigned int addr,int len)479 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
480 {
481 void __iomem *base = q->iobase;
482 int seqid;
483 u32 reg, reg2;
484 int err;
485
486 init_completion(&q->c);
487 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
488 q->chip_base_addr, addr, len, cmd);
489
490 /* save the reg */
491 reg = readl(base + QUADSPI_MCR);
492
493 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
494 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
495 base + QUADSPI_RBCT);
496 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
497
498 do {
499 reg2 = readl(base + QUADSPI_SR);
500 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
501 udelay(1);
502 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
503 continue;
504 }
505 break;
506 } while (1);
507
508 /* trigger the LUT now */
509 seqid = fsl_qspi_get_seqid(q, cmd);
510 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
511
512 /* Wait for the interrupt. */
513 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
514 dev_err(q->dev,
515 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
516 cmd, addr, readl(base + QUADSPI_FR),
517 readl(base + QUADSPI_SR));
518 err = -ETIMEDOUT;
519 } else {
520 err = 0;
521 }
522
523 /* restore the MCR */
524 writel(reg, base + QUADSPI_MCR);
525
526 return err;
527 }
528
529 /* Read out the data from the QUADSPI_RBDR buffer registers. */
fsl_qspi_read_data(struct fsl_qspi * q,int len,u8 * rxbuf)530 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
531 {
532 u32 tmp;
533 int i = 0;
534
535 while (len > 0) {
536 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
537 tmp = fsl_qspi_endian_xchg(q, tmp);
538 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
539 q->chip_base_addr, tmp);
540
541 if (len >= 4) {
542 *((u32 *)rxbuf) = tmp;
543 rxbuf += 4;
544 } else {
545 memcpy(rxbuf, &tmp, len);
546 break;
547 }
548
549 len -= 4;
550 i++;
551 }
552 }
553
554 /*
555 * If we have changed the content of the flash by writing or erasing,
556 * we need to invalidate the AHB buffer. If we do not do so, we may read out
557 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
558 * domain at the same time.
559 */
fsl_qspi_invalid(struct fsl_qspi * q)560 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
561 {
562 u32 reg;
563
564 reg = readl(q->iobase + QUADSPI_MCR);
565 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
566 writel(reg, q->iobase + QUADSPI_MCR);
567
568 /*
569 * The minimum delay : 1 AHB + 2 SFCK clocks.
570 * Delay 1 us is enough.
571 */
572 udelay(1);
573
574 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
575 writel(reg, q->iobase + QUADSPI_MCR);
576 }
577
fsl_qspi_nor_write(struct fsl_qspi * q,struct spi_nor * nor,u8 opcode,unsigned int to,u32 * txbuf,unsigned count,size_t * retlen)578 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
579 u8 opcode, unsigned int to, u32 *txbuf,
580 unsigned count, size_t *retlen)
581 {
582 int ret, i, j;
583 u32 tmp;
584
585 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
586 q->chip_base_addr, to, count);
587
588 /* clear the TX FIFO. */
589 tmp = readl(q->iobase + QUADSPI_MCR);
590 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
591
592 /* fill the TX data to the FIFO */
593 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
594 tmp = fsl_qspi_endian_xchg(q, *txbuf);
595 writel(tmp, q->iobase + QUADSPI_TBDR);
596 txbuf++;
597 }
598
599 /* fill the TXFIFO upto 16 bytes for i.MX7d */
600 if (needs_fill_txfifo(q))
601 for (; i < 4; i++)
602 writel(tmp, q->iobase + QUADSPI_TBDR);
603
604 /* Trigger it */
605 ret = fsl_qspi_runcmd(q, opcode, to, count);
606
607 if (ret == 0 && retlen)
608 *retlen += count;
609
610 return ret;
611 }
612
fsl_qspi_set_map_addr(struct fsl_qspi * q)613 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
614 {
615 int nor_size = q->nor_size;
616 void __iomem *base = q->iobase;
617
618 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
619 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
620 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
621 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
622 }
623
624 /*
625 * There are two different ways to read out the data from the flash:
626 * the "IP Command Read" and the "AHB Command Read".
627 *
628 * The IC guy suggests we use the "AHB Command Read" which is faster
629 * then the "IP Command Read". (What's more is that there is a bug in
630 * the "IP Command Read" in the Vybrid.)
631 *
632 * After we set up the registers for the "AHB Command Read", we can use
633 * the memcpy to read the data directly. A "missed" access to the buffer
634 * causes the controller to clear the buffer, and use the sequence pointed
635 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
636 */
fsl_qspi_init_abh_read(struct fsl_qspi * q)637 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
638 {
639 void __iomem *base = q->iobase;
640 int seqid;
641
642 /* AHB configuration for access buffer 0/1/2 .*/
643 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
644 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
645 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
646 /*
647 * Set ADATSZ with the maximum AHB buffer size to improve the
648 * read performance.
649 */
650 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
651 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
652
653 /* We only use the buffer3 */
654 writel(0, base + QUADSPI_BUF0IND);
655 writel(0, base + QUADSPI_BUF1IND);
656 writel(0, base + QUADSPI_BUF2IND);
657
658 /* Set the default lut sequence for AHB Read. */
659 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
660 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
661 q->iobase + QUADSPI_BFGENCR);
662 }
663
664 /* This function was used to prepare and enable QSPI clock */
fsl_qspi_clk_prep_enable(struct fsl_qspi * q)665 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
666 {
667 int ret;
668
669 ret = clk_prepare_enable(q->clk_en);
670 if (ret)
671 return ret;
672
673 ret = clk_prepare_enable(q->clk);
674 if (ret) {
675 clk_disable_unprepare(q->clk_en);
676 return ret;
677 }
678
679 if (needs_wakeup_wait_mode(q))
680 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
681
682 return 0;
683 }
684
685 /* This function was used to disable and unprepare QSPI clock */
fsl_qspi_clk_disable_unprep(struct fsl_qspi * q)686 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
687 {
688 if (needs_wakeup_wait_mode(q))
689 pm_qos_remove_request(&q->pm_qos_req);
690
691 clk_disable_unprepare(q->clk);
692 clk_disable_unprepare(q->clk_en);
693
694 }
695
696 /* We use this function to do some basic init for spi_nor_scan(). */
fsl_qspi_nor_setup(struct fsl_qspi * q)697 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
698 {
699 void __iomem *base = q->iobase;
700 u32 reg;
701 int ret;
702
703 /* disable and unprepare clock to avoid glitch pass to controller */
704 fsl_qspi_clk_disable_unprep(q);
705
706 /* the default frequency, we will change it in the future. */
707 ret = clk_set_rate(q->clk, 66000000);
708 if (ret)
709 return ret;
710
711 ret = fsl_qspi_clk_prep_enable(q);
712 if (ret)
713 return ret;
714
715 /* Reset the module */
716 writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
717 base + QUADSPI_MCR);
718 udelay(1);
719
720 /* Init the LUT table. */
721 fsl_qspi_init_lut(q);
722
723 /* Disable the module */
724 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
725 base + QUADSPI_MCR);
726
727 reg = readl(base + QUADSPI_SMPR);
728 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
729 | QUADSPI_SMPR_FSPHS_MASK
730 | QUADSPI_SMPR_HSENA_MASK
731 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
732
733 /* Enable the module */
734 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
735 base + QUADSPI_MCR);
736
737 /* clear all interrupt status */
738 writel(0xffffffff, q->iobase + QUADSPI_FR);
739
740 /* enable the interrupt */
741 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
742
743 return 0;
744 }
745
fsl_qspi_nor_setup_last(struct fsl_qspi * q)746 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
747 {
748 unsigned long rate = q->clk_rate;
749 int ret;
750
751 if (needs_4x_clock(q))
752 rate *= 4;
753
754 /* disable and unprepare clock to avoid glitch pass to controller */
755 fsl_qspi_clk_disable_unprep(q);
756
757 ret = clk_set_rate(q->clk, rate);
758 if (ret)
759 return ret;
760
761 ret = fsl_qspi_clk_prep_enable(q);
762 if (ret)
763 return ret;
764
765 /* Init the LUT table again. */
766 fsl_qspi_init_lut(q);
767
768 /* Init for AHB read */
769 fsl_qspi_init_abh_read(q);
770
771 return 0;
772 }
773
774 static const struct of_device_id fsl_qspi_dt_ids[] = {
775 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
776 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
777 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
778 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
779 { /* sentinel */ }
780 };
781 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
782
fsl_qspi_set_base_addr(struct fsl_qspi * q,struct spi_nor * nor)783 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
784 {
785 q->chip_base_addr = q->nor_size * (nor - q->nor);
786 }
787
fsl_qspi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)788 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
789 {
790 int ret;
791 struct fsl_qspi *q = nor->priv;
792
793 ret = fsl_qspi_runcmd(q, opcode, 0, len);
794 if (ret)
795 return ret;
796
797 fsl_qspi_read_data(q, len, buf);
798 return 0;
799 }
800
fsl_qspi_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)801 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
802 {
803 struct fsl_qspi *q = nor->priv;
804 int ret;
805
806 if (!buf) {
807 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
808 if (ret)
809 return ret;
810
811 if (opcode == SPINOR_OP_CHIP_ERASE)
812 fsl_qspi_invalid(q);
813
814 } else if (len > 0) {
815 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
816 (u32 *)buf, len, NULL);
817 } else {
818 dev_err(q->dev, "invalid cmd %d\n", opcode);
819 ret = -EINVAL;
820 }
821
822 return ret;
823 }
824
fsl_qspi_write(struct spi_nor * nor,loff_t to,size_t len,size_t * retlen,const u_char * buf)825 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
826 size_t len, size_t *retlen, const u_char *buf)
827 {
828 struct fsl_qspi *q = nor->priv;
829
830 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
831 (u32 *)buf, len, retlen);
832
833 /* invalid the data in the AHB buffer. */
834 fsl_qspi_invalid(q);
835 }
836
fsl_qspi_read(struct spi_nor * nor,loff_t from,size_t len,size_t * retlen,u_char * buf)837 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
838 size_t len, size_t *retlen, u_char *buf)
839 {
840 struct fsl_qspi *q = nor->priv;
841 u8 cmd = nor->read_opcode;
842
843 /* if necessary,ioremap buffer before AHB read, */
844 if (!q->ahb_addr) {
845 q->memmap_offs = q->chip_base_addr + from;
846 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
847
848 q->ahb_addr = ioremap_nocache(
849 q->memmap_phy + q->memmap_offs,
850 q->memmap_len);
851 if (!q->ahb_addr) {
852 dev_err(q->dev, "ioremap failed\n");
853 return -ENOMEM;
854 }
855 /* ioremap if the data requested is out of range */
856 } else if (q->chip_base_addr + from < q->memmap_offs
857 || q->chip_base_addr + from + len >
858 q->memmap_offs + q->memmap_len) {
859 iounmap(q->ahb_addr);
860
861 q->memmap_offs = q->chip_base_addr + from;
862 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
863 q->ahb_addr = ioremap_nocache(
864 q->memmap_phy + q->memmap_offs,
865 q->memmap_len);
866 if (!q->ahb_addr) {
867 dev_err(q->dev, "ioremap failed\n");
868 return -ENOMEM;
869 }
870 }
871
872 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
873 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
874 len);
875
876 /* Read out the data directly from the AHB buffer.*/
877 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
878 len);
879
880 *retlen += len;
881 return 0;
882 }
883
fsl_qspi_erase(struct spi_nor * nor,loff_t offs)884 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
885 {
886 struct fsl_qspi *q = nor->priv;
887 int ret;
888
889 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
890 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
891
892 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
893 if (ret)
894 return ret;
895
896 fsl_qspi_invalid(q);
897 return 0;
898 }
899
fsl_qspi_prep(struct spi_nor * nor,enum spi_nor_ops ops)900 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
901 {
902 struct fsl_qspi *q = nor->priv;
903 int ret;
904
905 mutex_lock(&q->lock);
906
907 ret = fsl_qspi_clk_prep_enable(q);
908 if (ret)
909 goto err_mutex;
910
911 fsl_qspi_set_base_addr(q, nor);
912 return 0;
913
914 err_mutex:
915 mutex_unlock(&q->lock);
916 return ret;
917 }
918
fsl_qspi_unprep(struct spi_nor * nor,enum spi_nor_ops ops)919 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
920 {
921 struct fsl_qspi *q = nor->priv;
922
923 fsl_qspi_clk_disable_unprep(q);
924 mutex_unlock(&q->lock);
925 }
926
fsl_qspi_probe(struct platform_device * pdev)927 static int fsl_qspi_probe(struct platform_device *pdev)
928 {
929 struct device_node *np = pdev->dev.of_node;
930 struct mtd_part_parser_data ppdata;
931 struct device *dev = &pdev->dev;
932 struct fsl_qspi *q;
933 struct resource *res;
934 struct spi_nor *nor;
935 struct mtd_info *mtd;
936 int ret, i = 0;
937 const struct of_device_id *of_id =
938 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
939
940 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
941 if (!q)
942 return -ENOMEM;
943
944 q->nor_num = of_get_child_count(dev->of_node);
945 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
946 return -ENODEV;
947
948 q->dev = dev;
949 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
950 platform_set_drvdata(pdev, q);
951
952 /* find the resources */
953 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
954 q->iobase = devm_ioremap_resource(dev, res);
955 if (IS_ERR(q->iobase))
956 return PTR_ERR(q->iobase);
957
958 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
959 "QuadSPI-memory");
960 if (!devm_request_mem_region(dev, res->start, resource_size(res),
961 res->name)) {
962 dev_err(dev, "can't request region for resource %pR\n", res);
963 return -EBUSY;
964 }
965
966 q->memmap_phy = res->start;
967
968 /* find the clocks */
969 q->clk_en = devm_clk_get(dev, "qspi_en");
970 if (IS_ERR(q->clk_en))
971 return PTR_ERR(q->clk_en);
972
973 q->clk = devm_clk_get(dev, "qspi");
974 if (IS_ERR(q->clk))
975 return PTR_ERR(q->clk);
976
977 ret = fsl_qspi_clk_prep_enable(q);
978 if (ret) {
979 dev_err(dev, "can not enable the clock\n");
980 goto clk_failed;
981 }
982
983 /* find the irq */
984 ret = platform_get_irq(pdev, 0);
985 if (ret < 0) {
986 dev_err(dev, "failed to get the irq: %d\n", ret);
987 goto irq_failed;
988 }
989
990 ret = devm_request_irq(dev, ret,
991 fsl_qspi_irq_handler, 0, pdev->name, q);
992 if (ret) {
993 dev_err(dev, "failed to request irq: %d\n", ret);
994 goto irq_failed;
995 }
996
997 ret = fsl_qspi_nor_setup(q);
998 if (ret)
999 goto irq_failed;
1000
1001 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1002 q->has_second_chip = true;
1003
1004 mutex_init(&q->lock);
1005
1006 /* iterate the subnodes. */
1007 for_each_available_child_of_node(dev->of_node, np) {
1008 /* skip the holes */
1009 if (!q->has_second_chip)
1010 i *= 2;
1011
1012 nor = &q->nor[i];
1013 mtd = &nor->mtd;
1014
1015 nor->dev = dev;
1016 nor->flash_node = np;
1017 nor->priv = q;
1018
1019 /* fill the hooks */
1020 nor->read_reg = fsl_qspi_read_reg;
1021 nor->write_reg = fsl_qspi_write_reg;
1022 nor->read = fsl_qspi_read;
1023 nor->write = fsl_qspi_write;
1024 nor->erase = fsl_qspi_erase;
1025
1026 nor->prepare = fsl_qspi_prep;
1027 nor->unprepare = fsl_qspi_unprep;
1028
1029 ret = of_property_read_u32(np, "spi-max-frequency",
1030 &q->clk_rate);
1031 if (ret < 0)
1032 goto mutex_failed;
1033
1034 /* set the chip address for READID */
1035 fsl_qspi_set_base_addr(q, nor);
1036
1037 ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
1038 if (ret)
1039 goto mutex_failed;
1040
1041 ppdata.of_node = np;
1042 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1043 if (ret)
1044 goto mutex_failed;
1045
1046 /* Set the correct NOR size now. */
1047 if (q->nor_size == 0) {
1048 q->nor_size = mtd->size;
1049
1050 /* Map the SPI NOR to accessiable address */
1051 fsl_qspi_set_map_addr(q);
1052 }
1053
1054 /*
1055 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1056 * may writes 265 bytes per time. The write is working in the
1057 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1058 * size.
1059 *
1060 * So shrink the spi_nor->page_size if it is larger then the
1061 * TX FIFO.
1062 */
1063 if (nor->page_size > q->devtype_data->txfifo)
1064 nor->page_size = q->devtype_data->txfifo;
1065
1066 i++;
1067 }
1068
1069 /* finish the rest init. */
1070 ret = fsl_qspi_nor_setup_last(q);
1071 if (ret)
1072 goto last_init_failed;
1073
1074 fsl_qspi_clk_disable_unprep(q);
1075 return 0;
1076
1077 last_init_failed:
1078 for (i = 0; i < q->nor_num; i++) {
1079 /* skip the holes */
1080 if (!q->has_second_chip)
1081 i *= 2;
1082 mtd_device_unregister(&q->nor[i].mtd);
1083 }
1084 mutex_failed:
1085 mutex_destroy(&q->lock);
1086 irq_failed:
1087 fsl_qspi_clk_disable_unprep(q);
1088 clk_failed:
1089 dev_err(dev, "Freescale QuadSPI probe failed\n");
1090 return ret;
1091 }
1092
fsl_qspi_remove(struct platform_device * pdev)1093 static int fsl_qspi_remove(struct platform_device *pdev)
1094 {
1095 struct fsl_qspi *q = platform_get_drvdata(pdev);
1096 int i;
1097
1098 for (i = 0; i < q->nor_num; i++) {
1099 /* skip the holes */
1100 if (!q->has_second_chip)
1101 i *= 2;
1102 mtd_device_unregister(&q->nor[i].mtd);
1103 }
1104
1105 /* disable the hardware */
1106 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1107 writel(0x0, q->iobase + QUADSPI_RSER);
1108
1109 mutex_destroy(&q->lock);
1110
1111 if (q->ahb_addr)
1112 iounmap(q->ahb_addr);
1113
1114 return 0;
1115 }
1116
fsl_qspi_suspend(struct platform_device * pdev,pm_message_t state)1117 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1118 {
1119 return 0;
1120 }
1121
fsl_qspi_resume(struct platform_device * pdev)1122 static int fsl_qspi_resume(struct platform_device *pdev)
1123 {
1124 int ret;
1125 struct fsl_qspi *q = platform_get_drvdata(pdev);
1126
1127 ret = fsl_qspi_clk_prep_enable(q);
1128 if (ret)
1129 return ret;
1130
1131 fsl_qspi_nor_setup(q);
1132 fsl_qspi_set_map_addr(q);
1133 fsl_qspi_nor_setup_last(q);
1134
1135 fsl_qspi_clk_disable_unprep(q);
1136
1137 return 0;
1138 }
1139
1140 static struct platform_driver fsl_qspi_driver = {
1141 .driver = {
1142 .name = "fsl-quadspi",
1143 .bus = &platform_bus_type,
1144 .of_match_table = fsl_qspi_dt_ids,
1145 },
1146 .probe = fsl_qspi_probe,
1147 .remove = fsl_qspi_remove,
1148 .suspend = fsl_qspi_suspend,
1149 .resume = fsl_qspi_resume,
1150 };
1151 module_platform_driver(fsl_qspi_driver);
1152
1153 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1154 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1155 MODULE_LICENSE("GPL v2");
1156