1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
38
39 #include <asm/mach/flash.h>
40 #include <linux/platform_data/mtd-mxc_nand.h>
41
42 #define DRIVER_NAME "mxc_nand"
43
44 /* Addresses for NFC registers */
45 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
54 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
56 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
64 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
68 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
69 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
74 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
75 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78
79 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81 /*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85 #define NFC_CMD (1 << 0)
86 #define NFC_ADDR (1 << 1)
87 #define NFC_INPUT (1 << 2)
88 #define NFC_OUTPUT (1 << 3)
89 #define NFC_ID (1 << 4)
90 #define NFC_STATUS (1 << 5)
91
92 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
97 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105 #define NFC_V3_WRPROT_LOCK (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8 (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134 #define NFC_V3_IPC (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ (1 << 0)
136 #define NFC_V3_IPC_INT (1 << 31)
137
138 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139
140 struct mxc_nand_host;
141
142 struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
151 u32 (*get_ecc_status)(struct mxc_nand_host *);
152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
153 void (*select_chip)(struct mtd_info *mtd, int chip);
154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
172 int ppb_shift;
173 };
174
175 struct mxc_nand_host {
176 struct mtd_info mtd;
177 struct nand_chip nand;
178 struct device *dev;
179
180 void __iomem *spare0;
181 void __iomem *main_area0;
182
183 void __iomem *base;
184 void __iomem *regs;
185 void __iomem *regs_axi;
186 void __iomem *regs_ip;
187 int status_request;
188 struct clk *clk;
189 int clk_act;
190 int irq;
191 int eccsize;
192 int active_cs;
193
194 struct completion op_completion;
195
196 uint8_t *data_buf;
197 unsigned int buf_start;
198
199 const struct mxc_nand_devtype_data *devtype_data;
200 struct mxc_nand_platform_data pdata;
201 };
202
203 /* OOB placement block for use with hardware ecc generation */
204 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
205 .eccbytes = 5,
206 .eccpos = {6, 7, 8, 9, 10},
207 .oobfree = {{0, 5}, {12, 4}, }
208 };
209
210 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
211 .eccbytes = 20,
212 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
215 };
216
217 /* OOB description for 512 byte pages with 16 byte OOB */
218 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219 .eccbytes = 1 * 9,
220 .eccpos = {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
222 },
223 .oobfree = {
224 {.offset = 0, .length = 5}
225 }
226 };
227
228 /* OOB description for 2048 byte pages with 64 byte OOB */
229 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230 .eccbytes = 4 * 9,
231 .eccpos = {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
236 },
237 .oobfree = {
238 {.offset = 2, .length = 4},
239 {.offset = 16, .length = 7},
240 {.offset = 32, .length = 7},
241 {.offset = 48, .length = 7}
242 }
243 };
244
245 /* OOB description for 4096 byte pages with 128 byte OOB */
246 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247 .eccbytes = 8 * 9,
248 .eccpos = {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
257 },
258 .oobfree = {
259 {.offset = 2, .length = 4},
260 {.offset = 16, .length = 7},
261 {.offset = 32, .length = 7},
262 {.offset = 48, .length = 7},
263 {.offset = 64, .length = 7},
264 {.offset = 80, .length = 7},
265 {.offset = 96, .length = 7},
266 {.offset = 112, .length = 7},
267 }
268 };
269
270 static const char * const part_probes[] = {
271 "cmdlinepart", "RedBoot", "ofpart", NULL };
272
memcpy32_fromio(void * trg,const void __iomem * src,size_t size)273 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
274 {
275 int i;
276 u32 *t = trg;
277 const __iomem u32 *s = src;
278
279 for (i = 0; i < (size >> 2); i++)
280 *t++ = __raw_readl(s++);
281 }
282
memcpy32_toio(void __iomem * trg,const void * src,int size)283 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
284 {
285 /* __iowrite32_copy use 32bit size values so divide by 4 */
286 __iowrite32_copy(trg, src, size / 4);
287 }
288
check_int_v3(struct mxc_nand_host * host)289 static int check_int_v3(struct mxc_nand_host *host)
290 {
291 uint32_t tmp;
292
293 tmp = readl(NFC_V3_IPC);
294 if (!(tmp & NFC_V3_IPC_INT))
295 return 0;
296
297 tmp &= ~NFC_V3_IPC_INT;
298 writel(tmp, NFC_V3_IPC);
299
300 return 1;
301 }
302
check_int_v1_v2(struct mxc_nand_host * host)303 static int check_int_v1_v2(struct mxc_nand_host *host)
304 {
305 uint32_t tmp;
306
307 tmp = readw(NFC_V1_V2_CONFIG2);
308 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
309 return 0;
310
311 if (!host->devtype_data->irqpending_quirk)
312 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
313
314 return 1;
315 }
316
irq_control_v1_v2(struct mxc_nand_host * host,int activate)317 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
318 {
319 uint16_t tmp;
320
321 tmp = readw(NFC_V1_V2_CONFIG1);
322
323 if (activate)
324 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
325 else
326 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
327
328 writew(tmp, NFC_V1_V2_CONFIG1);
329 }
330
irq_control_v3(struct mxc_nand_host * host,int activate)331 static void irq_control_v3(struct mxc_nand_host *host, int activate)
332 {
333 uint32_t tmp;
334
335 tmp = readl(NFC_V3_CONFIG2);
336
337 if (activate)
338 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
339 else
340 tmp |= NFC_V3_CONFIG2_INT_MSK;
341
342 writel(tmp, NFC_V3_CONFIG2);
343 }
344
irq_control(struct mxc_nand_host * host,int activate)345 static void irq_control(struct mxc_nand_host *host, int activate)
346 {
347 if (host->devtype_data->irqpending_quirk) {
348 if (activate)
349 enable_irq(host->irq);
350 else
351 disable_irq_nosync(host->irq);
352 } else {
353 host->devtype_data->irq_control(host, activate);
354 }
355 }
356
get_ecc_status_v1(struct mxc_nand_host * host)357 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
358 {
359 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
360 }
361
get_ecc_status_v2(struct mxc_nand_host * host)362 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
363 {
364 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
365 }
366
get_ecc_status_v3(struct mxc_nand_host * host)367 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
368 {
369 return readl(NFC_V3_ECC_STATUS_RESULT);
370 }
371
mxc_nfc_irq(int irq,void * dev_id)372 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
373 {
374 struct mxc_nand_host *host = dev_id;
375
376 if (!host->devtype_data->check_int(host))
377 return IRQ_NONE;
378
379 irq_control(host, 0);
380
381 complete(&host->op_completion);
382
383 return IRQ_HANDLED;
384 }
385
386 /* This function polls the NANDFC to wait for the basic operation to
387 * complete by checking the INT bit of config2 register.
388 */
wait_op_done(struct mxc_nand_host * host,int useirq)389 static int wait_op_done(struct mxc_nand_host *host, int useirq)
390 {
391 int ret = 0;
392
393 /*
394 * If operation is already complete, don't bother to setup an irq or a
395 * loop.
396 */
397 if (host->devtype_data->check_int(host))
398 return 0;
399
400 if (useirq) {
401 unsigned long timeout;
402
403 reinit_completion(&host->op_completion);
404
405 irq_control(host, 1);
406
407 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
408 if (!timeout && !host->devtype_data->check_int(host)) {
409 dev_dbg(host->dev, "timeout waiting for irq\n");
410 ret = -ETIMEDOUT;
411 }
412 } else {
413 int max_retries = 8000;
414 int done;
415
416 do {
417 udelay(1);
418
419 done = host->devtype_data->check_int(host);
420 if (done)
421 break;
422
423 } while (--max_retries);
424
425 if (!done) {
426 dev_dbg(host->dev, "timeout polling for completion\n");
427 ret = -ETIMEDOUT;
428 }
429 }
430
431 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
432
433 return ret;
434 }
435
send_cmd_v3(struct mxc_nand_host * host,uint16_t cmd,int useirq)436 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
437 {
438 /* fill command */
439 writel(cmd, NFC_V3_FLASH_CMD);
440
441 /* send out command */
442 writel(NFC_CMD, NFC_V3_LAUNCH);
443
444 /* Wait for operation to complete */
445 wait_op_done(host, useirq);
446 }
447
448 /* This function issues the specified command to the NAND device and
449 * waits for completion. */
send_cmd_v1_v2(struct mxc_nand_host * host,uint16_t cmd,int useirq)450 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
451 {
452 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
453
454 writew(cmd, NFC_V1_V2_FLASH_CMD);
455 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
456
457 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
458 int max_retries = 100;
459 /* Reset completion is indicated by NFC_CONFIG2 */
460 /* being set to 0 */
461 while (max_retries-- > 0) {
462 if (readw(NFC_V1_V2_CONFIG2) == 0) {
463 break;
464 }
465 udelay(1);
466 }
467 if (max_retries < 0)
468 pr_debug("%s: RESET failed\n", __func__);
469 } else {
470 /* Wait for operation to complete */
471 wait_op_done(host, useirq);
472 }
473 }
474
send_addr_v3(struct mxc_nand_host * host,uint16_t addr,int islast)475 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
476 {
477 /* fill address */
478 writel(addr, NFC_V3_FLASH_ADDR0);
479
480 /* send out address */
481 writel(NFC_ADDR, NFC_V3_LAUNCH);
482
483 wait_op_done(host, 0);
484 }
485
486 /* This function sends an address (or partial address) to the
487 * NAND device. The address is used to select the source/destination for
488 * a NAND command. */
send_addr_v1_v2(struct mxc_nand_host * host,uint16_t addr,int islast)489 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
490 {
491 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
492
493 writew(addr, NFC_V1_V2_FLASH_ADDR);
494 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
495
496 /* Wait for operation to complete */
497 wait_op_done(host, islast);
498 }
499
send_page_v3(struct mtd_info * mtd,unsigned int ops)500 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
501 {
502 struct nand_chip *nand_chip = mtd->priv;
503 struct mxc_nand_host *host = nand_chip->priv;
504 uint32_t tmp;
505
506 tmp = readl(NFC_V3_CONFIG1);
507 tmp &= ~(7 << 4);
508 writel(tmp, NFC_V3_CONFIG1);
509
510 /* transfer data from NFC ram to nand */
511 writel(ops, NFC_V3_LAUNCH);
512
513 wait_op_done(host, false);
514 }
515
send_page_v2(struct mtd_info * mtd,unsigned int ops)516 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
517 {
518 struct nand_chip *nand_chip = mtd->priv;
519 struct mxc_nand_host *host = nand_chip->priv;
520
521 /* NANDFC buffer 0 is used for page read/write */
522 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
523
524 writew(ops, NFC_V1_V2_CONFIG2);
525
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
528 }
529
send_page_v1(struct mtd_info * mtd,unsigned int ops)530 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
531 {
532 struct nand_chip *nand_chip = mtd->priv;
533 struct mxc_nand_host *host = nand_chip->priv;
534 int bufs, i;
535
536 if (mtd->writesize > 512)
537 bufs = 4;
538 else
539 bufs = 1;
540
541 for (i = 0; i < bufs; i++) {
542
543 /* NANDFC buffer 0 is used for page read/write */
544 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
545
546 writew(ops, NFC_V1_V2_CONFIG2);
547
548 /* Wait for operation to complete */
549 wait_op_done(host, true);
550 }
551 }
552
send_read_id_v3(struct mxc_nand_host * host)553 static void send_read_id_v3(struct mxc_nand_host *host)
554 {
555 /* Read ID into main buffer */
556 writel(NFC_ID, NFC_V3_LAUNCH);
557
558 wait_op_done(host, true);
559
560 memcpy32_fromio(host->data_buf, host->main_area0, 16);
561 }
562
563 /* Request the NANDFC to perform a read of the NAND device ID. */
send_read_id_v1_v2(struct mxc_nand_host * host)564 static void send_read_id_v1_v2(struct mxc_nand_host *host)
565 {
566 /* NANDFC buffer 0 is used for device ID output */
567 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
568
569 writew(NFC_ID, NFC_V1_V2_CONFIG2);
570
571 /* Wait for operation to complete */
572 wait_op_done(host, true);
573
574 memcpy32_fromio(host->data_buf, host->main_area0, 16);
575 }
576
get_dev_status_v3(struct mxc_nand_host * host)577 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
578 {
579 writew(NFC_STATUS, NFC_V3_LAUNCH);
580 wait_op_done(host, true);
581
582 return readl(NFC_V3_CONFIG1) >> 16;
583 }
584
585 /* This function requests the NANDFC to perform a read of the
586 * NAND device status and returns the current status. */
get_dev_status_v1_v2(struct mxc_nand_host * host)587 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
588 {
589 void __iomem *main_buf = host->main_area0;
590 uint32_t store;
591 uint16_t ret;
592
593 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
594
595 /*
596 * The device status is stored in main_area0. To
597 * prevent corruption of the buffer save the value
598 * and restore it afterwards.
599 */
600 store = readl(main_buf);
601
602 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
603 wait_op_done(host, true);
604
605 ret = readw(main_buf);
606
607 writel(store, main_buf);
608
609 return ret;
610 }
611
612 /* This functions is used by upper layer to checks if device is ready */
mxc_nand_dev_ready(struct mtd_info * mtd)613 static int mxc_nand_dev_ready(struct mtd_info *mtd)
614 {
615 /*
616 * NFC handles R/B internally. Therefore, this function
617 * always returns status as ready.
618 */
619 return 1;
620 }
621
mxc_nand_enable_hwecc(struct mtd_info * mtd,int mode)622 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
623 {
624 /*
625 * If HW ECC is enabled, we turn it on during init. There is
626 * no need to enable again here.
627 */
628 }
629
mxc_nand_correct_data_v1(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)630 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
631 u_char *read_ecc, u_char *calc_ecc)
632 {
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
635
636 /*
637 * 1-Bit errors are automatically corrected in HW. No need for
638 * additional correction. 2-Bit errors cannot be corrected by
639 * HW ECC, so we need to return failure
640 */
641 uint16_t ecc_status = get_ecc_status_v1(host);
642
643 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
644 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
645 return -1;
646 }
647
648 return 0;
649 }
650
mxc_nand_correct_data_v2_v3(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)651 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
653 {
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u32 ecc_stat, err;
657 int no_subpages = 1;
658 int ret = 0;
659 u8 ecc_bit_mask, err_limit;
660
661 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
662 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
663
664 no_subpages = mtd->writesize >> 9;
665
666 ecc_stat = host->devtype_data->get_ecc_status(host);
667
668 do {
669 err = ecc_stat & ecc_bit_mask;
670 if (err > err_limit) {
671 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
672 return -1;
673 } else {
674 ret += err;
675 }
676 ecc_stat >>= 4;
677 } while (--no_subpages);
678
679 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
680
681 return ret;
682 }
683
mxc_nand_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)684 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
685 u_char *ecc_code)
686 {
687 return 0;
688 }
689
mxc_nand_read_byte(struct mtd_info * mtd)690 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
691 {
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
694 uint8_t ret;
695
696 /* Check for status request */
697 if (host->status_request)
698 return host->devtype_data->get_dev_status(host) & 0xFF;
699
700 if (nand_chip->options & NAND_BUSWIDTH_16) {
701 /* only take the lower byte of each word */
702 ret = *(uint16_t *)(host->data_buf + host->buf_start);
703
704 host->buf_start += 2;
705 } else {
706 ret = *(uint8_t *)(host->data_buf + host->buf_start);
707 host->buf_start++;
708 }
709
710 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
711 return ret;
712 }
713
mxc_nand_read_word(struct mtd_info * mtd)714 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
715 {
716 struct nand_chip *nand_chip = mtd->priv;
717 struct mxc_nand_host *host = nand_chip->priv;
718 uint16_t ret;
719
720 ret = *(uint16_t *)(host->data_buf + host->buf_start);
721 host->buf_start += 2;
722
723 return ret;
724 }
725
726 /* Write data of length len to buffer buf. The data to be
727 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
728 * Operation by the NFC, the data is written to NAND Flash */
mxc_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)729 static void mxc_nand_write_buf(struct mtd_info *mtd,
730 const u_char *buf, int len)
731 {
732 struct nand_chip *nand_chip = mtd->priv;
733 struct mxc_nand_host *host = nand_chip->priv;
734 u16 col = host->buf_start;
735 int n = mtd->oobsize + mtd->writesize - col;
736
737 n = min(n, len);
738
739 memcpy(host->data_buf + col, buf, n);
740
741 host->buf_start += n;
742 }
743
744 /* Read the data buffer from the NAND Flash. To read the data from NAND
745 * Flash first the data output cycle is initiated by the NFC, which copies
746 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
747 */
mxc_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)748 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
749 {
750 struct nand_chip *nand_chip = mtd->priv;
751 struct mxc_nand_host *host = nand_chip->priv;
752 u16 col = host->buf_start;
753 int n = mtd->oobsize + mtd->writesize - col;
754
755 n = min(n, len);
756
757 memcpy(buf, host->data_buf + col, n);
758
759 host->buf_start += n;
760 }
761
762 /* This function is used by upper layer for select and
763 * deselect of the NAND chip */
mxc_nand_select_chip_v1_v3(struct mtd_info * mtd,int chip)764 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
765 {
766 struct nand_chip *nand_chip = mtd->priv;
767 struct mxc_nand_host *host = nand_chip->priv;
768
769 if (chip == -1) {
770 /* Disable the NFC clock */
771 if (host->clk_act) {
772 clk_disable_unprepare(host->clk);
773 host->clk_act = 0;
774 }
775 return;
776 }
777
778 if (!host->clk_act) {
779 /* Enable the NFC clock */
780 clk_prepare_enable(host->clk);
781 host->clk_act = 1;
782 }
783 }
784
mxc_nand_select_chip_v2(struct mtd_info * mtd,int chip)785 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
786 {
787 struct nand_chip *nand_chip = mtd->priv;
788 struct mxc_nand_host *host = nand_chip->priv;
789
790 if (chip == -1) {
791 /* Disable the NFC clock */
792 if (host->clk_act) {
793 clk_disable_unprepare(host->clk);
794 host->clk_act = 0;
795 }
796 return;
797 }
798
799 if (!host->clk_act) {
800 /* Enable the NFC clock */
801 clk_prepare_enable(host->clk);
802 host->clk_act = 1;
803 }
804
805 host->active_cs = chip;
806 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
807 }
808
809 /*
810 * Function to transfer data to/from spare area.
811 */
copy_spare(struct mtd_info * mtd,bool bfrom)812 static void copy_spare(struct mtd_info *mtd, bool bfrom)
813 {
814 struct nand_chip *this = mtd->priv;
815 struct mxc_nand_host *host = this->priv;
816 u16 i, j;
817 u16 n = mtd->writesize >> 9;
818 u8 *d = host->data_buf + mtd->writesize;
819 u8 __iomem *s = host->spare0;
820 u16 t = host->devtype_data->spare_len;
821
822 j = (mtd->oobsize / n >> 1) << 1;
823
824 if (bfrom) {
825 for (i = 0; i < n - 1; i++)
826 memcpy32_fromio(d + i * j, s + i * t, j);
827
828 /* the last section */
829 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
830 } else {
831 for (i = 0; i < n - 1; i++)
832 memcpy32_toio(&s[i * t], &d[i * j], j);
833
834 /* the last section */
835 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
836 }
837 }
838
839 /*
840 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
841 * the upper layers perform a read/write buf operation, the saved column address
842 * is used to index into the full page. So usually this function is called with
843 * column == 0 (unless no column cycle is needed indicated by column == -1)
844 */
mxc_do_addr_cycle(struct mtd_info * mtd,int column,int page_addr)845 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
846 {
847 struct nand_chip *nand_chip = mtd->priv;
848 struct mxc_nand_host *host = nand_chip->priv;
849
850 /* Write out column address, if necessary */
851 if (column != -1) {
852 host->devtype_data->send_addr(host, column & 0xff,
853 page_addr == -1);
854 if (mtd->writesize > 512)
855 /* another col addr cycle for 2k page */
856 host->devtype_data->send_addr(host,
857 (column >> 8) & 0xff,
858 false);
859 }
860
861 /* Write out page address, if necessary */
862 if (page_addr != -1) {
863 /* paddr_0 - p_addr_7 */
864 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
865
866 if (mtd->writesize > 512) {
867 if (mtd->size >= 0x10000000) {
868 /* paddr_8 - paddr_15 */
869 host->devtype_data->send_addr(host,
870 (page_addr >> 8) & 0xff,
871 false);
872 host->devtype_data->send_addr(host,
873 (page_addr >> 16) & 0xff,
874 true);
875 } else
876 /* paddr_8 - paddr_15 */
877 host->devtype_data->send_addr(host,
878 (page_addr >> 8) & 0xff, true);
879 } else {
880 /* One more address cycle for higher density devices */
881 if (mtd->size >= 0x4000000) {
882 /* paddr_8 - paddr_15 */
883 host->devtype_data->send_addr(host,
884 (page_addr >> 8) & 0xff,
885 false);
886 host->devtype_data->send_addr(host,
887 (page_addr >> 16) & 0xff,
888 true);
889 } else
890 /* paddr_8 - paddr_15 */
891 host->devtype_data->send_addr(host,
892 (page_addr >> 8) & 0xff, true);
893 }
894 }
895 }
896
897 /*
898 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
899 * on how much oob the nand chip has. For 8bit ecc we need at least
900 * 26 bytes of oob data per 512 byte block.
901 */
get_eccsize(struct mtd_info * mtd)902 static int get_eccsize(struct mtd_info *mtd)
903 {
904 int oobbytes_per_512 = 0;
905
906 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
907
908 if (oobbytes_per_512 < 26)
909 return 4;
910 else
911 return 8;
912 }
913
preset_v1(struct mtd_info * mtd)914 static void preset_v1(struct mtd_info *mtd)
915 {
916 struct nand_chip *nand_chip = mtd->priv;
917 struct mxc_nand_host *host = nand_chip->priv;
918 uint16_t config1 = 0;
919
920 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
921 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
922
923 if (!host->devtype_data->irqpending_quirk)
924 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
925
926 host->eccsize = 1;
927
928 writew(config1, NFC_V1_V2_CONFIG1);
929 /* preset operation */
930
931 /* Unlock the internal RAM Buffer */
932 writew(0x2, NFC_V1_V2_CONFIG);
933
934 /* Blocks to be unlocked */
935 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
936 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
937
938 /* Unlock Block Command for given address range */
939 writew(0x4, NFC_V1_V2_WRPROT);
940 }
941
preset_v2(struct mtd_info * mtd)942 static void preset_v2(struct mtd_info *mtd)
943 {
944 struct nand_chip *nand_chip = mtd->priv;
945 struct mxc_nand_host *host = nand_chip->priv;
946 uint16_t config1 = 0;
947
948 config1 |= NFC_V2_CONFIG1_FP_INT;
949
950 if (!host->devtype_data->irqpending_quirk)
951 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
952
953 if (mtd->writesize) {
954 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
955
956 if (nand_chip->ecc.mode == NAND_ECC_HW)
957 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
958
959 host->eccsize = get_eccsize(mtd);
960 if (host->eccsize == 4)
961 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
962
963 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
964 } else {
965 host->eccsize = 1;
966 }
967
968 writew(config1, NFC_V1_V2_CONFIG1);
969 /* preset operation */
970
971 /* Unlock the internal RAM Buffer */
972 writew(0x2, NFC_V1_V2_CONFIG);
973
974 /* Blocks to be unlocked */
975 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
976 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
977 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
978 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
979 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
980 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
981 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
982 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
983
984 /* Unlock Block Command for given address range */
985 writew(0x4, NFC_V1_V2_WRPROT);
986 }
987
preset_v3(struct mtd_info * mtd)988 static void preset_v3(struct mtd_info *mtd)
989 {
990 struct nand_chip *chip = mtd->priv;
991 struct mxc_nand_host *host = chip->priv;
992 uint32_t config2, config3;
993 int i, addr_phases;
994
995 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
996 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
997
998 /* Unlock the internal RAM Buffer */
999 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1000 NFC_V3_WRPROT);
1001
1002 /* Blocks to be unlocked */
1003 for (i = 0; i < NAND_MAX_CHIPS; i++)
1004 writel(0x0 | (0xffff << 16),
1005 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1006
1007 writel(0, NFC_V3_IPC);
1008
1009 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1010 NFC_V3_CONFIG2_2CMD_PHASES |
1011 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1012 NFC_V3_CONFIG2_ST_CMD(0x70) |
1013 NFC_V3_CONFIG2_INT_MSK |
1014 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1015
1016 addr_phases = fls(chip->pagemask) >> 3;
1017
1018 if (mtd->writesize == 2048) {
1019 config2 |= NFC_V3_CONFIG2_PS_2048;
1020 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1021 } else if (mtd->writesize == 4096) {
1022 config2 |= NFC_V3_CONFIG2_PS_4096;
1023 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1024 } else {
1025 config2 |= NFC_V3_CONFIG2_PS_512;
1026 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1027 }
1028
1029 if (mtd->writesize) {
1030 if (chip->ecc.mode == NAND_ECC_HW)
1031 config2 |= NFC_V3_CONFIG2_ECC_EN;
1032
1033 config2 |= NFC_V3_CONFIG2_PPB(
1034 ffs(mtd->erasesize / mtd->writesize) - 6,
1035 host->devtype_data->ppb_shift);
1036 host->eccsize = get_eccsize(mtd);
1037 if (host->eccsize == 8)
1038 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1039 }
1040
1041 writel(config2, NFC_V3_CONFIG2);
1042
1043 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1044 NFC_V3_CONFIG3_NO_SDMA |
1045 NFC_V3_CONFIG3_RBB_MODE |
1046 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1047 NFC_V3_CONFIG3_ADD_OP(0);
1048
1049 if (!(chip->options & NAND_BUSWIDTH_16))
1050 config3 |= NFC_V3_CONFIG3_FW8;
1051
1052 writel(config3, NFC_V3_CONFIG3);
1053
1054 writel(0, NFC_V3_DELAY_LINE);
1055 }
1056
1057 /* Used by the upper layer to write command to NAND Flash for
1058 * different operations to be carried out on NAND Flash */
mxc_nand_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)1059 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1060 int column, int page_addr)
1061 {
1062 struct nand_chip *nand_chip = mtd->priv;
1063 struct mxc_nand_host *host = nand_chip->priv;
1064
1065 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1066 command, column, page_addr);
1067
1068 /* Reset command state information */
1069 host->status_request = false;
1070
1071 /* Command pre-processing step */
1072 switch (command) {
1073 case NAND_CMD_RESET:
1074 host->devtype_data->preset(mtd);
1075 host->devtype_data->send_cmd(host, command, false);
1076 break;
1077
1078 case NAND_CMD_STATUS:
1079 host->buf_start = 0;
1080 host->status_request = true;
1081
1082 host->devtype_data->send_cmd(host, command, true);
1083 WARN_ONCE(column != -1 || page_addr != -1,
1084 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1085 command, column, page_addr);
1086 mxc_do_addr_cycle(mtd, column, page_addr);
1087 break;
1088
1089 case NAND_CMD_READ0:
1090 case NAND_CMD_READOOB:
1091 if (command == NAND_CMD_READ0)
1092 host->buf_start = column;
1093 else
1094 host->buf_start = column + mtd->writesize;
1095
1096 command = NAND_CMD_READ0; /* only READ0 is valid */
1097
1098 host->devtype_data->send_cmd(host, command, false);
1099 WARN_ONCE(column < 0,
1100 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1101 command, column, page_addr);
1102 mxc_do_addr_cycle(mtd, 0, page_addr);
1103
1104 if (mtd->writesize > 512)
1105 host->devtype_data->send_cmd(host,
1106 NAND_CMD_READSTART, true);
1107
1108 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1109
1110 memcpy32_fromio(host->data_buf, host->main_area0,
1111 mtd->writesize);
1112 copy_spare(mtd, true);
1113 break;
1114
1115 case NAND_CMD_SEQIN:
1116 if (column >= mtd->writesize)
1117 /* call ourself to read a page */
1118 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1119
1120 host->buf_start = column;
1121
1122 host->devtype_data->send_cmd(host, command, false);
1123 WARN_ONCE(column < -1,
1124 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1125 command, column, page_addr);
1126 mxc_do_addr_cycle(mtd, 0, page_addr);
1127 break;
1128
1129 case NAND_CMD_PAGEPROG:
1130 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1131 copy_spare(mtd, false);
1132 host->devtype_data->send_page(mtd, NFC_INPUT);
1133 host->devtype_data->send_cmd(host, command, true);
1134 WARN_ONCE(column != -1 || page_addr != -1,
1135 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1136 command, column, page_addr);
1137 mxc_do_addr_cycle(mtd, column, page_addr);
1138 break;
1139
1140 case NAND_CMD_READID:
1141 host->devtype_data->send_cmd(host, command, true);
1142 mxc_do_addr_cycle(mtd, column, page_addr);
1143 host->devtype_data->send_read_id(host);
1144 host->buf_start = 0;
1145 break;
1146
1147 case NAND_CMD_ERASE1:
1148 case NAND_CMD_ERASE2:
1149 host->devtype_data->send_cmd(host, command, false);
1150 WARN_ONCE(column != -1,
1151 "Unexpected column value (cmd=%u, col=%d)\n",
1152 command, column);
1153 mxc_do_addr_cycle(mtd, column, page_addr);
1154
1155 break;
1156 case NAND_CMD_PARAM:
1157 host->devtype_data->send_cmd(host, command, false);
1158 mxc_do_addr_cycle(mtd, column, page_addr);
1159 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1160 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1161 host->buf_start = 0;
1162 break;
1163 default:
1164 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1165 command);
1166 break;
1167 }
1168 }
1169
1170 /*
1171 * The generic flash bbt decriptors overlap with our ecc
1172 * hardware, so define some i.MX specific ones.
1173 */
1174 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1175 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1176
1177 static struct nand_bbt_descr bbt_main_descr = {
1178 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1179 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1180 .offs = 0,
1181 .len = 4,
1182 .veroffs = 4,
1183 .maxblocks = 4,
1184 .pattern = bbt_pattern,
1185 };
1186
1187 static struct nand_bbt_descr bbt_mirror_descr = {
1188 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1189 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1190 .offs = 0,
1191 .len = 4,
1192 .veroffs = 4,
1193 .maxblocks = 4,
1194 .pattern = mirror_pattern,
1195 };
1196
1197 /* v1 + irqpending_quirk: i.MX21 */
1198 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1199 .preset = preset_v1,
1200 .send_cmd = send_cmd_v1_v2,
1201 .send_addr = send_addr_v1_v2,
1202 .send_page = send_page_v1,
1203 .send_read_id = send_read_id_v1_v2,
1204 .get_dev_status = get_dev_status_v1_v2,
1205 .check_int = check_int_v1_v2,
1206 .irq_control = irq_control_v1_v2,
1207 .get_ecc_status = get_ecc_status_v1,
1208 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1209 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1210 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1211 .select_chip = mxc_nand_select_chip_v1_v3,
1212 .correct_data = mxc_nand_correct_data_v1,
1213 .irqpending_quirk = 1,
1214 .needs_ip = 0,
1215 .regs_offset = 0xe00,
1216 .spare0_offset = 0x800,
1217 .spare_len = 16,
1218 .eccbytes = 3,
1219 .eccsize = 1,
1220 };
1221
1222 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1223 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1224 .preset = preset_v1,
1225 .send_cmd = send_cmd_v1_v2,
1226 .send_addr = send_addr_v1_v2,
1227 .send_page = send_page_v1,
1228 .send_read_id = send_read_id_v1_v2,
1229 .get_dev_status = get_dev_status_v1_v2,
1230 .check_int = check_int_v1_v2,
1231 .irq_control = irq_control_v1_v2,
1232 .get_ecc_status = get_ecc_status_v1,
1233 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1234 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1235 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1236 .select_chip = mxc_nand_select_chip_v1_v3,
1237 .correct_data = mxc_nand_correct_data_v1,
1238 .irqpending_quirk = 0,
1239 .needs_ip = 0,
1240 .regs_offset = 0xe00,
1241 .spare0_offset = 0x800,
1242 .axi_offset = 0,
1243 .spare_len = 16,
1244 .eccbytes = 3,
1245 .eccsize = 1,
1246 };
1247
1248 /* v21: i.MX25, i.MX35 */
1249 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1250 .preset = preset_v2,
1251 .send_cmd = send_cmd_v1_v2,
1252 .send_addr = send_addr_v1_v2,
1253 .send_page = send_page_v2,
1254 .send_read_id = send_read_id_v1_v2,
1255 .get_dev_status = get_dev_status_v1_v2,
1256 .check_int = check_int_v1_v2,
1257 .irq_control = irq_control_v1_v2,
1258 .get_ecc_status = get_ecc_status_v2,
1259 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1260 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1261 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1262 .select_chip = mxc_nand_select_chip_v2,
1263 .correct_data = mxc_nand_correct_data_v2_v3,
1264 .irqpending_quirk = 0,
1265 .needs_ip = 0,
1266 .regs_offset = 0x1e00,
1267 .spare0_offset = 0x1000,
1268 .axi_offset = 0,
1269 .spare_len = 64,
1270 .eccbytes = 9,
1271 .eccsize = 0,
1272 };
1273
1274 /* v3.2a: i.MX51 */
1275 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1276 .preset = preset_v3,
1277 .send_cmd = send_cmd_v3,
1278 .send_addr = send_addr_v3,
1279 .send_page = send_page_v3,
1280 .send_read_id = send_read_id_v3,
1281 .get_dev_status = get_dev_status_v3,
1282 .check_int = check_int_v3,
1283 .irq_control = irq_control_v3,
1284 .get_ecc_status = get_ecc_status_v3,
1285 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1286 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1287 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1288 .select_chip = mxc_nand_select_chip_v1_v3,
1289 .correct_data = mxc_nand_correct_data_v2_v3,
1290 .irqpending_quirk = 0,
1291 .needs_ip = 1,
1292 .regs_offset = 0,
1293 .spare0_offset = 0x1000,
1294 .axi_offset = 0x1e00,
1295 .spare_len = 64,
1296 .eccbytes = 0,
1297 .eccsize = 0,
1298 .ppb_shift = 7,
1299 };
1300
1301 /* v3.2b: i.MX53 */
1302 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1303 .preset = preset_v3,
1304 .send_cmd = send_cmd_v3,
1305 .send_addr = send_addr_v3,
1306 .send_page = send_page_v3,
1307 .send_read_id = send_read_id_v3,
1308 .get_dev_status = get_dev_status_v3,
1309 .check_int = check_int_v3,
1310 .irq_control = irq_control_v3,
1311 .get_ecc_status = get_ecc_status_v3,
1312 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1313 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1314 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1315 .select_chip = mxc_nand_select_chip_v1_v3,
1316 .correct_data = mxc_nand_correct_data_v2_v3,
1317 .irqpending_quirk = 0,
1318 .needs_ip = 1,
1319 .regs_offset = 0,
1320 .spare0_offset = 0x1000,
1321 .axi_offset = 0x1e00,
1322 .spare_len = 64,
1323 .eccbytes = 0,
1324 .eccsize = 0,
1325 .ppb_shift = 8,
1326 };
1327
is_imx21_nfc(struct mxc_nand_host * host)1328 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1329 {
1330 return host->devtype_data == &imx21_nand_devtype_data;
1331 }
1332
is_imx27_nfc(struct mxc_nand_host * host)1333 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1334 {
1335 return host->devtype_data == &imx27_nand_devtype_data;
1336 }
1337
is_imx25_nfc(struct mxc_nand_host * host)1338 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1339 {
1340 return host->devtype_data == &imx25_nand_devtype_data;
1341 }
1342
is_imx51_nfc(struct mxc_nand_host * host)1343 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1344 {
1345 return host->devtype_data == &imx51_nand_devtype_data;
1346 }
1347
is_imx53_nfc(struct mxc_nand_host * host)1348 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1349 {
1350 return host->devtype_data == &imx53_nand_devtype_data;
1351 }
1352
1353 static struct platform_device_id mxcnd_devtype[] = {
1354 {
1355 .name = "imx21-nand",
1356 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1357 }, {
1358 .name = "imx27-nand",
1359 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1360 }, {
1361 .name = "imx25-nand",
1362 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1363 }, {
1364 .name = "imx51-nand",
1365 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1366 }, {
1367 .name = "imx53-nand",
1368 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1369 }, {
1370 /* sentinel */
1371 }
1372 };
1373 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1374
1375 #ifdef CONFIG_OF_MTD
1376 static const struct of_device_id mxcnd_dt_ids[] = {
1377 {
1378 .compatible = "fsl,imx21-nand",
1379 .data = &imx21_nand_devtype_data,
1380 }, {
1381 .compatible = "fsl,imx27-nand",
1382 .data = &imx27_nand_devtype_data,
1383 }, {
1384 .compatible = "fsl,imx25-nand",
1385 .data = &imx25_nand_devtype_data,
1386 }, {
1387 .compatible = "fsl,imx51-nand",
1388 .data = &imx51_nand_devtype_data,
1389 }, {
1390 .compatible = "fsl,imx53-nand",
1391 .data = &imx53_nand_devtype_data,
1392 },
1393 { /* sentinel */ }
1394 };
1395
mxcnd_probe_dt(struct mxc_nand_host * host)1396 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1397 {
1398 struct device_node *np = host->dev->of_node;
1399 struct mxc_nand_platform_data *pdata = &host->pdata;
1400 const struct of_device_id *of_id =
1401 of_match_device(mxcnd_dt_ids, host->dev);
1402 int buswidth;
1403
1404 if (!np)
1405 return 1;
1406
1407 if (of_get_nand_ecc_mode(np) >= 0)
1408 pdata->hw_ecc = 1;
1409
1410 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1411
1412 buswidth = of_get_nand_bus_width(np);
1413 if (buswidth < 0)
1414 return buswidth;
1415
1416 pdata->width = buswidth / 8;
1417
1418 host->devtype_data = of_id->data;
1419
1420 return 0;
1421 }
1422 #else
mxcnd_probe_dt(struct mxc_nand_host * host)1423 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1424 {
1425 return 1;
1426 }
1427 #endif
1428
mxcnd_probe(struct platform_device * pdev)1429 static int mxcnd_probe(struct platform_device *pdev)
1430 {
1431 struct nand_chip *this;
1432 struct mtd_info *mtd;
1433 struct mxc_nand_host *host;
1434 struct resource *res;
1435 int err = 0;
1436
1437 /* Allocate memory for MTD device structure and private data */
1438 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1439 GFP_KERNEL);
1440 if (!host)
1441 return -ENOMEM;
1442
1443 /* allocate a temporary buffer for the nand_scan_ident() */
1444 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1445 if (!host->data_buf)
1446 return -ENOMEM;
1447
1448 host->dev = &pdev->dev;
1449 /* structures must be linked */
1450 this = &host->nand;
1451 mtd = &host->mtd;
1452 mtd->priv = this;
1453 mtd->owner = THIS_MODULE;
1454 mtd->dev.parent = &pdev->dev;
1455 mtd->name = DRIVER_NAME;
1456
1457 /* 50 us command delay time */
1458 this->chip_delay = 5;
1459
1460 this->priv = host;
1461 this->dev_ready = mxc_nand_dev_ready;
1462 this->cmdfunc = mxc_nand_command;
1463 this->read_byte = mxc_nand_read_byte;
1464 this->read_word = mxc_nand_read_word;
1465 this->write_buf = mxc_nand_write_buf;
1466 this->read_buf = mxc_nand_read_buf;
1467
1468 host->clk = devm_clk_get(&pdev->dev, NULL);
1469 if (IS_ERR(host->clk))
1470 return PTR_ERR(host->clk);
1471
1472 err = mxcnd_probe_dt(host);
1473 if (err > 0) {
1474 struct mxc_nand_platform_data *pdata =
1475 dev_get_platdata(&pdev->dev);
1476 if (pdata) {
1477 host->pdata = *pdata;
1478 host->devtype_data = (struct mxc_nand_devtype_data *)
1479 pdev->id_entry->driver_data;
1480 } else {
1481 err = -ENODEV;
1482 }
1483 }
1484 if (err < 0)
1485 return err;
1486
1487 if (host->devtype_data->needs_ip) {
1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1489 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1490 if (IS_ERR(host->regs_ip))
1491 return PTR_ERR(host->regs_ip);
1492
1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1494 } else {
1495 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496 }
1497
1498 host->base = devm_ioremap_resource(&pdev->dev, res);
1499 if (IS_ERR(host->base))
1500 return PTR_ERR(host->base);
1501
1502 host->main_area0 = host->base;
1503
1504 if (host->devtype_data->regs_offset)
1505 host->regs = host->base + host->devtype_data->regs_offset;
1506 host->spare0 = host->base + host->devtype_data->spare0_offset;
1507 if (host->devtype_data->axi_offset)
1508 host->regs_axi = host->base + host->devtype_data->axi_offset;
1509
1510 this->ecc.bytes = host->devtype_data->eccbytes;
1511 host->eccsize = host->devtype_data->eccsize;
1512
1513 this->select_chip = host->devtype_data->select_chip;
1514 this->ecc.size = 512;
1515 this->ecc.layout = host->devtype_data->ecclayout_512;
1516
1517 if (host->pdata.hw_ecc) {
1518 this->ecc.calculate = mxc_nand_calculate_ecc;
1519 this->ecc.hwctl = mxc_nand_enable_hwecc;
1520 this->ecc.correct = host->devtype_data->correct_data;
1521 this->ecc.mode = NAND_ECC_HW;
1522 } else {
1523 this->ecc.mode = NAND_ECC_SOFT;
1524 }
1525
1526 /* NAND bus width determines access functions used by upper layer */
1527 if (host->pdata.width == 2)
1528 this->options |= NAND_BUSWIDTH_16;
1529
1530 if (host->pdata.flash_bbt) {
1531 this->bbt_td = &bbt_main_descr;
1532 this->bbt_md = &bbt_mirror_descr;
1533 /* update flash based bbt */
1534 this->bbt_options |= NAND_BBT_USE_FLASH;
1535 }
1536
1537 init_completion(&host->op_completion);
1538
1539 host->irq = platform_get_irq(pdev, 0);
1540 if (host->irq < 0)
1541 return host->irq;
1542
1543 /*
1544 * Use host->devtype_data->irq_control() here instead of irq_control()
1545 * because we must not disable_irq_nosync without having requested the
1546 * irq.
1547 */
1548 host->devtype_data->irq_control(host, 0);
1549
1550 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1551 0, DRIVER_NAME, host);
1552 if (err)
1553 return err;
1554
1555 err = clk_prepare_enable(host->clk);
1556 if (err)
1557 return err;
1558 host->clk_act = 1;
1559
1560 /*
1561 * Now that we "own" the interrupt make sure the interrupt mask bit is
1562 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1563 * on this machine.
1564 */
1565 if (host->devtype_data->irqpending_quirk) {
1566 disable_irq_nosync(host->irq);
1567 host->devtype_data->irq_control(host, 1);
1568 }
1569
1570 /* first scan to find the device and get the page size */
1571 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1572 err = -ENXIO;
1573 goto escan;
1574 }
1575
1576 /* allocate the right size buffer now */
1577 devm_kfree(&pdev->dev, (void *)host->data_buf);
1578 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1579 GFP_KERNEL);
1580 if (!host->data_buf) {
1581 err = -ENOMEM;
1582 goto escan;
1583 }
1584
1585 /* Call preset again, with correct writesize this time */
1586 host->devtype_data->preset(mtd);
1587
1588 if (mtd->writesize == 2048)
1589 this->ecc.layout = host->devtype_data->ecclayout_2k;
1590 else if (mtd->writesize == 4096)
1591 this->ecc.layout = host->devtype_data->ecclayout_4k;
1592
1593 if (this->ecc.mode == NAND_ECC_HW) {
1594 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1595 this->ecc.strength = 1;
1596 else
1597 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1598 }
1599
1600 /* second phase scan */
1601 if (nand_scan_tail(mtd)) {
1602 err = -ENXIO;
1603 goto escan;
1604 }
1605
1606 /* Register the partitions */
1607 mtd_device_parse_register(mtd, part_probes,
1608 &(struct mtd_part_parser_data){
1609 .of_node = pdev->dev.of_node,
1610 },
1611 host->pdata.parts,
1612 host->pdata.nr_parts);
1613
1614 platform_set_drvdata(pdev, host);
1615
1616 return 0;
1617
1618 escan:
1619 if (host->clk_act)
1620 clk_disable_unprepare(host->clk);
1621
1622 return err;
1623 }
1624
mxcnd_remove(struct platform_device * pdev)1625 static int mxcnd_remove(struct platform_device *pdev)
1626 {
1627 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1628
1629 nand_release(&host->mtd);
1630 if (host->clk_act)
1631 clk_disable_unprepare(host->clk);
1632
1633 return 0;
1634 }
1635
1636 static struct platform_driver mxcnd_driver = {
1637 .driver = {
1638 .name = DRIVER_NAME,
1639 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1640 },
1641 .id_table = mxcnd_devtype,
1642 .probe = mxcnd_probe,
1643 .remove = mxcnd_remove,
1644 };
1645 module_platform_driver(mxcnd_driver);
1646
1647 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1648 MODULE_DESCRIPTION("MXC NAND MTD driver");
1649 MODULE_LICENSE("GPL");
1650