1 /*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30 #include <linux/delay.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/v4l2-dv-timings.h>
37 #include <linux/videodev2.h>
38 #include <linux/workqueue.h>
39
40 #include <media/adv7604.h>
41 #include <media/v4l2-ctrls.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-dv-timings.h>
44 #include <media/v4l2-of.h>
45
46 static int debug;
47 module_param(debug, int, 0644);
48 MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53 MODULE_LICENSE("GPL");
54
55 /* ADV7604 system clock frequency */
56 #define ADV76XX_FSC (28636360)
57
58 #define ADV76XX_RGB_OUT (1 << 1)
59
60 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
61 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
63
64 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
65 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
67 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
69 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
71 #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73 #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74 #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75 #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76 #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
77
78 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
79
80 enum adv76xx_type {
81 ADV7604,
82 ADV7611,
83 };
84
85 struct adv76xx_reg_seq {
86 unsigned int reg;
87 u8 val;
88 };
89
90 struct adv76xx_format_info {
91 u32 code;
92 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96 };
97
98 struct adv76xx_chip_info {
99 enum adv76xx_type type;
100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
112 unsigned int cp_csc;
113
114 const struct adv76xx_format_info *formats;
115 unsigned int nformats;
116
117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
118 void (*setup_irqs)(struct v4l2_subdev *sd);
119 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121
122 /* 0 = AFE, 1 = HDMI */
123 const struct adv76xx_reg_seq *recommended_settings[2];
124 unsigned int num_recommended_settings[2];
125
126 unsigned long page_mask;
127 };
128
129 /*
130 **********************************************************************
131 *
132 * Arrays with configuration parameters for the ADV7604
133 *
134 **********************************************************************
135 */
136
137 struct adv76xx_state {
138 const struct adv76xx_chip_info *info;
139 struct adv76xx_platform_data pdata;
140
141 struct gpio_desc *hpd_gpio[4];
142
143 struct v4l2_subdev sd;
144 struct media_pad pads[ADV76XX_PAD_MAX];
145 unsigned int source_pad;
146
147 struct v4l2_ctrl_handler hdl;
148
149 enum adv76xx_pad selected_input;
150
151 struct v4l2_dv_timings timings;
152 const struct adv76xx_format_info *format;
153
154 struct {
155 u8 edid[256];
156 u32 present;
157 unsigned blocks;
158 } edid;
159 u16 spa_port_a[2];
160 struct v4l2_fract aspect_ratio;
161 u32 rgb_quantization_range;
162 struct workqueue_struct *work_queues;
163 struct delayed_work delayed_work_enable_hotplug;
164 bool restart_stdi_once;
165
166 /* i2c clients */
167 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
168
169 /* controls */
170 struct v4l2_ctrl *detect_tx_5v_ctrl;
171 struct v4l2_ctrl *analog_sampling_phase_ctrl;
172 struct v4l2_ctrl *free_run_color_manual_ctrl;
173 struct v4l2_ctrl *free_run_color_ctrl;
174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
175 };
176
adv76xx_has_afe(struct adv76xx_state * state)177 static bool adv76xx_has_afe(struct adv76xx_state *state)
178 {
179 return state->info->has_afe;
180 }
181
182 /* Supported CEA and DMT timings */
183 static const struct v4l2_dv_timings adv76xx_timings[] = {
184 V4L2_DV_BT_CEA_720X480P59_94,
185 V4L2_DV_BT_CEA_720X576P50,
186 V4L2_DV_BT_CEA_1280X720P24,
187 V4L2_DV_BT_CEA_1280X720P25,
188 V4L2_DV_BT_CEA_1280X720P50,
189 V4L2_DV_BT_CEA_1280X720P60,
190 V4L2_DV_BT_CEA_1920X1080P24,
191 V4L2_DV_BT_CEA_1920X1080P25,
192 V4L2_DV_BT_CEA_1920X1080P30,
193 V4L2_DV_BT_CEA_1920X1080P50,
194 V4L2_DV_BT_CEA_1920X1080P60,
195
196 /* sorted by DMT ID */
197 V4L2_DV_BT_DMT_640X350P85,
198 V4L2_DV_BT_DMT_640X400P85,
199 V4L2_DV_BT_DMT_720X400P85,
200 V4L2_DV_BT_DMT_640X480P60,
201 V4L2_DV_BT_DMT_640X480P72,
202 V4L2_DV_BT_DMT_640X480P75,
203 V4L2_DV_BT_DMT_640X480P85,
204 V4L2_DV_BT_DMT_800X600P56,
205 V4L2_DV_BT_DMT_800X600P60,
206 V4L2_DV_BT_DMT_800X600P72,
207 V4L2_DV_BT_DMT_800X600P75,
208 V4L2_DV_BT_DMT_800X600P85,
209 V4L2_DV_BT_DMT_848X480P60,
210 V4L2_DV_BT_DMT_1024X768P60,
211 V4L2_DV_BT_DMT_1024X768P70,
212 V4L2_DV_BT_DMT_1024X768P75,
213 V4L2_DV_BT_DMT_1024X768P85,
214 V4L2_DV_BT_DMT_1152X864P75,
215 V4L2_DV_BT_DMT_1280X768P60_RB,
216 V4L2_DV_BT_DMT_1280X768P60,
217 V4L2_DV_BT_DMT_1280X768P75,
218 V4L2_DV_BT_DMT_1280X768P85,
219 V4L2_DV_BT_DMT_1280X800P60_RB,
220 V4L2_DV_BT_DMT_1280X800P60,
221 V4L2_DV_BT_DMT_1280X800P75,
222 V4L2_DV_BT_DMT_1280X800P85,
223 V4L2_DV_BT_DMT_1280X960P60,
224 V4L2_DV_BT_DMT_1280X960P85,
225 V4L2_DV_BT_DMT_1280X1024P60,
226 V4L2_DV_BT_DMT_1280X1024P75,
227 V4L2_DV_BT_DMT_1280X1024P85,
228 V4L2_DV_BT_DMT_1360X768P60,
229 V4L2_DV_BT_DMT_1400X1050P60_RB,
230 V4L2_DV_BT_DMT_1400X1050P60,
231 V4L2_DV_BT_DMT_1400X1050P75,
232 V4L2_DV_BT_DMT_1400X1050P85,
233 V4L2_DV_BT_DMT_1440X900P60_RB,
234 V4L2_DV_BT_DMT_1440X900P60,
235 V4L2_DV_BT_DMT_1600X1200P60,
236 V4L2_DV_BT_DMT_1680X1050P60_RB,
237 V4L2_DV_BT_DMT_1680X1050P60,
238 V4L2_DV_BT_DMT_1792X1344P60,
239 V4L2_DV_BT_DMT_1856X1392P60,
240 V4L2_DV_BT_DMT_1920X1200P60_RB,
241 V4L2_DV_BT_DMT_1366X768P60_RB,
242 V4L2_DV_BT_DMT_1366X768P60,
243 V4L2_DV_BT_DMT_1920X1080P60,
244 { },
245 };
246
247 struct adv76xx_video_standards {
248 struct v4l2_dv_timings timings;
249 u8 vid_std;
250 u8 v_freq;
251 };
252
253 /* sorted by number of lines */
254 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
258 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
259 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
260 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
261 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
262 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
263 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
264 /* TODO add 1920x1080P60_RB (CVT timing) */
265 { },
266 };
267
268 /* sorted by number of lines */
269 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
273 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
278 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
282 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
284 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
285 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
286 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
288 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
289 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
290 /* TODO add 1600X1200P60_RB (not a DMT timing) */
291 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
292 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
293 { },
294 };
295
296 /* sorted by number of lines */
297 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
301 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
302 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
303 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
304 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
305 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
306 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
307 { },
308 };
309
310 /* sorted by number of lines */
311 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
315 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
320 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
324 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
326 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
327 { },
328 };
329
330 /* ----------------------------------------------------------------------- */
331
to_state(struct v4l2_subdev * sd)332 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
333 {
334 return container_of(sd, struct adv76xx_state, sd);
335 }
336
htotal(const struct v4l2_bt_timings * t)337 static inline unsigned htotal(const struct v4l2_bt_timings *t)
338 {
339 return V4L2_DV_BT_FRAME_WIDTH(t);
340 }
341
vtotal(const struct v4l2_bt_timings * t)342 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
343 {
344 return V4L2_DV_BT_FRAME_HEIGHT(t);
345 }
346
347 /* ----------------------------------------------------------------------- */
348
adv_smbus_read_byte_data_check(struct i2c_client * client,u8 command,bool check)349 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
350 u8 command, bool check)
351 {
352 union i2c_smbus_data data;
353
354 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
355 I2C_SMBUS_READ, command,
356 I2C_SMBUS_BYTE_DATA, &data))
357 return data.byte;
358 if (check)
359 v4l_err(client, "error reading %02x, %02x\n",
360 client->addr, command);
361 return -EIO;
362 }
363
adv_smbus_read_byte_data(struct adv76xx_state * state,enum adv76xx_page page,u8 command)364 static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
365 enum adv76xx_page page, u8 command)
366 {
367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
368 command, true);
369 }
370
adv_smbus_write_byte_data(struct adv76xx_state * state,enum adv76xx_page page,u8 command,u8 value)371 static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
372 enum adv76xx_page page, u8 command,
373 u8 value)
374 {
375 struct i2c_client *client = state->i2c_clients[page];
376 union i2c_smbus_data data;
377 int err;
378 int i;
379
380 data.byte = value;
381 for (i = 0; i < 3; i++) {
382 err = i2c_smbus_xfer(client->adapter, client->addr,
383 client->flags,
384 I2C_SMBUS_WRITE, command,
385 I2C_SMBUS_BYTE_DATA, &data);
386 if (!err)
387 break;
388 }
389 if (err < 0)
390 v4l_err(client, "error writing %02x, %02x, %02x\n",
391 client->addr, command, value);
392 return err;
393 }
394
adv_smbus_write_i2c_block_data(struct adv76xx_state * state,enum adv76xx_page page,u8 command,unsigned length,const u8 * values)395 static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
396 enum adv76xx_page page, u8 command,
397 unsigned length, const u8 *values)
398 {
399 struct i2c_client *client = state->i2c_clients[page];
400 union i2c_smbus_data data;
401
402 if (length > I2C_SMBUS_BLOCK_MAX)
403 length = I2C_SMBUS_BLOCK_MAX;
404 data.block[0] = length;
405 memcpy(data.block + 1, values, length);
406 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
407 I2C_SMBUS_WRITE, command,
408 I2C_SMBUS_I2C_BLOCK_DATA, &data);
409 }
410
411 /* ----------------------------------------------------------------------- */
412
io_read(struct v4l2_subdev * sd,u8 reg)413 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
414 {
415 struct adv76xx_state *state = to_state(sd);
416
417 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
418 }
419
io_write(struct v4l2_subdev * sd,u8 reg,u8 val)420 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421 {
422 struct adv76xx_state *state = to_state(sd);
423
424 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
425 }
426
io_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)427 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
428 {
429 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
430 }
431
avlink_read(struct v4l2_subdev * sd,u8 reg)432 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
433 {
434 struct adv76xx_state *state = to_state(sd);
435
436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
437 }
438
avlink_write(struct v4l2_subdev * sd,u8 reg,u8 val)439 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440 {
441 struct adv76xx_state *state = to_state(sd);
442
443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
444 }
445
cec_read(struct v4l2_subdev * sd,u8 reg)446 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
447 {
448 struct adv76xx_state *state = to_state(sd);
449
450 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
451 }
452
cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)453 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454 {
455 struct adv76xx_state *state = to_state(sd);
456
457 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
458 }
459
infoframe_read(struct v4l2_subdev * sd,u8 reg)460 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
461 {
462 struct adv76xx_state *state = to_state(sd);
463
464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
465 }
466
infoframe_write(struct v4l2_subdev * sd,u8 reg,u8 val)467 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468 {
469 struct adv76xx_state *state = to_state(sd);
470
471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
472 reg, val);
473 }
474
afe_read(struct v4l2_subdev * sd,u8 reg)475 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
476 {
477 struct adv76xx_state *state = to_state(sd);
478
479 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
480 }
481
afe_write(struct v4l2_subdev * sd,u8 reg,u8 val)482 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483 {
484 struct adv76xx_state *state = to_state(sd);
485
486 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
487 }
488
rep_read(struct v4l2_subdev * sd,u8 reg)489 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
490 {
491 struct adv76xx_state *state = to_state(sd);
492
493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
494 }
495
rep_write(struct v4l2_subdev * sd,u8 reg,u8 val)496 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497 {
498 struct adv76xx_state *state = to_state(sd);
499
500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
501 }
502
rep_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)503 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
504 {
505 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
506 }
507
edid_read(struct v4l2_subdev * sd,u8 reg)508 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
509 {
510 struct adv76xx_state *state = to_state(sd);
511
512 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
513 }
514
edid_write(struct v4l2_subdev * sd,u8 reg,u8 val)515 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
516 {
517 struct adv76xx_state *state = to_state(sd);
518
519 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
520 }
521
edid_write_block(struct v4l2_subdev * sd,unsigned len,const u8 * val)522 static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val)
524 {
525 struct adv76xx_state *state = to_state(sd);
526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
532 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
533 i, I2C_SMBUS_BLOCK_MAX, val + i);
534 return err;
535 }
536
adv76xx_set_hpd(struct adv76xx_state * state,unsigned int hpd)537 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
538 {
539 unsigned int i;
540
541 for (i = 0; i < state->info->num_dv_ports; ++i)
542 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
543
544 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
545 }
546
adv76xx_delayed_work_enable_hotplug(struct work_struct * work)547 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
548 {
549 struct delayed_work *dwork = to_delayed_work(work);
550 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
551 delayed_work_enable_hotplug);
552 struct v4l2_subdev *sd = &state->sd;
553
554 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
555
556 adv76xx_set_hpd(state, state->edid.present);
557 }
558
hdmi_read(struct v4l2_subdev * sd,u8 reg)559 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
560 {
561 struct adv76xx_state *state = to_state(sd);
562
563 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
564 }
565
hdmi_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)566 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
567 {
568 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
569 }
570
hdmi_write(struct v4l2_subdev * sd,u8 reg,u8 val)571 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
572 {
573 struct adv76xx_state *state = to_state(sd);
574
575 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
576 }
577
hdmi_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)578 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
579 {
580 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
581 }
582
test_write(struct v4l2_subdev * sd,u8 reg,u8 val)583 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584 {
585 struct adv76xx_state *state = to_state(sd);
586
587 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
588 }
589
cp_read(struct v4l2_subdev * sd,u8 reg)590 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
591 {
592 struct adv76xx_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
595 }
596
cp_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)597 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
598 {
599 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
600 }
601
cp_write(struct v4l2_subdev * sd,u8 reg,u8 val)602 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
603 {
604 struct adv76xx_state *state = to_state(sd);
605
606 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
607 }
608
cp_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)609 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
610 {
611 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
612 }
613
vdp_read(struct v4l2_subdev * sd,u8 reg)614 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
615 {
616 struct adv76xx_state *state = to_state(sd);
617
618 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
619 }
620
vdp_write(struct v4l2_subdev * sd,u8 reg,u8 val)621 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
622 {
623 struct adv76xx_state *state = to_state(sd);
624
625 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
626 }
627
628 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
629 #define ADV76XX_REG_SEQ_TERM 0xffff
630
631 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_read_reg(struct v4l2_subdev * sd,unsigned int reg)632 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
633 {
634 struct adv76xx_state *state = to_state(sd);
635 unsigned int page = reg >> 8;
636
637 if (!(BIT(page) & state->info->page_mask))
638 return -EINVAL;
639
640 reg &= 0xff;
641
642 return adv_smbus_read_byte_data(state, page, reg);
643 }
644 #endif
645
adv76xx_write_reg(struct v4l2_subdev * sd,unsigned int reg,u8 val)646 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
647 {
648 struct adv76xx_state *state = to_state(sd);
649 unsigned int page = reg >> 8;
650
651 if (!(BIT(page) & state->info->page_mask))
652 return -EINVAL;
653
654 reg &= 0xff;
655
656 return adv_smbus_write_byte_data(state, page, reg, val);
657 }
658
adv76xx_write_reg_seq(struct v4l2_subdev * sd,const struct adv76xx_reg_seq * reg_seq)659 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
660 const struct adv76xx_reg_seq *reg_seq)
661 {
662 unsigned int i;
663
664 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
665 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
666 }
667
668 /* -----------------------------------------------------------------------------
669 * Format helpers
670 */
671
672 static const struct adv76xx_format_info adv7604_formats[] = {
673 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
674 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
675 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
677 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
679 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
681 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
683 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
685 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
687 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
689 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
691 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
695 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
697 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
699 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
701 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
703 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
705 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
707 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
709 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
711 };
712
713 static const struct adv76xx_format_info adv7611_formats[] = {
714 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
715 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
718 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
720 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
724 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
726 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
728 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
730 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
732 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
734 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
736 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
737 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
738 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
740 };
741
742 static const struct adv76xx_format_info *
adv76xx_format_info(struct adv76xx_state * state,u32 code)743 adv76xx_format_info(struct adv76xx_state *state, u32 code)
744 {
745 unsigned int i;
746
747 for (i = 0; i < state->info->nformats; ++i) {
748 if (state->info->formats[i].code == code)
749 return &state->info->formats[i];
750 }
751
752 return NULL;
753 }
754
755 /* ----------------------------------------------------------------------- */
756
is_analog_input(struct v4l2_subdev * sd)757 static inline bool is_analog_input(struct v4l2_subdev *sd)
758 {
759 struct adv76xx_state *state = to_state(sd);
760
761 return state->selected_input == ADV7604_PAD_VGA_RGB ||
762 state->selected_input == ADV7604_PAD_VGA_COMP;
763 }
764
is_digital_input(struct v4l2_subdev * sd)765 static inline bool is_digital_input(struct v4l2_subdev *sd)
766 {
767 struct adv76xx_state *state = to_state(sd);
768
769 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
770 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
771 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
772 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
773 }
774
775 /* ----------------------------------------------------------------------- */
776
777 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_inv_register(struct v4l2_subdev * sd)778 static void adv76xx_inv_register(struct v4l2_subdev *sd)
779 {
780 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
781 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
782 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
783 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
784 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
785 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
786 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
787 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
788 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
789 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
790 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
791 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
792 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
793 }
794
adv76xx_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)795 static int adv76xx_g_register(struct v4l2_subdev *sd,
796 struct v4l2_dbg_register *reg)
797 {
798 int ret;
799
800 ret = adv76xx_read_reg(sd, reg->reg);
801 if (ret < 0) {
802 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
803 adv76xx_inv_register(sd);
804 return ret;
805 }
806
807 reg->size = 1;
808 reg->val = ret;
809
810 return 0;
811 }
812
adv76xx_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)813 static int adv76xx_s_register(struct v4l2_subdev *sd,
814 const struct v4l2_dbg_register *reg)
815 {
816 int ret;
817
818 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
819 if (ret < 0) {
820 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
821 adv76xx_inv_register(sd);
822 return ret;
823 }
824
825 return 0;
826 }
827 #endif
828
adv7604_read_cable_det(struct v4l2_subdev * sd)829 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
830 {
831 u8 value = io_read(sd, 0x6f);
832
833 return ((value & 0x10) >> 4)
834 | ((value & 0x08) >> 2)
835 | ((value & 0x04) << 0)
836 | ((value & 0x02) << 2);
837 }
838
adv7611_read_cable_det(struct v4l2_subdev * sd)839 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
840 {
841 u8 value = io_read(sd, 0x6f);
842
843 return value & 1;
844 }
845
adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev * sd)846 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
847 {
848 struct adv76xx_state *state = to_state(sd);
849 const struct adv76xx_chip_info *info = state->info;
850
851 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
852 info->read_cable_det(sd));
853 }
854
find_and_set_predefined_video_timings(struct v4l2_subdev * sd,u8 prim_mode,const struct adv76xx_video_standards * predef_vid_timings,const struct v4l2_dv_timings * timings)855 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
856 u8 prim_mode,
857 const struct adv76xx_video_standards *predef_vid_timings,
858 const struct v4l2_dv_timings *timings)
859 {
860 int i;
861
862 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
863 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
864 is_digital_input(sd) ? 250000 : 1000000))
865 continue;
866 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
867 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
868 prim_mode); /* v_freq and prim mode */
869 return 0;
870 }
871
872 return -1;
873 }
874
configure_predefined_video_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)875 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
876 struct v4l2_dv_timings *timings)
877 {
878 struct adv76xx_state *state = to_state(sd);
879 int err;
880
881 v4l2_dbg(1, debug, sd, "%s", __func__);
882
883 if (adv76xx_has_afe(state)) {
884 /* reset to default values */
885 io_write(sd, 0x16, 0x43);
886 io_write(sd, 0x17, 0x5a);
887 }
888 /* disable embedded syncs for auto graphics mode */
889 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
890 cp_write(sd, 0x8f, 0x00);
891 cp_write(sd, 0x90, 0x00);
892 cp_write(sd, 0xa2, 0x00);
893 cp_write(sd, 0xa3, 0x00);
894 cp_write(sd, 0xa4, 0x00);
895 cp_write(sd, 0xa5, 0x00);
896 cp_write(sd, 0xa6, 0x00);
897 cp_write(sd, 0xa7, 0x00);
898 cp_write(sd, 0xab, 0x00);
899 cp_write(sd, 0xac, 0x00);
900
901 if (is_analog_input(sd)) {
902 err = find_and_set_predefined_video_timings(sd,
903 0x01, adv7604_prim_mode_comp, timings);
904 if (err)
905 err = find_and_set_predefined_video_timings(sd,
906 0x02, adv7604_prim_mode_gr, timings);
907 } else if (is_digital_input(sd)) {
908 err = find_and_set_predefined_video_timings(sd,
909 0x05, adv76xx_prim_mode_hdmi_comp, timings);
910 if (err)
911 err = find_and_set_predefined_video_timings(sd,
912 0x06, adv76xx_prim_mode_hdmi_gr, timings);
913 } else {
914 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
915 __func__, state->selected_input);
916 err = -1;
917 }
918
919
920 return err;
921 }
922
configure_custom_video_timings(struct v4l2_subdev * sd,const struct v4l2_bt_timings * bt)923 static void configure_custom_video_timings(struct v4l2_subdev *sd,
924 const struct v4l2_bt_timings *bt)
925 {
926 struct adv76xx_state *state = to_state(sd);
927 u32 width = htotal(bt);
928 u32 height = vtotal(bt);
929 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
930 u16 cp_start_eav = width - bt->hfrontporch;
931 u16 cp_start_vbi = height - bt->vfrontporch;
932 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
933 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
934 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
935 const u8 pll[2] = {
936 0xc0 | ((width >> 8) & 0x1f),
937 width & 0xff
938 };
939
940 v4l2_dbg(2, debug, sd, "%s\n", __func__);
941
942 if (is_analog_input(sd)) {
943 /* auto graphics */
944 io_write(sd, 0x00, 0x07); /* video std */
945 io_write(sd, 0x01, 0x02); /* prim mode */
946 /* enable embedded syncs for auto graphics mode */
947 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
948
949 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
950 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
951 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
952 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
953 0x16, 2, pll))
954 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
955
956 /* active video - horizontal timing */
957 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
958 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
959 ((cp_start_eav >> 8) & 0x0f));
960 cp_write(sd, 0xa4, cp_start_eav & 0xff);
961
962 /* active video - vertical timing */
963 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
964 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
965 ((cp_end_vbi >> 8) & 0xf));
966 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
967 } else if (is_digital_input(sd)) {
968 /* set default prim_mode/vid_std for HDMI
969 according to [REF_03, c. 4.2] */
970 io_write(sd, 0x00, 0x02); /* video std */
971 io_write(sd, 0x01, 0x06); /* prim mode */
972 } else {
973 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
974 __func__, state->selected_input);
975 }
976
977 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
978 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
979 cp_write(sd, 0xab, (height >> 4) & 0xff);
980 cp_write(sd, 0xac, (height & 0x0f) << 4);
981 }
982
adv76xx_set_offset(struct v4l2_subdev * sd,bool auto_offset,u16 offset_a,u16 offset_b,u16 offset_c)983 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
984 {
985 struct adv76xx_state *state = to_state(sd);
986 u8 offset_buf[4];
987
988 if (auto_offset) {
989 offset_a = 0x3ff;
990 offset_b = 0x3ff;
991 offset_c = 0x3ff;
992 }
993
994 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
995 __func__, auto_offset ? "Auto" : "Manual",
996 offset_a, offset_b, offset_c);
997
998 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
999 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1000 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1001 offset_buf[3] = offset_c & 0x0ff;
1002
1003 /* Registers must be written in this order with no i2c access in between */
1004 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1005 0x77, 4, offset_buf))
1006 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1007 }
1008
adv76xx_set_gain(struct v4l2_subdev * sd,bool auto_gain,u16 gain_a,u16 gain_b,u16 gain_c)1009 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1010 {
1011 struct adv76xx_state *state = to_state(sd);
1012 u8 gain_buf[4];
1013 u8 gain_man = 1;
1014 u8 agc_mode_man = 1;
1015
1016 if (auto_gain) {
1017 gain_man = 0;
1018 agc_mode_man = 0;
1019 gain_a = 0x100;
1020 gain_b = 0x100;
1021 gain_c = 0x100;
1022 }
1023
1024 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1025 __func__, auto_gain ? "Auto" : "Manual",
1026 gain_a, gain_b, gain_c);
1027
1028 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1029 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1030 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1031 gain_buf[3] = ((gain_c & 0x0ff));
1032
1033 /* Registers must be written in this order with no i2c access in between */
1034 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1035 0x73, 4, gain_buf))
1036 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1037 }
1038
set_rgb_quantization_range(struct v4l2_subdev * sd)1039 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1040 {
1041 struct adv76xx_state *state = to_state(sd);
1042 bool rgb_output = io_read(sd, 0x02) & 0x02;
1043 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1044
1045 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1046 __func__, state->rgb_quantization_range,
1047 rgb_output, hdmi_signal);
1048
1049 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1050 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1051
1052 switch (state->rgb_quantization_range) {
1053 case V4L2_DV_RGB_RANGE_AUTO:
1054 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1055 /* Receiving analog RGB signal
1056 * Set RGB full range (0-255) */
1057 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1058 break;
1059 }
1060
1061 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1062 /* Receiving analog YPbPr signal
1063 * Set automode */
1064 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1065 break;
1066 }
1067
1068 if (hdmi_signal) {
1069 /* Receiving HDMI signal
1070 * Set automode */
1071 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1072 break;
1073 }
1074
1075 /* Receiving DVI-D signal
1076 * ADV7604 selects RGB limited range regardless of
1077 * input format (CE/IT) in automatic mode */
1078 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1079 /* RGB limited range (16-235) */
1080 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1081 } else {
1082 /* RGB full range (0-255) */
1083 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1084
1085 if (is_digital_input(sd) && rgb_output) {
1086 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1087 } else {
1088 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1089 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1090 }
1091 }
1092 break;
1093 case V4L2_DV_RGB_RANGE_LIMITED:
1094 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1095 /* YCrCb limited range (16-235) */
1096 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1097 break;
1098 }
1099
1100 /* RGB limited range (16-235) */
1101 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1102
1103 break;
1104 case V4L2_DV_RGB_RANGE_FULL:
1105 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1106 /* YCrCb full range (0-255) */
1107 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1108 break;
1109 }
1110
1111 /* RGB full range (0-255) */
1112 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1113
1114 if (is_analog_input(sd) || hdmi_signal)
1115 break;
1116
1117 /* Adjust gain/offset for DVI-D signals only */
1118 if (rgb_output) {
1119 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1120 } else {
1121 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1122 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1123 }
1124 break;
1125 }
1126 }
1127
adv76xx_s_ctrl(struct v4l2_ctrl * ctrl)1128 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1129 {
1130 struct v4l2_subdev *sd =
1131 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1132
1133 struct adv76xx_state *state = to_state(sd);
1134
1135 switch (ctrl->id) {
1136 case V4L2_CID_BRIGHTNESS:
1137 cp_write(sd, 0x3c, ctrl->val);
1138 return 0;
1139 case V4L2_CID_CONTRAST:
1140 cp_write(sd, 0x3a, ctrl->val);
1141 return 0;
1142 case V4L2_CID_SATURATION:
1143 cp_write(sd, 0x3b, ctrl->val);
1144 return 0;
1145 case V4L2_CID_HUE:
1146 cp_write(sd, 0x3d, ctrl->val);
1147 return 0;
1148 case V4L2_CID_DV_RX_RGB_RANGE:
1149 state->rgb_quantization_range = ctrl->val;
1150 set_rgb_quantization_range(sd);
1151 return 0;
1152 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1153 if (!adv76xx_has_afe(state))
1154 return -EINVAL;
1155 /* Set the analog sampling phase. This is needed to find the
1156 best sampling phase for analog video: an application or
1157 driver has to try a number of phases and analyze the picture
1158 quality before settling on the best performing phase. */
1159 afe_write(sd, 0xc8, ctrl->val);
1160 return 0;
1161 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1162 /* Use the default blue color for free running mode,
1163 or supply your own. */
1164 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1165 return 0;
1166 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1167 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1168 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1169 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1170 return 0;
1171 }
1172 return -EINVAL;
1173 }
1174
1175 /* ----------------------------------------------------------------------- */
1176
no_power(struct v4l2_subdev * sd)1177 static inline bool no_power(struct v4l2_subdev *sd)
1178 {
1179 /* Entire chip or CP powered off */
1180 return io_read(sd, 0x0c) & 0x24;
1181 }
1182
no_signal_tmds(struct v4l2_subdev * sd)1183 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1184 {
1185 struct adv76xx_state *state = to_state(sd);
1186
1187 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1188 }
1189
no_lock_tmds(struct v4l2_subdev * sd)1190 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1191 {
1192 struct adv76xx_state *state = to_state(sd);
1193 const struct adv76xx_chip_info *info = state->info;
1194
1195 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1196 }
1197
is_hdmi(struct v4l2_subdev * sd)1198 static inline bool is_hdmi(struct v4l2_subdev *sd)
1199 {
1200 return hdmi_read(sd, 0x05) & 0x80;
1201 }
1202
no_lock_sspd(struct v4l2_subdev * sd)1203 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1204 {
1205 struct adv76xx_state *state = to_state(sd);
1206
1207 /*
1208 * Chips without a AFE don't expose registers for the SSPD, so just assume
1209 * that we have a lock.
1210 */
1211 if (adv76xx_has_afe(state))
1212 return false;
1213
1214 /* TODO channel 2 */
1215 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1216 }
1217
no_lock_stdi(struct v4l2_subdev * sd)1218 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1219 {
1220 /* TODO channel 2 */
1221 return !(cp_read(sd, 0xb1) & 0x80);
1222 }
1223
no_signal(struct v4l2_subdev * sd)1224 static inline bool no_signal(struct v4l2_subdev *sd)
1225 {
1226 bool ret;
1227
1228 ret = no_power(sd);
1229
1230 ret |= no_lock_stdi(sd);
1231 ret |= no_lock_sspd(sd);
1232
1233 if (is_digital_input(sd)) {
1234 ret |= no_lock_tmds(sd);
1235 ret |= no_signal_tmds(sd);
1236 }
1237
1238 return ret;
1239 }
1240
no_lock_cp(struct v4l2_subdev * sd)1241 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1242 {
1243 struct adv76xx_state *state = to_state(sd);
1244
1245 if (!adv76xx_has_afe(state))
1246 return false;
1247
1248 /* CP has detected a non standard number of lines on the incoming
1249 video compared to what it is configured to receive by s_dv_timings */
1250 return io_read(sd, 0x12) & 0x01;
1251 }
1252
in_free_run(struct v4l2_subdev * sd)1253 static inline bool in_free_run(struct v4l2_subdev *sd)
1254 {
1255 return cp_read(sd, 0xff) & 0x10;
1256 }
1257
adv76xx_g_input_status(struct v4l2_subdev * sd,u32 * status)1258 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1259 {
1260 *status = 0;
1261 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1262 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1263 if (!in_free_run(sd) && no_lock_cp(sd))
1264 *status |= is_digital_input(sd) ?
1265 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1266
1267 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1268
1269 return 0;
1270 }
1271
1272 /* ----------------------------------------------------------------------- */
1273
1274 struct stdi_readback {
1275 u16 bl, lcf, lcvs;
1276 u8 hs_pol, vs_pol;
1277 bool interlaced;
1278 };
1279
stdi2dv_timings(struct v4l2_subdev * sd,struct stdi_readback * stdi,struct v4l2_dv_timings * timings)1280 static int stdi2dv_timings(struct v4l2_subdev *sd,
1281 struct stdi_readback *stdi,
1282 struct v4l2_dv_timings *timings)
1283 {
1284 struct adv76xx_state *state = to_state(sd);
1285 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1286 u32 pix_clk;
1287 int i;
1288
1289 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1290 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
1291 continue;
1292 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
1293 continue;
1294
1295 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
1296
1297 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1298 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1299 *timings = adv76xx_timings[i];
1300 return 0;
1301 }
1302 }
1303
1304 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1305 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1306 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1307 timings))
1308 return 0;
1309 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1310 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1311 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1312 state->aspect_ratio, timings))
1313 return 0;
1314
1315 v4l2_dbg(2, debug, sd,
1316 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1317 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1318 stdi->hs_pol, stdi->vs_pol);
1319 return -1;
1320 }
1321
1322
read_stdi(struct v4l2_subdev * sd,struct stdi_readback * stdi)1323 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1324 {
1325 struct adv76xx_state *state = to_state(sd);
1326 const struct adv76xx_chip_info *info = state->info;
1327 u8 polarity;
1328
1329 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1330 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1331 return -1;
1332 }
1333
1334 /* read STDI */
1335 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1336 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1337 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1338 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1339
1340 if (adv76xx_has_afe(state)) {
1341 /* read SSPD */
1342 polarity = cp_read(sd, 0xb5);
1343 if ((polarity & 0x03) == 0x01) {
1344 stdi->hs_pol = polarity & 0x10
1345 ? (polarity & 0x08 ? '+' : '-') : 'x';
1346 stdi->vs_pol = polarity & 0x40
1347 ? (polarity & 0x20 ? '+' : '-') : 'x';
1348 } else {
1349 stdi->hs_pol = 'x';
1350 stdi->vs_pol = 'x';
1351 }
1352 } else {
1353 polarity = hdmi_read(sd, 0x05);
1354 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1355 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1356 }
1357
1358 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1359 v4l2_dbg(2, debug, sd,
1360 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1361 return -1;
1362 }
1363
1364 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1365 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1366 memset(stdi, 0, sizeof(struct stdi_readback));
1367 return -1;
1368 }
1369
1370 v4l2_dbg(2, debug, sd,
1371 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1372 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1373 stdi->hs_pol, stdi->vs_pol,
1374 stdi->interlaced ? "interlaced" : "progressive");
1375
1376 return 0;
1377 }
1378
adv76xx_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1379 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1380 struct v4l2_enum_dv_timings *timings)
1381 {
1382 struct adv76xx_state *state = to_state(sd);
1383
1384 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
1385 return -EINVAL;
1386
1387 if (timings->pad >= state->source_pad)
1388 return -EINVAL;
1389
1390 memset(timings->reserved, 0, sizeof(timings->reserved));
1391 timings->timings = adv76xx_timings[timings->index];
1392 return 0;
1393 }
1394
adv76xx_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1395 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1396 struct v4l2_dv_timings_cap *cap)
1397 {
1398 struct adv76xx_state *state = to_state(sd);
1399
1400 if (cap->pad >= state->source_pad)
1401 return -EINVAL;
1402
1403 cap->type = V4L2_DV_BT_656_1120;
1404 cap->bt.max_width = 1920;
1405 cap->bt.max_height = 1200;
1406 cap->bt.min_pixelclock = 25000000;
1407
1408 switch (cap->pad) {
1409 case ADV76XX_PAD_HDMI_PORT_A:
1410 case ADV7604_PAD_HDMI_PORT_B:
1411 case ADV7604_PAD_HDMI_PORT_C:
1412 case ADV7604_PAD_HDMI_PORT_D:
1413 cap->bt.max_pixelclock = 225000000;
1414 break;
1415 case ADV7604_PAD_VGA_RGB:
1416 case ADV7604_PAD_VGA_COMP:
1417 default:
1418 cap->bt.max_pixelclock = 170000000;
1419 break;
1420 }
1421
1422 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1423 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1424 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1425 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1426 return 0;
1427 }
1428
1429 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1430 if the format is listed in adv76xx_timings[] */
adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1431 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1432 struct v4l2_dv_timings *timings)
1433 {
1434 int i;
1435
1436 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1437 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
1438 is_digital_input(sd) ? 250000 : 1000000)) {
1439 *timings = adv76xx_timings[i];
1440 break;
1441 }
1442 }
1443 }
1444
adv7604_read_hdmi_pixelclock(struct v4l2_subdev * sd)1445 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1446 {
1447 unsigned int freq;
1448 int a, b;
1449
1450 a = hdmi_read(sd, 0x06);
1451 b = hdmi_read(sd, 0x3b);
1452 if (a < 0 || b < 0)
1453 return 0;
1454 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1455
1456 if (is_hdmi(sd)) {
1457 /* adjust for deep color mode */
1458 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1459
1460 freq = freq * 8 / bits_per_channel;
1461 }
1462
1463 return freq;
1464 }
1465
adv7611_read_hdmi_pixelclock(struct v4l2_subdev * sd)1466 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1467 {
1468 int a, b;
1469
1470 a = hdmi_read(sd, 0x51);
1471 b = hdmi_read(sd, 0x52);
1472 if (a < 0 || b < 0)
1473 return 0;
1474 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1475 }
1476
adv76xx_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1477 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1478 struct v4l2_dv_timings *timings)
1479 {
1480 struct adv76xx_state *state = to_state(sd);
1481 const struct adv76xx_chip_info *info = state->info;
1482 struct v4l2_bt_timings *bt = &timings->bt;
1483 struct stdi_readback stdi;
1484
1485 if (!timings)
1486 return -EINVAL;
1487
1488 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1489
1490 if (no_signal(sd)) {
1491 state->restart_stdi_once = true;
1492 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1493 return -ENOLINK;
1494 }
1495
1496 /* read STDI */
1497 if (read_stdi(sd, &stdi)) {
1498 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1499 return -ENOLINK;
1500 }
1501 bt->interlaced = stdi.interlaced ?
1502 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1503
1504 if (is_digital_input(sd)) {
1505 timings->type = V4L2_DV_BT_656_1120;
1506
1507 /* FIXME: All masks are incorrect for ADV7611 */
1508 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1509 bt->height = hdmi_read16(sd, 0x09, 0xfff);
1510 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1511 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1512 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1513 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1514 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1515 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1516 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
1517 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1518 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1519 if (bt->interlaced == V4L2_DV_INTERLACED) {
1520 bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1521 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1522 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1523 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1524 }
1525 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1526 } else {
1527 /* find format
1528 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1529 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1530 */
1531 if (!stdi2dv_timings(sd, &stdi, timings))
1532 goto found;
1533 stdi.lcvs += 1;
1534 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1535 if (!stdi2dv_timings(sd, &stdi, timings))
1536 goto found;
1537 stdi.lcvs -= 2;
1538 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1539 if (stdi2dv_timings(sd, &stdi, timings)) {
1540 /*
1541 * The STDI block may measure wrong values, especially
1542 * for lcvs and lcf. If the driver can not find any
1543 * valid timing, the STDI block is restarted to measure
1544 * the video timings again. The function will return an
1545 * error, but the restart of STDI will generate a new
1546 * STDI interrupt and the format detection process will
1547 * restart.
1548 */
1549 if (state->restart_stdi_once) {
1550 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1551 /* TODO restart STDI for Sync Channel 2 */
1552 /* enter one-shot mode */
1553 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1554 /* trigger STDI restart */
1555 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1556 /* reset to continuous mode */
1557 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1558 state->restart_stdi_once = false;
1559 return -ENOLINK;
1560 }
1561 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1562 return -ERANGE;
1563 }
1564 state->restart_stdi_once = true;
1565 }
1566 found:
1567
1568 if (no_signal(sd)) {
1569 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1570 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1571 return -ENOLINK;
1572 }
1573
1574 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1575 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1576 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1577 __func__, (u32)bt->pixelclock);
1578 return -ERANGE;
1579 }
1580
1581 if (debug > 1)
1582 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1583 timings, true);
1584
1585 return 0;
1586 }
1587
adv76xx_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1588 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1589 struct v4l2_dv_timings *timings)
1590 {
1591 struct adv76xx_state *state = to_state(sd);
1592 struct v4l2_bt_timings *bt;
1593 int err;
1594
1595 if (!timings)
1596 return -EINVAL;
1597
1598 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1599 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1600 return 0;
1601 }
1602
1603 bt = &timings->bt;
1604
1605 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1606 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1607 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1608 __func__, (u32)bt->pixelclock);
1609 return -ERANGE;
1610 }
1611
1612 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1613
1614 state->timings = *timings;
1615
1616 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1617
1618 /* Use prim_mode and vid_std when available */
1619 err = configure_predefined_video_timings(sd, timings);
1620 if (err) {
1621 /* custom settings when the video format
1622 does not have prim_mode/vid_std */
1623 configure_custom_video_timings(sd, bt);
1624 }
1625
1626 set_rgb_quantization_range(sd);
1627
1628 if (debug > 1)
1629 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1630 timings, true);
1631 return 0;
1632 }
1633
adv76xx_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1634 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1635 struct v4l2_dv_timings *timings)
1636 {
1637 struct adv76xx_state *state = to_state(sd);
1638
1639 *timings = state->timings;
1640 return 0;
1641 }
1642
adv7604_set_termination(struct v4l2_subdev * sd,bool enable)1643 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1644 {
1645 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1646 }
1647
adv7611_set_termination(struct v4l2_subdev * sd,bool enable)1648 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1649 {
1650 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1651 }
1652
enable_input(struct v4l2_subdev * sd)1653 static void enable_input(struct v4l2_subdev *sd)
1654 {
1655 struct adv76xx_state *state = to_state(sd);
1656
1657 if (is_analog_input(sd)) {
1658 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1659 } else if (is_digital_input(sd)) {
1660 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1661 state->info->set_termination(sd, true);
1662 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1663 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1664 } else {
1665 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1666 __func__, state->selected_input);
1667 }
1668 }
1669
disable_input(struct v4l2_subdev * sd)1670 static void disable_input(struct v4l2_subdev *sd)
1671 {
1672 struct adv76xx_state *state = to_state(sd);
1673
1674 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1675 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1676 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1677 state->info->set_termination(sd, false);
1678 }
1679
select_input(struct v4l2_subdev * sd)1680 static void select_input(struct v4l2_subdev *sd)
1681 {
1682 struct adv76xx_state *state = to_state(sd);
1683 const struct adv76xx_chip_info *info = state->info;
1684
1685 if (is_analog_input(sd)) {
1686 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1687
1688 afe_write(sd, 0x00, 0x08); /* power up ADC */
1689 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1690 afe_write(sd, 0xc8, 0x00); /* phase control */
1691 } else if (is_digital_input(sd)) {
1692 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1693
1694 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1695
1696 if (adv76xx_has_afe(state)) {
1697 afe_write(sd, 0x00, 0xff); /* power down ADC */
1698 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1699 afe_write(sd, 0xc8, 0x40); /* phase control */
1700 }
1701
1702 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1703 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1704 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1705 } else {
1706 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1707 __func__, state->selected_input);
1708 }
1709 }
1710
adv76xx_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)1711 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1712 u32 input, u32 output, u32 config)
1713 {
1714 struct adv76xx_state *state = to_state(sd);
1715
1716 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1717 __func__, input, state->selected_input);
1718
1719 if (input == state->selected_input)
1720 return 0;
1721
1722 if (input > state->info->max_port)
1723 return -EINVAL;
1724
1725 state->selected_input = input;
1726
1727 disable_input(sd);
1728
1729 select_input(sd);
1730
1731 enable_input(sd);
1732
1733 return 0;
1734 }
1735
adv76xx_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1736 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1737 struct v4l2_subdev_pad_config *cfg,
1738 struct v4l2_subdev_mbus_code_enum *code)
1739 {
1740 struct adv76xx_state *state = to_state(sd);
1741
1742 if (code->index >= state->info->nformats)
1743 return -EINVAL;
1744
1745 code->code = state->info->formats[code->index].code;
1746
1747 return 0;
1748 }
1749
adv76xx_fill_format(struct adv76xx_state * state,struct v4l2_mbus_framefmt * format)1750 static void adv76xx_fill_format(struct adv76xx_state *state,
1751 struct v4l2_mbus_framefmt *format)
1752 {
1753 memset(format, 0, sizeof(*format));
1754
1755 format->width = state->timings.bt.width;
1756 format->height = state->timings.bt.height;
1757 format->field = V4L2_FIELD_NONE;
1758 format->colorspace = V4L2_COLORSPACE_SRGB;
1759
1760 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1761 format->colorspace = (state->timings.bt.height <= 576) ?
1762 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1763 }
1764
1765 /*
1766 * Compute the op_ch_sel value required to obtain on the bus the component order
1767 * corresponding to the selected format taking into account bus reordering
1768 * applied by the board at the output of the device.
1769 *
1770 * The following table gives the op_ch_value from the format component order
1771 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1772 * adv76xx_bus_order value in row).
1773 *
1774 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1775 * ----------+-------------------------------------------------
1776 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1777 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1778 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1779 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1780 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1781 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1782 */
adv76xx_op_ch_sel(struct adv76xx_state * state)1783 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1784 {
1785 #define _SEL(a,b,c,d,e,f) { \
1786 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1787 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1788 #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1789
1790 static const unsigned int op_ch_sel[6][6] = {
1791 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1792 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1793 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1794 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1795 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1796 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1797 };
1798
1799 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1800 }
1801
adv76xx_setup_format(struct adv76xx_state * state)1802 static void adv76xx_setup_format(struct adv76xx_state *state)
1803 {
1804 struct v4l2_subdev *sd = &state->sd;
1805
1806 io_write_clr_set(sd, 0x02, 0x02,
1807 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1808 io_write(sd, 0x03, state->format->op_format_sel |
1809 state->pdata.op_format_mode_sel);
1810 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1811 io_write_clr_set(sd, 0x05, 0x01,
1812 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1813 }
1814
adv76xx_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1815 static int adv76xx_get_format(struct v4l2_subdev *sd,
1816 struct v4l2_subdev_pad_config *cfg,
1817 struct v4l2_subdev_format *format)
1818 {
1819 struct adv76xx_state *state = to_state(sd);
1820
1821 if (format->pad != state->source_pad)
1822 return -EINVAL;
1823
1824 adv76xx_fill_format(state, &format->format);
1825
1826 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1827 struct v4l2_mbus_framefmt *fmt;
1828
1829 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1830 format->format.code = fmt->code;
1831 } else {
1832 format->format.code = state->format->code;
1833 }
1834
1835 return 0;
1836 }
1837
adv76xx_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1838 static int adv76xx_set_format(struct v4l2_subdev *sd,
1839 struct v4l2_subdev_pad_config *cfg,
1840 struct v4l2_subdev_format *format)
1841 {
1842 struct adv76xx_state *state = to_state(sd);
1843 const struct adv76xx_format_info *info;
1844
1845 if (format->pad != state->source_pad)
1846 return -EINVAL;
1847
1848 info = adv76xx_format_info(state, format->format.code);
1849 if (info == NULL)
1850 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1851
1852 adv76xx_fill_format(state, &format->format);
1853 format->format.code = info->code;
1854
1855 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1856 struct v4l2_mbus_framefmt *fmt;
1857
1858 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1859 fmt->code = format->format.code;
1860 } else {
1861 state->format = info;
1862 adv76xx_setup_format(state);
1863 }
1864
1865 return 0;
1866 }
1867
adv76xx_isr(struct v4l2_subdev * sd,u32 status,bool * handled)1868 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1869 {
1870 struct adv76xx_state *state = to_state(sd);
1871 const struct adv76xx_chip_info *info = state->info;
1872 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1873 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1874 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1875 u8 fmt_change_digital;
1876 u8 fmt_change;
1877 u8 tx_5v;
1878
1879 if (irq_reg_0x43)
1880 io_write(sd, 0x44, irq_reg_0x43);
1881 if (irq_reg_0x70)
1882 io_write(sd, 0x71, irq_reg_0x70);
1883 if (irq_reg_0x6b)
1884 io_write(sd, 0x6c, irq_reg_0x6b);
1885
1886 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1887
1888 /* format change */
1889 fmt_change = irq_reg_0x43 & 0x98;
1890 fmt_change_digital = is_digital_input(sd)
1891 ? irq_reg_0x6b & info->fmt_change_digital_mask
1892 : 0;
1893
1894 if (fmt_change || fmt_change_digital) {
1895 v4l2_dbg(1, debug, sd,
1896 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1897 __func__, fmt_change, fmt_change_digital);
1898
1899 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
1900
1901 if (handled)
1902 *handled = true;
1903 }
1904 /* HDMI/DVI mode */
1905 if (irq_reg_0x6b & 0x01) {
1906 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1907 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1908 set_rgb_quantization_range(sd);
1909 if (handled)
1910 *handled = true;
1911 }
1912
1913 /* tx 5v detect */
1914 tx_5v = irq_reg_0x70 & info->cable_det_mask;
1915 if (tx_5v) {
1916 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1917 adv76xx_s_detect_tx_5v_ctrl(sd);
1918 if (handled)
1919 *handled = true;
1920 }
1921 return 0;
1922 }
1923
adv76xx_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1924 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1925 {
1926 struct adv76xx_state *state = to_state(sd);
1927 u8 *data = NULL;
1928
1929 memset(edid->reserved, 0, sizeof(edid->reserved));
1930
1931 switch (edid->pad) {
1932 case ADV76XX_PAD_HDMI_PORT_A:
1933 case ADV7604_PAD_HDMI_PORT_B:
1934 case ADV7604_PAD_HDMI_PORT_C:
1935 case ADV7604_PAD_HDMI_PORT_D:
1936 if (state->edid.present & (1 << edid->pad))
1937 data = state->edid.edid;
1938 break;
1939 default:
1940 return -EINVAL;
1941 }
1942
1943 if (edid->start_block == 0 && edid->blocks == 0) {
1944 edid->blocks = data ? state->edid.blocks : 0;
1945 return 0;
1946 }
1947
1948 if (data == NULL)
1949 return -ENODATA;
1950
1951 if (edid->start_block >= state->edid.blocks)
1952 return -EINVAL;
1953
1954 if (edid->start_block + edid->blocks > state->edid.blocks)
1955 edid->blocks = state->edid.blocks - edid->start_block;
1956
1957 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1958
1959 return 0;
1960 }
1961
get_edid_spa_location(const u8 * edid)1962 static int get_edid_spa_location(const u8 *edid)
1963 {
1964 u8 d;
1965
1966 if ((edid[0x7e] != 1) ||
1967 (edid[0x80] != 0x02) ||
1968 (edid[0x81] != 0x03)) {
1969 return -1;
1970 }
1971
1972 /* search Vendor Specific Data Block (tag 3) */
1973 d = edid[0x82] & 0x7f;
1974 if (d > 4) {
1975 int i = 0x84;
1976 int end = 0x80 + d;
1977
1978 do {
1979 u8 tag = edid[i] >> 5;
1980 u8 len = edid[i] & 0x1f;
1981
1982 if ((tag == 3) && (len >= 5))
1983 return i + 4;
1984 i += len + 1;
1985 } while (i < end);
1986 }
1987 return -1;
1988 }
1989
adv76xx_set_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1990 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1991 {
1992 struct adv76xx_state *state = to_state(sd);
1993 const struct adv76xx_chip_info *info = state->info;
1994 int spa_loc;
1995 int err;
1996 int i;
1997
1998 memset(edid->reserved, 0, sizeof(edid->reserved));
1999
2000 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2001 return -EINVAL;
2002 if (edid->start_block != 0)
2003 return -EINVAL;
2004 if (edid->blocks == 0) {
2005 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2006 state->edid.present &= ~(1 << edid->pad);
2007 adv76xx_set_hpd(state, state->edid.present);
2008 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2009
2010 /* Fall back to a 16:9 aspect ratio */
2011 state->aspect_ratio.numerator = 16;
2012 state->aspect_ratio.denominator = 9;
2013
2014 if (!state->edid.present)
2015 state->edid.blocks = 0;
2016
2017 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2018 __func__, edid->pad, state->edid.present);
2019 return 0;
2020 }
2021 if (edid->blocks > 2) {
2022 edid->blocks = 2;
2023 return -E2BIG;
2024 }
2025
2026 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2027 __func__, edid->pad, state->edid.present);
2028
2029 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2030 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2031 adv76xx_set_hpd(state, 0);
2032 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2033
2034 spa_loc = get_edid_spa_location(edid->edid);
2035 if (spa_loc < 0)
2036 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2037
2038 switch (edid->pad) {
2039 case ADV76XX_PAD_HDMI_PORT_A:
2040 state->spa_port_a[0] = edid->edid[spa_loc];
2041 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2042 break;
2043 case ADV7604_PAD_HDMI_PORT_B:
2044 rep_write(sd, 0x70, edid->edid[spa_loc]);
2045 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2046 break;
2047 case ADV7604_PAD_HDMI_PORT_C:
2048 rep_write(sd, 0x72, edid->edid[spa_loc]);
2049 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2050 break;
2051 case ADV7604_PAD_HDMI_PORT_D:
2052 rep_write(sd, 0x74, edid->edid[spa_loc]);
2053 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2054 break;
2055 default:
2056 return -EINVAL;
2057 }
2058
2059 if (info->type == ADV7604) {
2060 rep_write(sd, 0x76, spa_loc & 0xff);
2061 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2062 } else {
2063 /* FIXME: Where is the SPA location LSB register ? */
2064 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2065 }
2066
2067 edid->edid[spa_loc] = state->spa_port_a[0];
2068 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2069
2070 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2071 state->edid.blocks = edid->blocks;
2072 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2073 edid->edid[0x16]);
2074 state->edid.present |= 1 << edid->pad;
2075
2076 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2077 if (err < 0) {
2078 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2079 return err;
2080 }
2081
2082 /* adv76xx calculates the checksums and enables I2C access to internal
2083 EDID RAM from DDC port. */
2084 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2085
2086 for (i = 0; i < 1000; i++) {
2087 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2088 break;
2089 mdelay(1);
2090 }
2091 if (i == 1000) {
2092 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2093 return -EIO;
2094 }
2095
2096 /* enable hotplug after 100 ms */
2097 queue_delayed_work(state->work_queues,
2098 &state->delayed_work_enable_hotplug, HZ / 10);
2099 return 0;
2100 }
2101
2102 /*********** avi info frame CEA-861-E **************/
2103
print_avi_infoframe(struct v4l2_subdev * sd)2104 static void print_avi_infoframe(struct v4l2_subdev *sd)
2105 {
2106 int i;
2107 u8 buf[14];
2108 u8 avi_len;
2109 u8 avi_ver;
2110
2111 if (!is_hdmi(sd)) {
2112 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2113 return;
2114 }
2115 if (!(io_read(sd, 0x60) & 0x01)) {
2116 v4l2_info(sd, "AVI infoframe not received\n");
2117 return;
2118 }
2119
2120 if (io_read(sd, 0x83) & 0x01) {
2121 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2122 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2123 if (io_read(sd, 0x83) & 0x01) {
2124 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2125 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2126 }
2127 }
2128
2129 avi_len = infoframe_read(sd, 0xe2);
2130 avi_ver = infoframe_read(sd, 0xe1);
2131 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2132 avi_ver, avi_len);
2133
2134 if (avi_ver != 0x02)
2135 return;
2136
2137 for (i = 0; i < 14; i++)
2138 buf[i] = infoframe_read(sd, i);
2139
2140 v4l2_info(sd,
2141 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2142 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2143 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2144 }
2145
adv76xx_log_status(struct v4l2_subdev * sd)2146 static int adv76xx_log_status(struct v4l2_subdev *sd)
2147 {
2148 struct adv76xx_state *state = to_state(sd);
2149 const struct adv76xx_chip_info *info = state->info;
2150 struct v4l2_dv_timings timings;
2151 struct stdi_readback stdi;
2152 u8 reg_io_0x02 = io_read(sd, 0x02);
2153 u8 edid_enabled;
2154 u8 cable_det;
2155
2156 static const char * const csc_coeff_sel_rb[16] = {
2157 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2158 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2159 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2160 "reserved", "reserved", "reserved", "reserved", "manual"
2161 };
2162 static const char * const input_color_space_txt[16] = {
2163 "RGB limited range (16-235)", "RGB full range (0-255)",
2164 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2165 "xvYCC Bt.601", "xvYCC Bt.709",
2166 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2167 "invalid", "invalid", "invalid", "invalid", "invalid",
2168 "invalid", "invalid", "automatic"
2169 };
2170 static const char * const rgb_quantization_range_txt[] = {
2171 "Automatic",
2172 "RGB limited range (16-235)",
2173 "RGB full range (0-255)",
2174 };
2175 static const char * const deep_color_mode_txt[4] = {
2176 "8-bits per channel",
2177 "10-bits per channel",
2178 "12-bits per channel",
2179 "16-bits per channel (not supported)"
2180 };
2181
2182 v4l2_info(sd, "-----Chip status-----\n");
2183 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2184 edid_enabled = rep_read(sd, info->edid_status_reg);
2185 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2186 ((edid_enabled & 0x01) ? "Yes" : "No"),
2187 ((edid_enabled & 0x02) ? "Yes" : "No"),
2188 ((edid_enabled & 0x04) ? "Yes" : "No"),
2189 ((edid_enabled & 0x08) ? "Yes" : "No"));
2190 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2191 "enabled" : "disabled");
2192
2193 v4l2_info(sd, "-----Signal status-----\n");
2194 cable_det = info->read_cable_det(sd);
2195 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2196 ((cable_det & 0x01) ? "Yes" : "No"),
2197 ((cable_det & 0x02) ? "Yes" : "No"),
2198 ((cable_det & 0x04) ? "Yes" : "No"),
2199 ((cable_det & 0x08) ? "Yes" : "No"));
2200 v4l2_info(sd, "TMDS signal detected: %s\n",
2201 no_signal_tmds(sd) ? "false" : "true");
2202 v4l2_info(sd, "TMDS signal locked: %s\n",
2203 no_lock_tmds(sd) ? "false" : "true");
2204 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2205 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2206 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2207 v4l2_info(sd, "CP free run: %s\n",
2208 (in_free_run(sd)) ? "on" : "off");
2209 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2210 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2211 (io_read(sd, 0x01) & 0x70) >> 4);
2212
2213 v4l2_info(sd, "-----Video Timings-----\n");
2214 if (read_stdi(sd, &stdi))
2215 v4l2_info(sd, "STDI: not locked\n");
2216 else
2217 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2218 stdi.lcf, stdi.bl, stdi.lcvs,
2219 stdi.interlaced ? "interlaced" : "progressive",
2220 stdi.hs_pol, stdi.vs_pol);
2221 if (adv76xx_query_dv_timings(sd, &timings))
2222 v4l2_info(sd, "No video detected\n");
2223 else
2224 v4l2_print_dv_timings(sd->name, "Detected format: ",
2225 &timings, true);
2226 v4l2_print_dv_timings(sd->name, "Configured format: ",
2227 &state->timings, true);
2228
2229 if (no_signal(sd))
2230 return 0;
2231
2232 v4l2_info(sd, "-----Color space-----\n");
2233 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2234 rgb_quantization_range_txt[state->rgb_quantization_range]);
2235 v4l2_info(sd, "Input color space: %s\n",
2236 input_color_space_txt[reg_io_0x02 >> 4]);
2237 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2238 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2239 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2240 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2241 "enabled" : "disabled");
2242 v4l2_info(sd, "Color space conversion: %s\n",
2243 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2244
2245 if (!is_digital_input(sd))
2246 return 0;
2247
2248 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2249 v4l2_info(sd, "Digital video port selected: %c\n",
2250 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2251 v4l2_info(sd, "HDCP encrypted content: %s\n",
2252 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2253 v4l2_info(sd, "HDCP keys read: %s%s\n",
2254 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2255 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2256 if (is_hdmi(sd)) {
2257 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2258 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2259 bool audio_mute = io_read(sd, 0x65) & 0x40;
2260
2261 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2262 audio_pll_locked ? "locked" : "not locked",
2263 audio_sample_packet_detect ? "detected" : "not detected",
2264 audio_mute ? "muted" : "enabled");
2265 if (audio_pll_locked && audio_sample_packet_detect) {
2266 v4l2_info(sd, "Audio format: %s\n",
2267 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2268 }
2269 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2270 (hdmi_read(sd, 0x5c) << 8) +
2271 (hdmi_read(sd, 0x5d) & 0xf0));
2272 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2273 (hdmi_read(sd, 0x5e) << 8) +
2274 hdmi_read(sd, 0x5f));
2275 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2276
2277 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2278
2279 print_avi_infoframe(sd);
2280 }
2281
2282 return 0;
2283 }
2284
2285 /* ----------------------------------------------------------------------- */
2286
2287 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2288 .s_ctrl = adv76xx_s_ctrl,
2289 };
2290
2291 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2292 .log_status = adv76xx_log_status,
2293 .interrupt_service_routine = adv76xx_isr,
2294 #ifdef CONFIG_VIDEO_ADV_DEBUG
2295 .g_register = adv76xx_g_register,
2296 .s_register = adv76xx_s_register,
2297 #endif
2298 };
2299
2300 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2301 .s_routing = adv76xx_s_routing,
2302 .g_input_status = adv76xx_g_input_status,
2303 .s_dv_timings = adv76xx_s_dv_timings,
2304 .g_dv_timings = adv76xx_g_dv_timings,
2305 .query_dv_timings = adv76xx_query_dv_timings,
2306 };
2307
2308 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2309 .enum_mbus_code = adv76xx_enum_mbus_code,
2310 .get_fmt = adv76xx_get_format,
2311 .set_fmt = adv76xx_set_format,
2312 .get_edid = adv76xx_get_edid,
2313 .set_edid = adv76xx_set_edid,
2314 .dv_timings_cap = adv76xx_dv_timings_cap,
2315 .enum_dv_timings = adv76xx_enum_dv_timings,
2316 };
2317
2318 static const struct v4l2_subdev_ops adv76xx_ops = {
2319 .core = &adv76xx_core_ops,
2320 .video = &adv76xx_video_ops,
2321 .pad = &adv76xx_pad_ops,
2322 };
2323
2324 /* -------------------------- custom ctrls ---------------------------------- */
2325
2326 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2327 .ops = &adv76xx_ctrl_ops,
2328 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2329 .name = "Analog Sampling Phase",
2330 .type = V4L2_CTRL_TYPE_INTEGER,
2331 .min = 0,
2332 .max = 0x1f,
2333 .step = 1,
2334 .def = 0,
2335 };
2336
2337 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2338 .ops = &adv76xx_ctrl_ops,
2339 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2340 .name = "Free Running Color, Manual",
2341 .type = V4L2_CTRL_TYPE_BOOLEAN,
2342 .min = false,
2343 .max = true,
2344 .step = 1,
2345 .def = false,
2346 };
2347
2348 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2349 .ops = &adv76xx_ctrl_ops,
2350 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2351 .name = "Free Running Color",
2352 .type = V4L2_CTRL_TYPE_INTEGER,
2353 .min = 0x0,
2354 .max = 0xffffff,
2355 .step = 0x1,
2356 .def = 0x0,
2357 };
2358
2359 /* ----------------------------------------------------------------------- */
2360
adv76xx_core_init(struct v4l2_subdev * sd)2361 static int adv76xx_core_init(struct v4l2_subdev *sd)
2362 {
2363 struct adv76xx_state *state = to_state(sd);
2364 const struct adv76xx_chip_info *info = state->info;
2365 struct adv76xx_platform_data *pdata = &state->pdata;
2366
2367 hdmi_write(sd, 0x48,
2368 (pdata->disable_pwrdnb ? 0x80 : 0) |
2369 (pdata->disable_cable_det_rst ? 0x40 : 0));
2370
2371 disable_input(sd);
2372
2373 if (pdata->default_input >= 0 &&
2374 pdata->default_input < state->source_pad) {
2375 state->selected_input = pdata->default_input;
2376 select_input(sd);
2377 enable_input(sd);
2378 }
2379
2380 /* power */
2381 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2382 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2383 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2384
2385 /* video format */
2386 io_write_clr_set(sd, 0x02, 0x0f,
2387 pdata->alt_gamma << 3 |
2388 pdata->op_656_range << 2 |
2389 pdata->alt_data_sat << 0);
2390 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2391 pdata->insert_av_codes << 2 |
2392 pdata->replicate_av_codes << 1);
2393 adv76xx_setup_format(state);
2394
2395 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2396
2397 /* VS, HS polarities */
2398 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2399 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2400
2401 /* Adjust drive strength */
2402 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2403 pdata->dr_str_clk << 2 |
2404 pdata->dr_str_sync);
2405
2406 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2407 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2408 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2409 ADI recommended setting [REF_01, c. 2.3.3] */
2410 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2411 ADI recommended setting [REF_01, c. 2.3.3] */
2412 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2413 for digital formats */
2414
2415 /* HDMI audio */
2416 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2417 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2418 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2419
2420 /* TODO from platform data */
2421 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2422
2423 if (adv76xx_has_afe(state)) {
2424 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2425 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2426 }
2427
2428 /* interrupts */
2429 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2430 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2431 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2432 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2433 info->setup_irqs(sd);
2434
2435 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2436 }
2437
adv7604_setup_irqs(struct v4l2_subdev * sd)2438 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2439 {
2440 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2441 }
2442
adv7611_setup_irqs(struct v4l2_subdev * sd)2443 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2444 {
2445 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2446 }
2447
adv76xx_unregister_clients(struct adv76xx_state * state)2448 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2449 {
2450 unsigned int i;
2451
2452 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2453 if (state->i2c_clients[i])
2454 i2c_unregister_device(state->i2c_clients[i]);
2455 }
2456 }
2457
adv76xx_dummy_client(struct v4l2_subdev * sd,u8 addr,u8 io_reg)2458 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2459 u8 addr, u8 io_reg)
2460 {
2461 struct i2c_client *client = v4l2_get_subdevdata(sd);
2462
2463 if (addr)
2464 io_write(sd, io_reg, addr << 1);
2465 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2466 }
2467
2468 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2469 /* reset ADI recommended settings for HDMI: */
2470 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2471 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2472 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2473 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2474 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2475 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2476 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2477 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2478 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2479 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2480 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2481 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2482 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2483
2484 /* set ADI recommended settings for digitizer */
2485 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2486 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2487 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2488 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2489 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2490 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2491
2492 { ADV76XX_REG_SEQ_TERM, 0 },
2493 };
2494
2495 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2496 /* set ADI recommended settings for HDMI: */
2497 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2498 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2499 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2503 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2504 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2505 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2506 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2507 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2508 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2509
2510 /* reset ADI recommended settings for digitizer */
2511 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2512 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2513 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2514
2515 { ADV76XX_REG_SEQ_TERM, 0 },
2516 };
2517
2518 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2519 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2520 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2521 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2522 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2529 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2530 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2531
2532 { ADV76XX_REG_SEQ_TERM, 0 },
2533 };
2534
2535 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2536 [ADV7604] = {
2537 .type = ADV7604,
2538 .has_afe = true,
2539 .max_port = ADV7604_PAD_VGA_COMP,
2540 .num_dv_ports = 4,
2541 .edid_enable_reg = 0x77,
2542 .edid_status_reg = 0x7d,
2543 .lcf_reg = 0xb3,
2544 .tdms_lock_mask = 0xe0,
2545 .cable_det_mask = 0x1e,
2546 .fmt_change_digital_mask = 0xc1,
2547 .cp_csc = 0xfc,
2548 .formats = adv7604_formats,
2549 .nformats = ARRAY_SIZE(adv7604_formats),
2550 .set_termination = adv7604_set_termination,
2551 .setup_irqs = adv7604_setup_irqs,
2552 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2553 .read_cable_det = adv7604_read_cable_det,
2554 .recommended_settings = {
2555 [0] = adv7604_recommended_settings_afe,
2556 [1] = adv7604_recommended_settings_hdmi,
2557 },
2558 .num_recommended_settings = {
2559 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2560 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2561 },
2562 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2563 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2564 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2565 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2566 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2567 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2568 BIT(ADV7604_PAGE_VDP),
2569 },
2570 [ADV7611] = {
2571 .type = ADV7611,
2572 .has_afe = false,
2573 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2574 .num_dv_ports = 1,
2575 .edid_enable_reg = 0x74,
2576 .edid_status_reg = 0x76,
2577 .lcf_reg = 0xa3,
2578 .tdms_lock_mask = 0x43,
2579 .cable_det_mask = 0x01,
2580 .fmt_change_digital_mask = 0x03,
2581 .cp_csc = 0xf4,
2582 .formats = adv7611_formats,
2583 .nformats = ARRAY_SIZE(adv7611_formats),
2584 .set_termination = adv7611_set_termination,
2585 .setup_irqs = adv7611_setup_irqs,
2586 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2587 .read_cable_det = adv7611_read_cable_det,
2588 .recommended_settings = {
2589 [1] = adv7611_recommended_settings_hdmi,
2590 },
2591 .num_recommended_settings = {
2592 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2593 },
2594 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2595 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2596 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2597 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2598 },
2599 };
2600
2601 static struct i2c_device_id adv76xx_i2c_id[] = {
2602 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2603 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
2604 { }
2605 };
2606 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
2607
2608 static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2609 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
2610 { }
2611 };
2612 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
2613
adv76xx_parse_dt(struct adv76xx_state * state)2614 static int adv76xx_parse_dt(struct adv76xx_state *state)
2615 {
2616 struct v4l2_of_endpoint bus_cfg;
2617 struct device_node *endpoint;
2618 struct device_node *np;
2619 unsigned int flags;
2620
2621 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
2622
2623 /* Parse the endpoint. */
2624 endpoint = of_graph_get_next_endpoint(np, NULL);
2625 if (!endpoint)
2626 return -EINVAL;
2627
2628 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2629 of_node_put(endpoint);
2630
2631 flags = bus_cfg.bus.parallel.flags;
2632
2633 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2634 state->pdata.inv_hs_pol = 1;
2635
2636 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2637 state->pdata.inv_vs_pol = 1;
2638
2639 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2640 state->pdata.inv_llc_pol = 1;
2641
2642 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2643 state->pdata.insert_av_codes = 1;
2644 state->pdata.op_656_range = 1;
2645 }
2646
2647 /* Disable the interrupt for now as no DT-based board uses it. */
2648 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
2649
2650 /* Use the default I2C addresses. */
2651 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2652 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2653 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
2654 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2656 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2657 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2658 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2659 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2660 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2661 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
2662 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2663
2664 /* Hardcode the remaining platform data fields. */
2665 state->pdata.disable_pwrdnb = 0;
2666 state->pdata.disable_cable_det_rst = 0;
2667 state->pdata.default_input = -1;
2668 state->pdata.blank_data = 1;
2669 state->pdata.alt_data_sat = 1;
2670 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2671 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2672
2673 return 0;
2674 }
2675
adv76xx_probe(struct i2c_client * client,const struct i2c_device_id * id)2676 static int adv76xx_probe(struct i2c_client *client,
2677 const struct i2c_device_id *id)
2678 {
2679 static const struct v4l2_dv_timings cea640x480 =
2680 V4L2_DV_BT_CEA_640X480P59_94;
2681 struct adv76xx_state *state;
2682 struct v4l2_ctrl_handler *hdl;
2683 struct v4l2_subdev *sd;
2684 unsigned int i;
2685 u16 val;
2686 int err;
2687
2688 /* Check if the adapter supports the needed features */
2689 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2690 return -EIO;
2691 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
2692 client->addr << 1);
2693
2694 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2695 if (!state) {
2696 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
2697 return -ENOMEM;
2698 }
2699
2700 state->i2c_clients[ADV76XX_PAGE_IO] = client;
2701
2702 /* initialize variables */
2703 state->restart_stdi_once = true;
2704 state->selected_input = ~0;
2705
2706 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2707 const struct of_device_id *oid;
2708
2709 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
2710 state->info = oid->data;
2711
2712 err = adv76xx_parse_dt(state);
2713 if (err < 0) {
2714 v4l_err(client, "DT parsing error\n");
2715 return err;
2716 }
2717 } else if (client->dev.platform_data) {
2718 struct adv76xx_platform_data *pdata = client->dev.platform_data;
2719
2720 state->info = (const struct adv76xx_chip_info *)id->driver_data;
2721 state->pdata = *pdata;
2722 } else {
2723 v4l_err(client, "No platform data!\n");
2724 return -ENODEV;
2725 }
2726
2727 /* Request GPIOs. */
2728 for (i = 0; i < state->info->num_dv_ports; ++i) {
2729 state->hpd_gpio[i] =
2730 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2731 GPIOD_OUT_LOW);
2732 if (IS_ERR(state->hpd_gpio[i]))
2733 return PTR_ERR(state->hpd_gpio[i]);
2734
2735 if (state->hpd_gpio[i])
2736 v4l_info(client, "Handling HPD %u GPIO\n", i);
2737 }
2738
2739 state->timings = cea640x480;
2740 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2741
2742 sd = &state->sd;
2743 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
2744 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2745 id->name, i2c_adapter_id(client->adapter),
2746 client->addr);
2747 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2748
2749 /*
2750 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2751 * identifies the revision, while on ADV7611 it identifies the model as
2752 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2753 */
2754 if (state->info->type == ADV7604) {
2755 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2756 if (val != 0x68) {
2757 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2758 client->addr << 1);
2759 return -ENODEV;
2760 }
2761 } else {
2762 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2763 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2764 if (val != 0x2051) {
2765 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2766 client->addr << 1);
2767 return -ENODEV;
2768 }
2769 }
2770
2771 /* control handlers */
2772 hdl = &state->hdl;
2773 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
2774
2775 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2776 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2777 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2778 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2779 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2780 V4L2_CID_SATURATION, 0, 255, 1, 128);
2781 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2782 V4L2_CID_HUE, 0, 128, 1, 0);
2783
2784 /* private controls */
2785 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2786 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2787 (1 << state->info->num_dv_ports) - 1, 0, 0);
2788 state->rgb_quantization_range_ctrl =
2789 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
2790 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2791 0, V4L2_DV_RGB_RANGE_AUTO);
2792
2793 /* custom controls */
2794 if (adv76xx_has_afe(state))
2795 state->analog_sampling_phase_ctrl =
2796 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2797 state->free_run_color_manual_ctrl =
2798 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
2799 state->free_run_color_ctrl =
2800 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
2801
2802 sd->ctrl_handler = hdl;
2803 if (hdl->error) {
2804 err = hdl->error;
2805 goto err_hdl;
2806 }
2807 state->detect_tx_5v_ctrl->is_private = true;
2808 state->rgb_quantization_range_ctrl->is_private = true;
2809 if (adv76xx_has_afe(state))
2810 state->analog_sampling_phase_ctrl->is_private = true;
2811 state->free_run_color_manual_ctrl->is_private = true;
2812 state->free_run_color_ctrl->is_private = true;
2813
2814 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
2815 err = -ENODEV;
2816 goto err_hdl;
2817 }
2818
2819 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
2820 if (!(BIT(i) & state->info->page_mask))
2821 continue;
2822
2823 state->i2c_clients[i] =
2824 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
2825 0xf2 + i);
2826 if (state->i2c_clients[i] == NULL) {
2827 err = -ENOMEM;
2828 v4l2_err(sd, "failed to create i2c client %u\n", i);
2829 goto err_i2c;
2830 }
2831 }
2832
2833 /* work queues */
2834 state->work_queues = create_singlethread_workqueue(client->name);
2835 if (!state->work_queues) {
2836 v4l2_err(sd, "Could not create work queue\n");
2837 err = -ENOMEM;
2838 goto err_i2c;
2839 }
2840
2841 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2842 adv76xx_delayed_work_enable_hotplug);
2843
2844 state->source_pad = state->info->num_dv_ports
2845 + (state->info->has_afe ? 2 : 0);
2846 for (i = 0; i < state->source_pad; ++i)
2847 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2848 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2849
2850 err = media_entity_init(&sd->entity, state->source_pad + 1,
2851 state->pads, 0);
2852 if (err)
2853 goto err_work_queues;
2854
2855 err = adv76xx_core_init(sd);
2856 if (err)
2857 goto err_entity;
2858 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2859 client->addr << 1, client->adapter->name);
2860
2861 err = v4l2_async_register_subdev(sd);
2862 if (err)
2863 goto err_entity;
2864
2865 return 0;
2866
2867 err_entity:
2868 media_entity_cleanup(&sd->entity);
2869 err_work_queues:
2870 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2871 destroy_workqueue(state->work_queues);
2872 err_i2c:
2873 adv76xx_unregister_clients(state);
2874 err_hdl:
2875 v4l2_ctrl_handler_free(hdl);
2876 return err;
2877 }
2878
2879 /* ----------------------------------------------------------------------- */
2880
adv76xx_remove(struct i2c_client * client)2881 static int adv76xx_remove(struct i2c_client *client)
2882 {
2883 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2884 struct adv76xx_state *state = to_state(sd);
2885
2886 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2887 destroy_workqueue(state->work_queues);
2888 v4l2_async_unregister_subdev(sd);
2889 media_entity_cleanup(&sd->entity);
2890 adv76xx_unregister_clients(to_state(sd));
2891 v4l2_ctrl_handler_free(sd->ctrl_handler);
2892 return 0;
2893 }
2894
2895 /* ----------------------------------------------------------------------- */
2896
2897 static struct i2c_driver adv76xx_driver = {
2898 .driver = {
2899 .owner = THIS_MODULE,
2900 .name = "adv7604",
2901 .of_match_table = of_match_ptr(adv76xx_of_id),
2902 },
2903 .probe = adv76xx_probe,
2904 .remove = adv76xx_remove,
2905 .id_table = adv76xx_i2c_id,
2906 };
2907
2908 module_i2c_driver(adv76xx_driver);
2909