1 /*
2 * comedi/drivers/adv_pci_dio.c
3 *
4 * Author: Michal Dobes <dobes@tesnet.cz>
5 *
6 * Hardware driver for Advantech PCI DIO cards.
7 */
8 /*
9 Driver: adv_pci_dio
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18 PCI-1760, PCI-1762
19 Status: untested
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
21
22 This driver supports now only insn interface for DI/DO/DIO.
23
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
28 device will be used.
29
30 */
31
32 #include <linux/module.h>
33 #include <linux/delay.h>
34
35 #include "../comedi_pci.h"
36
37 #include "8255.h"
38 #include "comedi_8254.h"
39
40 /* hardware types of the cards */
41 enum hw_cards_id {
42 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
43 TYPE_PCI1739,
44 TYPE_PCI1750,
45 TYPE_PCI1751,
46 TYPE_PCI1752,
47 TYPE_PCI1753, TYPE_PCI1753E,
48 TYPE_PCI1754, TYPE_PCI1756,
49 TYPE_PCI1760,
50 TYPE_PCI1762
51 };
52
53 /* which I/O instructions to use */
54 enum hw_io_access {
55 IO_8b, IO_16b
56 };
57
58 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
59 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
60 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
61 * card */
62
63 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
64
65 /* Register offset definitions */
66 /* Advantech PCI-1730/3/4 */
67 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
68 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
69 #define PCI1730_DI 2 /* R: Digital input 0-15 */
70 #define PCI1730_DO 2 /* W: Digital output 0-15 */
71 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
72 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
73 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
74 * interrupts */
75 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
76 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
77 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
78
79 /* Advantech PCI-1735U */
80 #define PCI1735_DI 0 /* R: Digital input 0-31 */
81 #define PCI1735_DO 0 /* W: Digital output 0-31 */
82 #define PCI1735_C8254 4 /* R/W: 8254 counter */
83 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
84
85 /* Advantech PCI-1736UP */
86 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
87 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
88 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
89 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
90 * interrupts */
91 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
92 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
93 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
94
95 /* Advantech PCI-1739U */
96 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
97 #define PCI1739_ICR 32 /* W: Interrupt control register */
98 #define PCI1739_ISR 32 /* R: Interrupt status register */
99 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
100
101 /* Advantech PCI-1750 */
102 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
103 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
104 #define PCI1750_ICR 32 /* W: Interrupt control register */
105 #define PCI1750_ISR 32 /* R: Interrupt status register */
106
107 /* Advantech PCI-1751/3/3E */
108 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
109 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
110 #define PCI1751_ICR 32 /* W: Interrupt control register */
111 #define PCI1751_ISR 32 /* R: Interrupt status register */
112 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
113 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
114 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
115 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
116 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
117 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
118 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
119 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
120 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
121 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
122
123 /* Advantech PCI-1752/4/6 */
124 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
125 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
126 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
127 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
128 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
129 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
130 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
131 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
132 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
133 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
134 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
135 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
136
137 /* Advantech PCI-1762 registers */
138 #define PCI1762_RO 0 /* R/W: Relays status/output */
139 #define PCI1762_IDI 2 /* R: Isolated input status */
140 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
141 #define PCI1762_ICR 6 /* W: Interrupt control register */
142 #define PCI1762_ISR 6 /* R: Interrupt status register */
143
144 /* Advantech PCI-1760 registers */
145 #define OMB0 0x0c /* W: Mailbox outgoing registers */
146 #define OMB1 0x0d
147 #define OMB2 0x0e
148 #define OMB3 0x0f
149 #define IMB0 0x1c /* R: Mailbox incoming registers */
150 #define IMB1 0x1d
151 #define IMB2 0x1e
152 #define IMB3 0x1f
153 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
154 #define INTCSR1 0x39
155 #define INTCSR2 0x3a
156 #define INTCSR3 0x3b
157
158 /* PCI-1760 mailbox commands */
159 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
160 * DI status in IMB3 */
161 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
162 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
163 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
164 * register in OMB0, result in IMB0 */
165 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
166 * IMB1.IMB0 */
167 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
168 * IMB1.IMB0 */
169 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
170 * OMB0 */
171 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
172 * bits in OMB0 */
173 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
174 * bits in OMB0 */
175 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
176 * OMB0 */
177 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
178 * OMB0 to its reset values */
179 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
180 * interrupts based on bits in OMB0 */
181 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
182 * interrupts based on bits in OMB0 */
183 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
184 * - rising, =1 - falling) */
185 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
186 * value */
187 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
188 * 256*OMB1+OMB0 */
189 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
190 * 256*OMB1+OMB0 */
191 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
192 * 256*OMB1+OMB0 */
193 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
194 * 256*OMB1+OMB0 */
195 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
196 * 256*OMB1+OMB0 */
197 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
198 * 256*OMB1+OMB0 */
199 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
200 * 256*OMB1+OMB0 */
201 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
202 * 256*OMB1+OMB0 */
203 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
204 * 256*OMB1+OMB0 */
205 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
206 * 256*OMB1+OMB0 */
207 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
208 * 256*OMB1+OMB0 */
209 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
210 * 256*OMB1+OMB0 */
211 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
212 * 256*OMB1+OMB0 */
213 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
214 * 256*OMB1+OMB0 */
215 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
216 * 256*OMB1+OMB0 */
217 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
218 * 256*OMB1+OMB0 */
219
220 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
221
222 struct diosubd_data {
223 int chans; /* num of chans */
224 int addr; /* PCI address ofset */
225 int regs; /* number of registers to read or 8255
226 subdevices */
227 unsigned int specflags; /* addon subdevice flags */
228 };
229
230 struct dio_boardtype {
231 const char *name; /* board name */
232 int main_pci_region; /* main I/O PCI region */
233 enum hw_cards_id cardtype;
234 int nsubdevs;
235 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
236 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
237 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
238 struct diosubd_data boardid; /* card supports board ID switch */
239 unsigned long timer_regbase;
240 enum hw_io_access io_access;
241 };
242
243 static const struct dio_boardtype boardtypes[] = {
244 [TYPE_PCI1730] = {
245 .name = "pci1730",
246 .main_pci_region = PCIDIO_MAINREG,
247 .cardtype = TYPE_PCI1730,
248 .nsubdevs = 5,
249 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
250 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
251 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
252 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
253 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
254 .io_access = IO_8b,
255 },
256 [TYPE_PCI1733] = {
257 .name = "pci1733",
258 .main_pci_region = PCIDIO_MAINREG,
259 .cardtype = TYPE_PCI1733,
260 .nsubdevs = 2,
261 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
262 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
263 .io_access = IO_8b,
264 },
265 [TYPE_PCI1734] = {
266 .name = "pci1734",
267 .main_pci_region = PCIDIO_MAINREG,
268 .cardtype = TYPE_PCI1734,
269 .nsubdevs = 2,
270 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
271 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
272 .io_access = IO_8b,
273 },
274 [TYPE_PCI1735] = {
275 .name = "pci1735",
276 .main_pci_region = PCIDIO_MAINREG,
277 .cardtype = TYPE_PCI1735,
278 .nsubdevs = 4,
279 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
280 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
281 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
282 .timer_regbase = PCI1735_C8254,
283 .io_access = IO_8b,
284 },
285 [TYPE_PCI1736] = {
286 .name = "pci1736",
287 .main_pci_region = PCI1736_MAINREG,
288 .cardtype = TYPE_PCI1736,
289 .nsubdevs = 3,
290 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
291 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
292 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
293 .io_access = IO_8b,
294 },
295 [TYPE_PCI1739] = {
296 .name = "pci1739",
297 .main_pci_region = PCIDIO_MAINREG,
298 .cardtype = TYPE_PCI1739,
299 .nsubdevs = 2,
300 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
301 .io_access = IO_8b,
302 },
303 [TYPE_PCI1750] = {
304 .name = "pci1750",
305 .main_pci_region = PCIDIO_MAINREG,
306 .cardtype = TYPE_PCI1750,
307 .nsubdevs = 2,
308 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
309 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
310 .io_access = IO_8b,
311 },
312 [TYPE_PCI1751] = {
313 .name = "pci1751",
314 .main_pci_region = PCIDIO_MAINREG,
315 .cardtype = TYPE_PCI1751,
316 .nsubdevs = 3,
317 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
318 .timer_regbase = PCI1751_CNT,
319 .io_access = IO_8b,
320 },
321 [TYPE_PCI1752] = {
322 .name = "pci1752",
323 .main_pci_region = PCIDIO_MAINREG,
324 .cardtype = TYPE_PCI1752,
325 .nsubdevs = 3,
326 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
327 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
328 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
329 .io_access = IO_16b,
330 },
331 [TYPE_PCI1753] = {
332 .name = "pci1753",
333 .main_pci_region = PCIDIO_MAINREG,
334 .cardtype = TYPE_PCI1753,
335 .nsubdevs = 4,
336 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
337 .io_access = IO_8b,
338 },
339 [TYPE_PCI1753E] = {
340 .name = "pci1753e",
341 .main_pci_region = PCIDIO_MAINREG,
342 .cardtype = TYPE_PCI1753E,
343 .nsubdevs = 8,
344 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
345 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
346 .io_access = IO_8b,
347 },
348 [TYPE_PCI1754] = {
349 .name = "pci1754",
350 .main_pci_region = PCIDIO_MAINREG,
351 .cardtype = TYPE_PCI1754,
352 .nsubdevs = 3,
353 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
354 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
355 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
356 .io_access = IO_16b,
357 },
358 [TYPE_PCI1756] = {
359 .name = "pci1756",
360 .main_pci_region = PCIDIO_MAINREG,
361 .cardtype = TYPE_PCI1756,
362 .nsubdevs = 3,
363 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
364 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
365 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
366 .io_access = IO_16b,
367 },
368 [TYPE_PCI1760] = {
369 /* This card has its own 'attach' */
370 .name = "pci1760",
371 .main_pci_region = 0,
372 .cardtype = TYPE_PCI1760,
373 .nsubdevs = 4,
374 .io_access = IO_8b,
375 },
376 [TYPE_PCI1762] = {
377 .name = "pci1762",
378 .main_pci_region = PCIDIO_MAINREG,
379 .cardtype = TYPE_PCI1762,
380 .nsubdevs = 3,
381 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
382 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
383 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
384 .io_access = IO_16b,
385 },
386 };
387
388 struct pci_dio_private {
389 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
390 /* PCI-1760 specific data */
391 unsigned char IDICntEnable; /* counter's counting enable status */
392 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
393 * status */
394 unsigned char IDICntMatchEnable; /* counter's match interrupts
395 * enable status */
396 unsigned char IDICntEdge; /* counter's count edge value
397 * (bit=0 - rising, =1 - falling) */
398 unsigned short CntResValue[8]; /* counters' reset value */
399 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
400 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
401 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
402 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
403 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
404 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
405 };
406
407 /*
408 ==============================================================================
409 */
pci_dio_insn_bits_di_b(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)410 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
411 struct comedi_subdevice *s,
412 struct comedi_insn *insn, unsigned int *data)
413 {
414 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
415 int i;
416
417 data[1] = 0;
418 for (i = 0; i < d->regs; i++)
419 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
420
421 return insn->n;
422 }
423
424 /*
425 ==============================================================================
426 */
pci_dio_insn_bits_di_w(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)427 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
428 struct comedi_subdevice *s,
429 struct comedi_insn *insn, unsigned int *data)
430 {
431 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
432 int i;
433
434 data[1] = 0;
435 for (i = 0; i < d->regs; i++)
436 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
437
438 return insn->n;
439 }
440
pci_dio_insn_bits_do_b(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)441 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
442 struct comedi_subdevice *s,
443 struct comedi_insn *insn,
444 unsigned int *data)
445 {
446 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
447 int i;
448
449 if (comedi_dio_update_state(s, data)) {
450 for (i = 0; i < d->regs; i++)
451 outb((s->state >> (8 * i)) & 0xff,
452 dev->iobase + d->addr + i);
453 }
454
455 data[1] = s->state;
456
457 return insn->n;
458 }
459
pci_dio_insn_bits_do_w(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)460 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
461 struct comedi_subdevice *s,
462 struct comedi_insn *insn,
463 unsigned int *data)
464 {
465 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
466 int i;
467
468 if (comedi_dio_update_state(s, data)) {
469 for (i = 0; i < d->regs; i++)
470 outw((s->state >> (16 * i)) & 0xffff,
471 dev->iobase + d->addr + 2 * i);
472 }
473
474 data[1] = s->state;
475
476 return insn->n;
477 }
478
479 /*
480 ==============================================================================
481 */
pci1760_unchecked_mbxrequest(struct comedi_device * dev,unsigned char * omb,unsigned char * imb,int repeats)482 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
483 unsigned char *omb, unsigned char *imb,
484 int repeats)
485 {
486 int cnt, tout, ok = 0;
487
488 for (cnt = 0; cnt < repeats; cnt++) {
489 outb(omb[0], dev->iobase + OMB0);
490 outb(omb[1], dev->iobase + OMB1);
491 outb(omb[2], dev->iobase + OMB2);
492 outb(omb[3], dev->iobase + OMB3);
493 for (tout = 0; tout < 251; tout++) {
494 imb[2] = inb(dev->iobase + IMB2);
495 if (imb[2] == omb[2]) {
496 imb[0] = inb(dev->iobase + IMB0);
497 imb[1] = inb(dev->iobase + IMB1);
498 imb[3] = inb(dev->iobase + IMB3);
499 ok = 1;
500 break;
501 }
502 udelay(1);
503 }
504 if (ok)
505 return 0;
506 }
507
508 dev_err(dev->class_dev, "PCI-1760 mailbox request timeout!\n");
509 return -ETIME;
510 }
511
pci1760_clear_imb2(struct comedi_device * dev)512 static int pci1760_clear_imb2(struct comedi_device *dev)
513 {
514 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
515 unsigned char imb[4];
516 /* check if imb2 is already clear */
517 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
518 return 0;
519 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
520 }
521
pci1760_mbxrequest(struct comedi_device * dev,unsigned char * omb,unsigned char * imb)522 static int pci1760_mbxrequest(struct comedi_device *dev,
523 unsigned char *omb, unsigned char *imb)
524 {
525 if (omb[2] == CMD_ClearIMB2) {
526 dev_err(dev->class_dev,
527 "bug! this function should not be used for CMD_ClearIMB2 command\n");
528 return -EINVAL;
529 }
530 if (inb(dev->iobase + IMB2) == omb[2]) {
531 int retval;
532
533 retval = pci1760_clear_imb2(dev);
534 if (retval < 0)
535 return retval;
536 }
537 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
538 }
539
540 /*
541 ==============================================================================
542 */
pci1760_insn_bits_di(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)543 static int pci1760_insn_bits_di(struct comedi_device *dev,
544 struct comedi_subdevice *s,
545 struct comedi_insn *insn, unsigned int *data)
546 {
547 data[1] = inb(dev->iobase + IMB3);
548
549 return insn->n;
550 }
551
pci1760_insn_bits_do(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)552 static int pci1760_insn_bits_do(struct comedi_device *dev,
553 struct comedi_subdevice *s,
554 struct comedi_insn *insn,
555 unsigned int *data)
556 {
557 int ret;
558 unsigned char omb[4] = {
559 0x00,
560 0x00,
561 CMD_SetRelaysOutput,
562 0x00
563 };
564 unsigned char imb[4];
565
566 if (comedi_dio_update_state(s, data)) {
567 omb[0] = s->state;
568 ret = pci1760_mbxrequest(dev, omb, imb);
569 if (!ret)
570 return ret;
571 }
572
573 data[1] = s->state;
574
575 return insn->n;
576 }
577
578 /*
579 ==============================================================================
580 */
pci1760_insn_cnt_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)581 static int pci1760_insn_cnt_read(struct comedi_device *dev,
582 struct comedi_subdevice *s,
583 struct comedi_insn *insn, unsigned int *data)
584 {
585 int ret, n;
586 unsigned char omb[4] = {
587 CR_CHAN(insn->chanspec) & 0x07,
588 0x00,
589 CMD_GetIDICntCurValue,
590 0x00
591 };
592 unsigned char imb[4];
593
594 for (n = 0; n < insn->n; n++) {
595 ret = pci1760_mbxrequest(dev, omb, imb);
596 if (!ret)
597 return ret;
598 data[n] = (imb[1] << 8) + imb[0];
599 }
600
601 return n;
602 }
603
604 /*
605 ==============================================================================
606 */
pci1760_insn_cnt_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)607 static int pci1760_insn_cnt_write(struct comedi_device *dev,
608 struct comedi_subdevice *s,
609 struct comedi_insn *insn, unsigned int *data)
610 {
611 struct pci_dio_private *devpriv = dev->private;
612 int ret;
613 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
614 unsigned char bitmask = 1 << chan;
615 unsigned char omb[4] = {
616 data[0] & 0xff,
617 (data[0] >> 8) & 0xff,
618 CMD_SetIDI0CntResetValue + chan,
619 0x00
620 };
621 unsigned char imb[4];
622
623 /* Set reset value if different */
624 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
625 ret = pci1760_mbxrequest(dev, omb, imb);
626 if (!ret)
627 return ret;
628 devpriv->CntResValue[chan] = data[0] & 0xffff;
629 }
630
631 omb[0] = bitmask; /* reset counter to it reset value */
632 omb[2] = CMD_ResetIDICounters;
633 ret = pci1760_mbxrequest(dev, omb, imb);
634 if (!ret)
635 return ret;
636
637 /* start counter if it don't run */
638 if (!(bitmask & devpriv->IDICntEnable)) {
639 omb[0] = bitmask;
640 omb[2] = CMD_EnableIDICounters;
641 ret = pci1760_mbxrequest(dev, omb, imb);
642 if (!ret)
643 return ret;
644 devpriv->IDICntEnable |= bitmask;
645 }
646 return 1;
647 }
648
649 /*
650 ==============================================================================
651 */
pci1760_reset(struct comedi_device * dev)652 static int pci1760_reset(struct comedi_device *dev)
653 {
654 struct pci_dio_private *devpriv = dev->private;
655 int i;
656 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
657 unsigned char imb[4];
658
659 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
660 outb(0, dev->iobase + INTCSR1);
661 outb(0, dev->iobase + INTCSR2);
662 outb(0, dev->iobase + INTCSR3);
663 devpriv->GlobalIrqEnabled = 0;
664
665 omb[0] = 0x00;
666 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
667 pci1760_mbxrequest(dev, omb, imb);
668
669 omb[0] = 0x00;
670 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
671 pci1760_mbxrequest(dev, omb, imb);
672 devpriv->IDICntEnable = 0;
673
674 omb[0] = 0x00;
675 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
676 * interrupts */
677 pci1760_mbxrequest(dev, omb, imb);
678 devpriv->IDICntOverEnable = 0;
679
680 omb[0] = 0x00;
681 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
682 * interrupts */
683 pci1760_mbxrequest(dev, omb, imb);
684 devpriv->IDICntMatchEnable = 0;
685
686 omb[0] = 0x00;
687 omb[1] = 0x80;
688 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
689 omb[2] = CMD_SetIDI0CntMatchValue + i;
690 pci1760_mbxrequest(dev, omb, imb);
691 devpriv->CntMatchValue[i] = 0x8000;
692 }
693
694 omb[0] = 0x00;
695 omb[1] = 0x00;
696 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
697 omb[2] = CMD_SetIDI0CntResetValue + i;
698 pci1760_mbxrequest(dev, omb, imb);
699 devpriv->CntResValue[i] = 0x0000;
700 }
701
702 omb[0] = 0xff;
703 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
704 * values */
705 pci1760_mbxrequest(dev, omb, imb);
706
707 omb[0] = 0x00;
708 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
709 pci1760_mbxrequest(dev, omb, imb);
710 devpriv->IDICntEdge = 0x00;
711
712 omb[0] = 0x00;
713 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
714 pci1760_mbxrequest(dev, omb, imb);
715 devpriv->IDIFiltersEn = 0x00;
716
717 omb[0] = 0x00;
718 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
719 pci1760_mbxrequest(dev, omb, imb);
720 devpriv->IDIPatMatchEn = 0x00;
721
722 omb[0] = 0x00;
723 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
724 pci1760_mbxrequest(dev, omb, imb);
725 devpriv->IDIPatMatchValue = 0x00;
726
727 return 0;
728 }
729
730 /*
731 ==============================================================================
732 */
pci_dio_reset(struct comedi_device * dev)733 static int pci_dio_reset(struct comedi_device *dev)
734 {
735 const struct dio_boardtype *board = dev->board_ptr;
736
737 switch (board->cardtype) {
738 case TYPE_PCI1730:
739 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
740 outb(0, dev->iobase + PCI1730_DO + 1);
741 outb(0, dev->iobase + PCI1730_IDO);
742 outb(0, dev->iobase + PCI1730_IDO + 1);
743 /* fallthrough */
744 case TYPE_PCI1733:
745 /* disable interrupts */
746 outb(0, dev->iobase + PCI1730_3_INT_EN);
747 /* clear interrupts */
748 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
749 /* set rising edge trigger */
750 outb(0, dev->iobase + PCI1730_3_INT_RF);
751 break;
752 case TYPE_PCI1734:
753 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
754 outb(0, dev->iobase + PCI1734_IDO + 1);
755 outb(0, dev->iobase + PCI1734_IDO + 2);
756 outb(0, dev->iobase + PCI1734_IDO + 3);
757 break;
758 case TYPE_PCI1735:
759 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
760 outb(0, dev->iobase + PCI1735_DO + 1);
761 outb(0, dev->iobase + PCI1735_DO + 2);
762 outb(0, dev->iobase + PCI1735_DO + 3);
763 break;
764
765 case TYPE_PCI1736:
766 outb(0, dev->iobase + PCI1736_IDO);
767 outb(0, dev->iobase + PCI1736_IDO + 1);
768 /* disable interrupts */
769 outb(0, dev->iobase + PCI1736_3_INT_EN);
770 /* clear interrupts */
771 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
772 /* set rising edge trigger */
773 outb(0, dev->iobase + PCI1736_3_INT_RF);
774 break;
775
776 case TYPE_PCI1739:
777 /* disable & clear interrupts */
778 outb(0x88, dev->iobase + PCI1739_ICR);
779 break;
780
781 case TYPE_PCI1750:
782 case TYPE_PCI1751:
783 /* disable & clear interrupts */
784 outb(0x88, dev->iobase + PCI1750_ICR);
785 break;
786 case TYPE_PCI1752:
787 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
788 * function */
789 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
790 outw(0, dev->iobase + PCI1752_IDO + 2);
791 outw(0, dev->iobase + PCI1752_IDO2);
792 outw(0, dev->iobase + PCI1752_IDO2 + 2);
793 break;
794 case TYPE_PCI1753E:
795 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
796 * interrupts */
797 outb(0x80, dev->iobase + PCI1753E_ICR1);
798 outb(0x80, dev->iobase + PCI1753E_ICR2);
799 outb(0x80, dev->iobase + PCI1753E_ICR3);
800 /* fallthrough */
801 case TYPE_PCI1753:
802 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
803 * interrupts */
804 outb(0x80, dev->iobase + PCI1753_ICR1);
805 outb(0x80, dev->iobase + PCI1753_ICR2);
806 outb(0x80, dev->iobase + PCI1753_ICR3);
807 break;
808 case TYPE_PCI1754:
809 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
810 * interrupts */
811 outw(0x08, dev->iobase + PCI1754_6_ICR1);
812 outw(0x08, dev->iobase + PCI1754_ICR2);
813 outw(0x08, dev->iobase + PCI1754_ICR3);
814 break;
815 case TYPE_PCI1756:
816 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
817 * function */
818 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
819 * interrupts */
820 outw(0x08, dev->iobase + PCI1754_6_ICR1);
821 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
822 outw(0, dev->iobase + PCI1756_IDO + 2);
823 break;
824 case TYPE_PCI1760:
825 pci1760_reset(dev);
826 break;
827 case TYPE_PCI1762:
828 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
829 * interrupts */
830 break;
831 }
832
833 return 0;
834 }
835
836 /*
837 ==============================================================================
838 */
pci1760_attach(struct comedi_device * dev)839 static int pci1760_attach(struct comedi_device *dev)
840 {
841 struct comedi_subdevice *s;
842
843 s = &dev->subdevices[0];
844 s->type = COMEDI_SUBD_DI;
845 s->subdev_flags = SDF_READABLE;
846 s->n_chan = 8;
847 s->maxdata = 1;
848 s->len_chanlist = 8;
849 s->range_table = &range_digital;
850 s->insn_bits = pci1760_insn_bits_di;
851
852 s = &dev->subdevices[1];
853 s->type = COMEDI_SUBD_DO;
854 s->subdev_flags = SDF_WRITABLE;
855 s->n_chan = 8;
856 s->maxdata = 1;
857 s->len_chanlist = 8;
858 s->range_table = &range_digital;
859 s->state = 0;
860 s->insn_bits = pci1760_insn_bits_do;
861
862 s = &dev->subdevices[2];
863 s->type = COMEDI_SUBD_TIMER;
864 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
865 s->n_chan = 2;
866 s->maxdata = 0xffffffff;
867 s->len_chanlist = 2;
868 /* s->insn_config=pci1760_insn_pwm_cfg; */
869
870 s = &dev->subdevices[3];
871 s->type = COMEDI_SUBD_COUNTER;
872 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
873 s->n_chan = 8;
874 s->maxdata = 0xffff;
875 s->len_chanlist = 8;
876 s->insn_read = pci1760_insn_cnt_read;
877 s->insn_write = pci1760_insn_cnt_write;
878 /* s->insn_config=pci1760_insn_cnt_cfg; */
879
880 return 0;
881 }
882
883 /*
884 ==============================================================================
885 */
pci_dio_add_di(struct comedi_device * dev,struct comedi_subdevice * s,const struct diosubd_data * d)886 static int pci_dio_add_di(struct comedi_device *dev,
887 struct comedi_subdevice *s,
888 const struct diosubd_data *d)
889 {
890 const struct dio_boardtype *board = dev->board_ptr;
891
892 s->type = COMEDI_SUBD_DI;
893 s->subdev_flags = SDF_READABLE | d->specflags;
894 if (d->chans > 16)
895 s->subdev_flags |= SDF_LSAMPL;
896 s->n_chan = d->chans;
897 s->maxdata = 1;
898 s->len_chanlist = d->chans;
899 s->range_table = &range_digital;
900 switch (board->io_access) {
901 case IO_8b:
902 s->insn_bits = pci_dio_insn_bits_di_b;
903 break;
904 case IO_16b:
905 s->insn_bits = pci_dio_insn_bits_di_w;
906 break;
907 }
908 s->private = (void *)d;
909
910 return 0;
911 }
912
913 /*
914 ==============================================================================
915 */
pci_dio_add_do(struct comedi_device * dev,struct comedi_subdevice * s,const struct diosubd_data * d)916 static int pci_dio_add_do(struct comedi_device *dev,
917 struct comedi_subdevice *s,
918 const struct diosubd_data *d)
919 {
920 const struct dio_boardtype *board = dev->board_ptr;
921
922 s->type = COMEDI_SUBD_DO;
923 s->subdev_flags = SDF_WRITABLE;
924 if (d->chans > 16)
925 s->subdev_flags |= SDF_LSAMPL;
926 s->n_chan = d->chans;
927 s->maxdata = 1;
928 s->len_chanlist = d->chans;
929 s->range_table = &range_digital;
930 s->state = 0;
931 switch (board->io_access) {
932 case IO_8b:
933 s->insn_bits = pci_dio_insn_bits_do_b;
934 break;
935 case IO_16b:
936 s->insn_bits = pci_dio_insn_bits_do_w;
937 break;
938 }
939 s->private = (void *)d;
940
941 return 0;
942 }
943
pci_dio_override_cardtype(struct pci_dev * pcidev,unsigned long cardtype)944 static unsigned long pci_dio_override_cardtype(struct pci_dev *pcidev,
945 unsigned long cardtype)
946 {
947 /*
948 * Change cardtype from TYPE_PCI1753 to TYPE_PCI1753E if expansion
949 * board available. Need to enable PCI device and request the main
950 * registers PCI BAR temporarily to perform the test.
951 */
952 if (cardtype != TYPE_PCI1753)
953 return cardtype;
954 if (pci_enable_device(pcidev) < 0)
955 return cardtype;
956 if (pci_request_region(pcidev, PCIDIO_MAINREG, "adv_pci_dio") == 0) {
957 /*
958 * This test is based on Advantech's "advdaq" driver source
959 * (which declares its module licence as "GPL" although the
960 * driver source does not include a "COPYING" file).
961 */
962 unsigned long reg =
963 pci_resource_start(pcidev, PCIDIO_MAINREG) + 53;
964
965 outb(0x05, reg);
966 if ((inb(reg) & 0x07) == 0x02) {
967 outb(0x02, reg);
968 if ((inb(reg) & 0x07) == 0x05)
969 cardtype = TYPE_PCI1753E;
970 }
971 pci_release_region(pcidev, PCIDIO_MAINREG);
972 }
973 pci_disable_device(pcidev);
974 return cardtype;
975 }
976
pci_dio_auto_attach(struct comedi_device * dev,unsigned long context)977 static int pci_dio_auto_attach(struct comedi_device *dev,
978 unsigned long context)
979 {
980 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
981 const struct dio_boardtype *board = NULL;
982 struct pci_dio_private *devpriv;
983 struct comedi_subdevice *s;
984 int ret, subdev, i, j;
985
986 if (context < ARRAY_SIZE(boardtypes))
987 board = &boardtypes[context];
988 if (!board)
989 return -ENODEV;
990 dev->board_ptr = board;
991 dev->board_name = board->name;
992
993 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
994 if (!devpriv)
995 return -ENOMEM;
996
997 ret = comedi_pci_enable(dev);
998 if (ret)
999 return ret;
1000 dev->iobase = pci_resource_start(pcidev, board->main_pci_region);
1001
1002 ret = comedi_alloc_subdevices(dev, board->nsubdevs);
1003 if (ret)
1004 return ret;
1005
1006 subdev = 0;
1007 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1008 if (board->sdi[i].chans) {
1009 s = &dev->subdevices[subdev];
1010 pci_dio_add_di(dev, s, &board->sdi[i]);
1011 subdev++;
1012 }
1013
1014 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1015 if (board->sdo[i].chans) {
1016 s = &dev->subdevices[subdev];
1017 pci_dio_add_do(dev, s, &board->sdo[i]);
1018 subdev++;
1019 }
1020
1021 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1022 for (j = 0; j < board->sdio[i].regs; j++) {
1023 s = &dev->subdevices[subdev];
1024 ret = subdev_8255_init(dev, s, NULL,
1025 board->sdio[i].addr +
1026 j * I8255_SIZE);
1027 if (ret)
1028 return ret;
1029 subdev++;
1030 }
1031
1032 if (board->boardid.chans) {
1033 s = &dev->subdevices[subdev];
1034 s->type = COMEDI_SUBD_DI;
1035 pci_dio_add_di(dev, s, &board->boardid);
1036 subdev++;
1037 }
1038
1039 if (board->timer_regbase) {
1040 s = &dev->subdevices[subdev];
1041
1042 dev->pacer = comedi_8254_init(dev->iobase +
1043 board->timer_regbase,
1044 0, I8254_IO8, 0);
1045 if (!dev->pacer)
1046 return -ENOMEM;
1047
1048 comedi_8254_subdevice_init(s, dev->pacer);
1049
1050 subdev++;
1051 }
1052
1053 if (board->cardtype == TYPE_PCI1760)
1054 pci1760_attach(dev);
1055
1056 pci_dio_reset(dev);
1057
1058 return 0;
1059 }
1060
pci_dio_detach(struct comedi_device * dev)1061 static void pci_dio_detach(struct comedi_device *dev)
1062 {
1063 if (dev->iobase)
1064 pci_dio_reset(dev);
1065 comedi_pci_detach(dev);
1066 }
1067
1068 static struct comedi_driver adv_pci_dio_driver = {
1069 .driver_name = "adv_pci_dio",
1070 .module = THIS_MODULE,
1071 .auto_attach = pci_dio_auto_attach,
1072 .detach = pci_dio_detach,
1073 };
1074
adv_pci_dio_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1075 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1076 const struct pci_device_id *id)
1077 {
1078 unsigned long cardtype;
1079
1080 cardtype = pci_dio_override_cardtype(dev, id->driver_data);
1081 return comedi_pci_auto_config(dev, &adv_pci_dio_driver, cardtype);
1082 }
1083
1084 static const struct pci_device_id adv_pci_dio_pci_table[] = {
1085 { PCI_VDEVICE(ADVANTECH, 0x1730), TYPE_PCI1730 },
1086 { PCI_VDEVICE(ADVANTECH, 0x1733), TYPE_PCI1733 },
1087 { PCI_VDEVICE(ADVANTECH, 0x1734), TYPE_PCI1734 },
1088 { PCI_VDEVICE(ADVANTECH, 0x1735), TYPE_PCI1735 },
1089 { PCI_VDEVICE(ADVANTECH, 0x1736), TYPE_PCI1736 },
1090 { PCI_VDEVICE(ADVANTECH, 0x1739), TYPE_PCI1739 },
1091 { PCI_VDEVICE(ADVANTECH, 0x1750), TYPE_PCI1750 },
1092 { PCI_VDEVICE(ADVANTECH, 0x1751), TYPE_PCI1751 },
1093 { PCI_VDEVICE(ADVANTECH, 0x1752), TYPE_PCI1752 },
1094 { PCI_VDEVICE(ADVANTECH, 0x1753), TYPE_PCI1753 },
1095 { PCI_VDEVICE(ADVANTECH, 0x1754), TYPE_PCI1754 },
1096 { PCI_VDEVICE(ADVANTECH, 0x1756), TYPE_PCI1756 },
1097 { PCI_VDEVICE(ADVANTECH, 0x1760), TYPE_PCI1760 },
1098 { PCI_VDEVICE(ADVANTECH, 0x1762), TYPE_PCI1762 },
1099 { 0 }
1100 };
1101 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1102
1103 static struct pci_driver adv_pci_dio_pci_driver = {
1104 .name = "adv_pci_dio",
1105 .id_table = adv_pci_dio_pci_table,
1106 .probe = adv_pci_dio_pci_probe,
1107 .remove = comedi_pci_auto_unconfig,
1108 };
1109 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1110
1111 MODULE_AUTHOR("Comedi http://www.comedi.org");
1112 MODULE_DESCRIPTION("Comedi low-level driver");
1113 MODULE_LICENSE("GPL");
1114