1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
59 };
60
61 enum board_ids {
62 /* board IDs by feature in alphabetical order */
63 board_ahci,
64 board_ahci_ign_iferr,
65 board_ahci_nomsi,
66 board_ahci_noncq,
67 board_ahci_nosntf,
68 board_ahci_yes_fbs,
69
70 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_avn,
72 board_ahci_mcp65,
73 board_ahci_mcp77,
74 board_ahci_mcp89,
75 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
85 };
86
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
99 #endif
100
101 static struct scsi_host_template ahci_sht = {
102 AHCI_SHT("ahci"),
103 };
104
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
108 };
109
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
113 };
114
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
118 };
119
120 static const struct ata_port_info ahci_port_info[] = {
121 /* by features */
122 [board_ahci] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 /* by chipsets */
164 [board_ahci_avn] = {
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
169 },
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
172 AHCI_HFLAG_YES_NCQ),
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mv] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
208 },
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
222 },
223 };
224
225 static const struct pci_device_id ahci_pci_tbl[] = {
226 /* Intel */
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
338 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
340 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
344 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
348 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
353 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
361 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
363 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
364 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
365 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
368 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
371 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
372 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
374 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
380 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
385
386 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
387 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
388 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
389 /* JMicron 362B and 362C have an AHCI function with IDE class code */
390 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
391 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
392 /* May need to update quirk_jmicron_async_suspend() for additions */
393
394 /* ATI */
395 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
396 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
397 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
398 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
399 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
402
403 /* AMD */
404 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
405 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
406 /* AMD is using RAID class only for ahci controllers */
407 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
409
410 /* VIA */
411 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
412 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
413
414 /* NVIDIA */
415 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
436 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
476 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
488 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
499
500 /* SiS */
501 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
502 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
503 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
504
505 /* ST Microelectronics */
506 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
507
508 /* Marvell */
509 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
510 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
511 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
512 .class = PCI_CLASS_STORAGE_SATA_AHCI,
513 .class_mask = 0xffffff,
514 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
515 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
516 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
517 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
518 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
523 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
527 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
529 .driver_data = board_ahci_yes_fbs },
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
531 .driver_data = board_ahci_yes_fbs },
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
533 .driver_data = board_ahci_yes_fbs },
534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
535 .driver_data = board_ahci_yes_fbs },
536 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
537 .driver_data = board_ahci_yes_fbs },
538
539 /* Promise */
540 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
541 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
542
543 /* Asmedia */
544 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
545 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
546 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
547 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
548
549 /*
550 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
551 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
552 */
553 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
554 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
555
556 /* Enmotus */
557 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
558
559 /* Generic, PCI class code for AHCI */
560 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
561 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
562
563 { } /* terminate list */
564 };
565
566
567 static struct pci_driver ahci_pci_driver = {
568 .name = DRV_NAME,
569 .id_table = ahci_pci_tbl,
570 .probe = ahci_init_one,
571 .remove = ata_pci_remove_one,
572 #ifdef CONFIG_PM
573 .suspend = ahci_pci_device_suspend,
574 .resume = ahci_pci_device_resume,
575 #endif
576 };
577
578 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
579 static int marvell_enable;
580 #else
581 static int marvell_enable = 1;
582 #endif
583 module_param(marvell_enable, int, 0644);
584 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
585
586
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)587 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
588 struct ahci_host_priv *hpriv)
589 {
590 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
591 dev_info(&pdev->dev, "JMB361 has only one port\n");
592 hpriv->force_port_map = 1;
593 }
594
595 /*
596 * Temporary Marvell 6145 hack: PATA port presence
597 * is asserted through the standard AHCI port
598 * presence register, as bit 4 (counting from 0)
599 */
600 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
601 if (pdev->device == 0x6121)
602 hpriv->mask_port_map = 0x3;
603 else
604 hpriv->mask_port_map = 0xf;
605 dev_info(&pdev->dev,
606 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
607 }
608
609 ahci_save_initial_config(&pdev->dev, hpriv);
610 }
611
ahci_pci_reset_controller(struct ata_host * host)612 static int ahci_pci_reset_controller(struct ata_host *host)
613 {
614 struct pci_dev *pdev = to_pci_dev(host->dev);
615
616 ahci_reset_controller(host);
617
618 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
619 struct ahci_host_priv *hpriv = host->private_data;
620 u16 tmp16;
621
622 /* configure PCS */
623 pci_read_config_word(pdev, 0x92, &tmp16);
624 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
625 tmp16 |= hpriv->port_map;
626 pci_write_config_word(pdev, 0x92, tmp16);
627 }
628 }
629
630 return 0;
631 }
632
ahci_pci_init_controller(struct ata_host * host)633 static void ahci_pci_init_controller(struct ata_host *host)
634 {
635 struct ahci_host_priv *hpriv = host->private_data;
636 struct pci_dev *pdev = to_pci_dev(host->dev);
637 void __iomem *port_mmio;
638 u32 tmp;
639 int mv;
640
641 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
642 if (pdev->device == 0x6121)
643 mv = 2;
644 else
645 mv = 4;
646 port_mmio = __ahci_port_base(host, mv);
647
648 writel(0, port_mmio + PORT_IRQ_MASK);
649
650 /* clear port IRQ */
651 tmp = readl(port_mmio + PORT_IRQ_STAT);
652 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
653 if (tmp)
654 writel(tmp, port_mmio + PORT_IRQ_STAT);
655 }
656
657 ahci_init_controller(host);
658 }
659
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)660 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
661 unsigned long deadline)
662 {
663 struct ata_port *ap = link->ap;
664 struct ahci_host_priv *hpriv = ap->host->private_data;
665 bool online;
666 int rc;
667
668 DPRINTK("ENTER\n");
669
670 ahci_stop_engine(ap);
671
672 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
673 deadline, &online, NULL);
674
675 hpriv->start_engine(ap);
676
677 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
678
679 /* vt8251 doesn't clear BSY on signature FIS reception,
680 * request follow-up softreset.
681 */
682 return online ? -EAGAIN : rc;
683 }
684
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)685 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
686 unsigned long deadline)
687 {
688 struct ata_port *ap = link->ap;
689 struct ahci_port_priv *pp = ap->private_data;
690 struct ahci_host_priv *hpriv = ap->host->private_data;
691 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
692 struct ata_taskfile tf;
693 bool online;
694 int rc;
695
696 ahci_stop_engine(ap);
697
698 /* clear D2H reception area to properly wait for D2H FIS */
699 ata_tf_init(link->device, &tf);
700 tf.command = ATA_BUSY;
701 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
702
703 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
704 deadline, &online, NULL);
705
706 hpriv->start_engine(ap);
707
708 /* The pseudo configuration device on SIMG4726 attached to
709 * ASUS P5W-DH Deluxe doesn't send signature FIS after
710 * hardreset if no device is attached to the first downstream
711 * port && the pseudo device locks up on SRST w/ PMP==0. To
712 * work around this, wait for !BSY only briefly. If BSY isn't
713 * cleared, perform CLO and proceed to IDENTIFY (achieved by
714 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
715 *
716 * Wait for two seconds. Devices attached to downstream port
717 * which can't process the following IDENTIFY after this will
718 * have to be reset again. For most cases, this should
719 * suffice while making probing snappish enough.
720 */
721 if (online) {
722 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
723 ahci_check_ready);
724 if (rc)
725 ahci_kick_engine(ap);
726 }
727 return rc;
728 }
729
730 /*
731 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
732 *
733 * It has been observed with some SSDs that the timing of events in the
734 * link synchronization phase can leave the port in a state that can not
735 * be recovered by a SATA-hard-reset alone. The failing signature is
736 * SStatus.DET stuck at 1 ("Device presence detected but Phy
737 * communication not established"). It was found that unloading and
738 * reloading the driver when this problem occurs allows the drive
739 * connection to be recovered (DET advanced to 0x3). The critical
740 * component of reloading the driver is that the port state machines are
741 * reset by bouncing "port enable" in the AHCI PCS configuration
742 * register. So, reproduce that effect by bouncing a port whenever we
743 * see DET==1 after a reset.
744 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)745 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
746 unsigned long deadline)
747 {
748 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
749 struct ata_port *ap = link->ap;
750 struct ahci_port_priv *pp = ap->private_data;
751 struct ahci_host_priv *hpriv = ap->host->private_data;
752 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
753 unsigned long tmo = deadline - jiffies;
754 struct ata_taskfile tf;
755 bool online;
756 int rc, i;
757
758 DPRINTK("ENTER\n");
759
760 ahci_stop_engine(ap);
761
762 for (i = 0; i < 2; i++) {
763 u16 val;
764 u32 sstatus;
765 int port = ap->port_no;
766 struct ata_host *host = ap->host;
767 struct pci_dev *pdev = to_pci_dev(host->dev);
768
769 /* clear D2H reception area to properly wait for D2H FIS */
770 ata_tf_init(link->device, &tf);
771 tf.command = ATA_BUSY;
772 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
773
774 rc = sata_link_hardreset(link, timing, deadline, &online,
775 ahci_check_ready);
776
777 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
778 (sstatus & 0xf) != 1)
779 break;
780
781 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
782 port);
783
784 pci_read_config_word(pdev, 0x92, &val);
785 val &= ~(1 << port);
786 pci_write_config_word(pdev, 0x92, val);
787 ata_msleep(ap, 1000);
788 val |= 1 << port;
789 pci_write_config_word(pdev, 0x92, val);
790 deadline += tmo;
791 }
792
793 hpriv->start_engine(ap);
794
795 if (online)
796 *class = ahci_dev_classify(ap);
797
798 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
799 return rc;
800 }
801
802
803 #ifdef CONFIG_PM
ahci_pci_device_suspend(struct pci_dev * pdev,pm_message_t mesg)804 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
805 {
806 struct ata_host *host = pci_get_drvdata(pdev);
807 struct ahci_host_priv *hpriv = host->private_data;
808 void __iomem *mmio = hpriv->mmio;
809 u32 ctl;
810
811 if (mesg.event & PM_EVENT_SUSPEND &&
812 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
813 dev_err(&pdev->dev,
814 "BIOS update required for suspend/resume\n");
815 return -EIO;
816 }
817
818 if (mesg.event & PM_EVENT_SLEEP) {
819 /* AHCI spec rev1.1 section 8.3.3:
820 * Software must disable interrupts prior to requesting a
821 * transition of the HBA to D3 state.
822 */
823 ctl = readl(mmio + HOST_CTL);
824 ctl &= ~HOST_IRQ_EN;
825 writel(ctl, mmio + HOST_CTL);
826 readl(mmio + HOST_CTL); /* flush */
827 }
828
829 return ata_pci_device_suspend(pdev, mesg);
830 }
831
ahci_pci_device_resume(struct pci_dev * pdev)832 static int ahci_pci_device_resume(struct pci_dev *pdev)
833 {
834 struct ata_host *host = pci_get_drvdata(pdev);
835 int rc;
836
837 rc = ata_pci_device_do_resume(pdev);
838 if (rc)
839 return rc;
840
841 /* Apple BIOS helpfully mangles the registers on resume */
842 if (is_mcp89_apple(pdev))
843 ahci_mcp89_apple_enable(pdev);
844
845 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
846 rc = ahci_pci_reset_controller(host);
847 if (rc)
848 return rc;
849
850 ahci_pci_init_controller(host);
851 }
852
853 ata_host_resume(host);
854
855 return 0;
856 }
857 #endif
858
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)859 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
860 {
861 int rc;
862
863 /*
864 * If the device fixup already set the dma_mask to some non-standard
865 * value, don't extend it here. This happens on STA2X11, for example.
866 */
867 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
868 return 0;
869
870 if (using_dac &&
871 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
872 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
873 if (rc) {
874 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
875 if (rc) {
876 dev_err(&pdev->dev,
877 "64-bit DMA enable failed\n");
878 return rc;
879 }
880 }
881 } else {
882 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
883 if (rc) {
884 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
885 return rc;
886 }
887 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
888 if (rc) {
889 dev_err(&pdev->dev,
890 "32-bit consistent DMA enable failed\n");
891 return rc;
892 }
893 }
894 return 0;
895 }
896
ahci_pci_print_info(struct ata_host * host)897 static void ahci_pci_print_info(struct ata_host *host)
898 {
899 struct pci_dev *pdev = to_pci_dev(host->dev);
900 u16 cc;
901 const char *scc_s;
902
903 pci_read_config_word(pdev, 0x0a, &cc);
904 if (cc == PCI_CLASS_STORAGE_IDE)
905 scc_s = "IDE";
906 else if (cc == PCI_CLASS_STORAGE_SATA)
907 scc_s = "SATA";
908 else if (cc == PCI_CLASS_STORAGE_RAID)
909 scc_s = "RAID";
910 else
911 scc_s = "unknown";
912
913 ahci_print_info(host, scc_s);
914 }
915
916 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
917 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
918 * support PMP and the 4726 either directly exports the device
919 * attached to the first downstream port or acts as a hardware storage
920 * controller and emulate a single ATA device (can be RAID 0/1 or some
921 * other configuration).
922 *
923 * When there's no device attached to the first downstream port of the
924 * 4726, "Config Disk" appears, which is a pseudo ATA device to
925 * configure the 4726. However, ATA emulation of the device is very
926 * lame. It doesn't send signature D2H Reg FIS after the initial
927 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
928 *
929 * The following function works around the problem by always using
930 * hardreset on the port and not depending on receiving signature FIS
931 * afterward. If signature FIS isn't received soon, ATA class is
932 * assumed without follow-up softreset.
933 */
ahci_p5wdh_workaround(struct ata_host * host)934 static void ahci_p5wdh_workaround(struct ata_host *host)
935 {
936 static const struct dmi_system_id sysids[] = {
937 {
938 .ident = "P5W DH Deluxe",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR,
941 "ASUSTEK COMPUTER INC"),
942 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
943 },
944 },
945 { }
946 };
947 struct pci_dev *pdev = to_pci_dev(host->dev);
948
949 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
950 dmi_check_system(sysids)) {
951 struct ata_port *ap = host->ports[1];
952
953 dev_info(&pdev->dev,
954 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
955
956 ap->ops = &ahci_p5wdh_ops;
957 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
958 }
959 }
960
961 /*
962 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
963 * booting in BIOS compatibility mode. We restore the registers but not ID.
964 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)965 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
966 {
967 u32 val;
968
969 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
970
971 pci_read_config_dword(pdev, 0xf8, &val);
972 val |= 1 << 0x1b;
973 /* the following changes the device ID, but appears not to affect function */
974 /* val = (val & ~0xf0000000) | 0x80000000; */
975 pci_write_config_dword(pdev, 0xf8, val);
976
977 pci_read_config_dword(pdev, 0x54c, &val);
978 val |= 1 << 0xc;
979 pci_write_config_dword(pdev, 0x54c, val);
980
981 pci_read_config_dword(pdev, 0x4a4, &val);
982 val &= 0xff;
983 val |= 0x01060100;
984 pci_write_config_dword(pdev, 0x4a4, val);
985
986 pci_read_config_dword(pdev, 0x54c, &val);
987 val &= ~(1 << 0xc);
988 pci_write_config_dword(pdev, 0x54c, val);
989
990 pci_read_config_dword(pdev, 0xf8, &val);
991 val &= ~(1 << 0x1b);
992 pci_write_config_dword(pdev, 0xf8, val);
993 }
994
is_mcp89_apple(struct pci_dev * pdev)995 static bool is_mcp89_apple(struct pci_dev *pdev)
996 {
997 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
998 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
999 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1000 pdev->subsystem_device == 0xcb89;
1001 }
1002
1003 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1004 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1005 {
1006 static const struct dmi_system_id sysids[] = {
1007 /*
1008 * The oldest version known to be broken is 0901 and
1009 * working is 1501 which was released on 2007-10-26.
1010 * Enable 64bit DMA on 1501 and anything newer.
1011 *
1012 * Please read bko#9412 for more info.
1013 */
1014 {
1015 .ident = "ASUS M2A-VM",
1016 .matches = {
1017 DMI_MATCH(DMI_BOARD_VENDOR,
1018 "ASUSTeK Computer INC."),
1019 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1020 },
1021 .driver_data = "20071026", /* yyyymmdd */
1022 },
1023 /*
1024 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1025 * support 64bit DMA.
1026 *
1027 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1028 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1029 * This spelling mistake was fixed in BIOS version 1.5, so
1030 * 1.5 and later have the Manufacturer as
1031 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1032 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1033 *
1034 * BIOS versions earlier than 1.9 had a Board Product Name
1035 * DMI field of "MS-7376". This was changed to be
1036 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1037 * match on DMI_BOARD_NAME of "MS-7376".
1038 */
1039 {
1040 .ident = "MSI K9A2 Platinum",
1041 .matches = {
1042 DMI_MATCH(DMI_BOARD_VENDOR,
1043 "MICRO-STAR INTER"),
1044 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1045 },
1046 },
1047 /*
1048 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1049 * 64bit DMA.
1050 *
1051 * This board also had the typo mentioned above in the
1052 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1053 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1054 */
1055 {
1056 .ident = "MSI K9AGM2",
1057 .matches = {
1058 DMI_MATCH(DMI_BOARD_VENDOR,
1059 "MICRO-STAR INTER"),
1060 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1061 },
1062 },
1063 /*
1064 * All BIOS versions for the Asus M3A support 64bit DMA.
1065 * (all release versions from 0301 to 1206 were tested)
1066 */
1067 {
1068 .ident = "ASUS M3A",
1069 .matches = {
1070 DMI_MATCH(DMI_BOARD_VENDOR,
1071 "ASUSTeK Computer INC."),
1072 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1073 },
1074 },
1075 { }
1076 };
1077 const struct dmi_system_id *match;
1078 int year, month, date;
1079 char buf[9];
1080
1081 match = dmi_first_match(sysids);
1082 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1083 !match)
1084 return false;
1085
1086 if (!match->driver_data)
1087 goto enable_64bit;
1088
1089 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1090 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1091
1092 if (strcmp(buf, match->driver_data) >= 0)
1093 goto enable_64bit;
1094 else {
1095 dev_warn(&pdev->dev,
1096 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1097 match->ident);
1098 return false;
1099 }
1100
1101 enable_64bit:
1102 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1103 return true;
1104 }
1105
ahci_broken_system_poweroff(struct pci_dev * pdev)1106 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1107 {
1108 static const struct dmi_system_id broken_systems[] = {
1109 {
1110 .ident = "HP Compaq nx6310",
1111 .matches = {
1112 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1113 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1114 },
1115 /* PCI slot number of the controller */
1116 .driver_data = (void *)0x1FUL,
1117 },
1118 {
1119 .ident = "HP Compaq 6720s",
1120 .matches = {
1121 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1122 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1123 },
1124 /* PCI slot number of the controller */
1125 .driver_data = (void *)0x1FUL,
1126 },
1127
1128 { } /* terminate list */
1129 };
1130 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1131
1132 if (dmi) {
1133 unsigned long slot = (unsigned long)dmi->driver_data;
1134 /* apply the quirk only to on-board controllers */
1135 return slot == PCI_SLOT(pdev->devfn);
1136 }
1137
1138 return false;
1139 }
1140
ahci_broken_suspend(struct pci_dev * pdev)1141 static bool ahci_broken_suspend(struct pci_dev *pdev)
1142 {
1143 static const struct dmi_system_id sysids[] = {
1144 /*
1145 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1146 * to the harddisk doesn't become online after
1147 * resuming from STR. Warn and fail suspend.
1148 *
1149 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1150 *
1151 * Use dates instead of versions to match as HP is
1152 * apparently recycling both product and version
1153 * strings.
1154 *
1155 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1156 */
1157 {
1158 .ident = "dv4",
1159 .matches = {
1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1161 DMI_MATCH(DMI_PRODUCT_NAME,
1162 "HP Pavilion dv4 Notebook PC"),
1163 },
1164 .driver_data = "20090105", /* F.30 */
1165 },
1166 {
1167 .ident = "dv5",
1168 .matches = {
1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1170 DMI_MATCH(DMI_PRODUCT_NAME,
1171 "HP Pavilion dv5 Notebook PC"),
1172 },
1173 .driver_data = "20090506", /* F.16 */
1174 },
1175 {
1176 .ident = "dv6",
1177 .matches = {
1178 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1179 DMI_MATCH(DMI_PRODUCT_NAME,
1180 "HP Pavilion dv6 Notebook PC"),
1181 },
1182 .driver_data = "20090423", /* F.21 */
1183 },
1184 {
1185 .ident = "HDX18",
1186 .matches = {
1187 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1188 DMI_MATCH(DMI_PRODUCT_NAME,
1189 "HP HDX18 Notebook PC"),
1190 },
1191 .driver_data = "20090430", /* F.23 */
1192 },
1193 /*
1194 * Acer eMachines G725 has the same problem. BIOS
1195 * V1.03 is known to be broken. V3.04 is known to
1196 * work. Between, there are V1.06, V2.06 and V3.03
1197 * that we don't have much idea about. For now,
1198 * blacklist anything older than V3.04.
1199 *
1200 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1201 */
1202 {
1203 .ident = "G725",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1206 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1207 },
1208 .driver_data = "20091216", /* V3.04 */
1209 },
1210 { } /* terminate list */
1211 };
1212 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1213 int year, month, date;
1214 char buf[9];
1215
1216 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1217 return false;
1218
1219 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1220 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1221
1222 return strcmp(buf, dmi->driver_data) < 0;
1223 }
1224
ahci_broken_online(struct pci_dev * pdev)1225 static bool ahci_broken_online(struct pci_dev *pdev)
1226 {
1227 #define ENCODE_BUSDEVFN(bus, slot, func) \
1228 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1229 static const struct dmi_system_id sysids[] = {
1230 /*
1231 * There are several gigabyte boards which use
1232 * SIMG5723s configured as hardware RAID. Certain
1233 * 5723 firmware revisions shipped there keep the link
1234 * online but fail to answer properly to SRST or
1235 * IDENTIFY when no device is attached downstream
1236 * causing libata to retry quite a few times leading
1237 * to excessive detection delay.
1238 *
1239 * As these firmwares respond to the second reset try
1240 * with invalid device signature, considering unknown
1241 * sig as offline works around the problem acceptably.
1242 */
1243 {
1244 .ident = "EP45-DQ6",
1245 .matches = {
1246 DMI_MATCH(DMI_BOARD_VENDOR,
1247 "Gigabyte Technology Co., Ltd."),
1248 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1249 },
1250 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1251 },
1252 {
1253 .ident = "EP45-DS5",
1254 .matches = {
1255 DMI_MATCH(DMI_BOARD_VENDOR,
1256 "Gigabyte Technology Co., Ltd."),
1257 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1258 },
1259 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1260 },
1261 { } /* terminate list */
1262 };
1263 #undef ENCODE_BUSDEVFN
1264 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1265 unsigned int val;
1266
1267 if (!dmi)
1268 return false;
1269
1270 val = (unsigned long)dmi->driver_data;
1271
1272 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1273 }
1274
ahci_broken_devslp(struct pci_dev * pdev)1275 static bool ahci_broken_devslp(struct pci_dev *pdev)
1276 {
1277 /* device with broken DEVSLP but still showing SDS capability */
1278 static const struct pci_device_id ids[] = {
1279 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1280 {}
1281 };
1282
1283 return pci_match_id(ids, pdev);
1284 }
1285
1286 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1287 static void ahci_gtf_filter_workaround(struct ata_host *host)
1288 {
1289 static const struct dmi_system_id sysids[] = {
1290 /*
1291 * Aspire 3810T issues a bunch of SATA enable commands
1292 * via _GTF including an invalid one and one which is
1293 * rejected by the device. Among the successful ones
1294 * is FPDMA non-zero offset enable which when enabled
1295 * only on the drive side leads to NCQ command
1296 * failures. Filter it out.
1297 */
1298 {
1299 .ident = "Aspire 3810T",
1300 .matches = {
1301 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1302 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1303 },
1304 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1305 },
1306 { }
1307 };
1308 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1309 unsigned int filter;
1310 int i;
1311
1312 if (!dmi)
1313 return;
1314
1315 filter = (unsigned long)dmi->driver_data;
1316 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1317 filter, dmi->ident);
1318
1319 for (i = 0; i < host->n_ports; i++) {
1320 struct ata_port *ap = host->ports[i];
1321 struct ata_link *link;
1322 struct ata_device *dev;
1323
1324 ata_for_each_link(link, ap, EDGE)
1325 ata_for_each_dev(dev, link, ALL)
1326 dev->gtf_filter |= filter;
1327 }
1328 }
1329 #else
ahci_gtf_filter_workaround(struct ata_host * host)1330 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1331 {}
1332 #endif
1333
1334 /*
1335 * ahci_init_msix() only implements single MSI-X support, not multiple
1336 * MSI-X per-port interrupts. This is needed for host controllers that only
1337 * have MSI-X support implemented, but no MSI or intx.
1338 */
ahci_init_msix(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1339 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1340 struct ahci_host_priv *hpriv)
1341 {
1342 int rc, nvec;
1343 struct msix_entry entry = {};
1344
1345 /* Do not init MSI-X if MSI is disabled for the device */
1346 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1347 return -ENODEV;
1348
1349 nvec = pci_msix_vec_count(pdev);
1350 if (nvec < 0)
1351 return nvec;
1352
1353 if (!nvec) {
1354 rc = -ENODEV;
1355 goto fail;
1356 }
1357
1358 /*
1359 * There can be more than one vector (e.g. for error detection or
1360 * hdd hotplug). Only the first vector (entry.entry = 0) is used.
1361 */
1362 rc = pci_enable_msix_exact(pdev, &entry, 1);
1363 if (rc < 0)
1364 goto fail;
1365
1366 hpriv->irq = entry.vector;
1367
1368 return 1;
1369 fail:
1370 dev_err(&pdev->dev,
1371 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1372 rc, nvec);
1373
1374 return rc;
1375 }
1376
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1377 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1378 struct ahci_host_priv *hpriv)
1379 {
1380 int rc, nvec;
1381
1382 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1383 return -ENODEV;
1384
1385 nvec = pci_msi_vec_count(pdev);
1386 if (nvec < 0)
1387 return nvec;
1388
1389 /*
1390 * If number of MSIs is less than number of ports then Sharing Last
1391 * Message mode could be enforced. In this case assume that advantage
1392 * of multipe MSIs is negated and use single MSI mode instead.
1393 */
1394 if (nvec < n_ports)
1395 goto single_msi;
1396
1397 rc = pci_enable_msi_exact(pdev, nvec);
1398 if (rc == -ENOSPC)
1399 goto single_msi;
1400 if (rc < 0)
1401 return rc;
1402
1403 /* fallback to single MSI mode if the controller enforced MRSM mode */
1404 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1405 pci_disable_msi(pdev);
1406 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1407 goto single_msi;
1408 }
1409
1410 if (nvec > 1)
1411 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1412
1413 goto out;
1414
1415 single_msi:
1416 nvec = 1;
1417
1418 rc = pci_enable_msi(pdev);
1419 if (rc < 0)
1420 return rc;
1421 out:
1422 hpriv->irq = pdev->irq;
1423
1424 return nvec;
1425 }
1426
ahci_init_interrupts(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1427 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1428 struct ahci_host_priv *hpriv)
1429 {
1430 int nvec;
1431
1432 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1433 if (nvec >= 0)
1434 return nvec;
1435
1436 /*
1437 * Currently, MSI-X support only implements single IRQ mode and
1438 * exists for controllers which can't do other types of IRQ. Only
1439 * set it up if MSI fails.
1440 */
1441 nvec = ahci_init_msix(pdev, n_ports, hpriv);
1442 if (nvec >= 0)
1443 return nvec;
1444
1445 /* lagacy intx interrupts */
1446 pci_intx(pdev, 1);
1447 hpriv->irq = pdev->irq;
1448
1449 return 0;
1450 }
1451
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1452 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1453 {
1454 unsigned int board_id = ent->driver_data;
1455 struct ata_port_info pi = ahci_port_info[board_id];
1456 const struct ata_port_info *ppi[] = { &pi, NULL };
1457 struct device *dev = &pdev->dev;
1458 struct ahci_host_priv *hpriv;
1459 struct ata_host *host;
1460 int n_ports, i, rc;
1461 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1462
1463 VPRINTK("ENTER\n");
1464
1465 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1466
1467 ata_print_version_once(&pdev->dev, DRV_VERSION);
1468
1469 /* The AHCI driver can only drive the SATA ports, the PATA driver
1470 can drive them all so if both drivers are selected make sure
1471 AHCI stays out of the way */
1472 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1473 return -ENODEV;
1474
1475 /* Apple BIOS on MCP89 prevents us using AHCI */
1476 if (is_mcp89_apple(pdev))
1477 ahci_mcp89_apple_enable(pdev);
1478
1479 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1480 * At the moment, we can only use the AHCI mode. Let the users know
1481 * that for SAS drives they're out of luck.
1482 */
1483 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1484 dev_info(&pdev->dev,
1485 "PDC42819 can only drive SATA devices with this driver\n");
1486
1487 /* Some devices use non-standard BARs */
1488 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1489 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1490 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1491 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1492 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1493 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1494
1495 /* acquire resources */
1496 rc = pcim_enable_device(pdev);
1497 if (rc)
1498 return rc;
1499
1500 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1501 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1502 u8 map;
1503
1504 /* ICH6s share the same PCI ID for both piix and ahci
1505 * modes. Enabling ahci mode while MAP indicates
1506 * combined mode is a bad idea. Yield to ata_piix.
1507 */
1508 pci_read_config_byte(pdev, ICH_MAP, &map);
1509 if (map & 0x3) {
1510 dev_info(&pdev->dev,
1511 "controller is in combined mode, can't enable AHCI mode\n");
1512 return -ENODEV;
1513 }
1514 }
1515
1516 /* AHCI controllers often implement SFF compatible interface.
1517 * Grab all PCI BARs just in case.
1518 */
1519 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1520 if (rc == -EBUSY)
1521 pcim_pin_device(pdev);
1522 if (rc)
1523 return rc;
1524
1525 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1526 if (!hpriv)
1527 return -ENOMEM;
1528 hpriv->flags |= (unsigned long)pi.private_data;
1529
1530 /* MCP65 revision A1 and A2 can't do MSI */
1531 if (board_id == board_ahci_mcp65 &&
1532 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1533 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1534
1535 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1536 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1537 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1538
1539 /* only some SB600s can do 64bit DMA */
1540 if (ahci_sb600_enable_64bit(pdev))
1541 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1542
1543 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1544
1545 /* must set flag prior to save config in order to take effect */
1546 if (ahci_broken_devslp(pdev))
1547 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1548
1549 /* save initial config */
1550 ahci_pci_save_initial_config(pdev, hpriv);
1551
1552 /* prepare host */
1553 if (hpriv->cap & HOST_CAP_NCQ) {
1554 pi.flags |= ATA_FLAG_NCQ;
1555 /*
1556 * Auto-activate optimization is supposed to be
1557 * supported on all AHCI controllers indicating NCQ
1558 * capability, but it seems to be broken on some
1559 * chipsets including NVIDIAs.
1560 */
1561 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1562 pi.flags |= ATA_FLAG_FPDMA_AA;
1563
1564 /*
1565 * All AHCI controllers should be forward-compatible
1566 * with the new auxiliary field. This code should be
1567 * conditionalized if any buggy AHCI controllers are
1568 * encountered.
1569 */
1570 pi.flags |= ATA_FLAG_FPDMA_AUX;
1571 }
1572
1573 if (hpriv->cap & HOST_CAP_PMP)
1574 pi.flags |= ATA_FLAG_PMP;
1575
1576 ahci_set_em_messages(hpriv, &pi);
1577
1578 if (ahci_broken_system_poweroff(pdev)) {
1579 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1580 dev_info(&pdev->dev,
1581 "quirky BIOS, skipping spindown on poweroff\n");
1582 }
1583
1584 if (ahci_broken_suspend(pdev)) {
1585 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1586 dev_warn(&pdev->dev,
1587 "BIOS update required for suspend/resume\n");
1588 }
1589
1590 if (ahci_broken_online(pdev)) {
1591 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1592 dev_info(&pdev->dev,
1593 "online status unreliable, applying workaround\n");
1594 }
1595
1596 /* CAP.NP sometimes indicate the index of the last enabled
1597 * port, at other times, that of the last possible port, so
1598 * determining the maximum port number requires looking at
1599 * both CAP.NP and port_map.
1600 */
1601 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1602
1603 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1604 if (!host)
1605 return -ENOMEM;
1606 host->private_data = hpriv;
1607
1608 ahci_init_interrupts(pdev, n_ports, hpriv);
1609
1610 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1611 host->flags |= ATA_HOST_PARALLEL_SCAN;
1612 else
1613 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1614
1615 if (pi.flags & ATA_FLAG_EM)
1616 ahci_reset_em(host);
1617
1618 for (i = 0; i < host->n_ports; i++) {
1619 struct ata_port *ap = host->ports[i];
1620
1621 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1622 ata_port_pbar_desc(ap, ahci_pci_bar,
1623 0x100 + ap->port_no * 0x80, "port");
1624
1625 /* set enclosure management message type */
1626 if (ap->flags & ATA_FLAG_EM)
1627 ap->em_message_type = hpriv->em_msg_type;
1628
1629
1630 /* disabled/not-implemented port */
1631 if (!(hpriv->port_map & (1 << i)))
1632 ap->ops = &ata_dummy_port_ops;
1633 }
1634
1635 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1636 ahci_p5wdh_workaround(host);
1637
1638 /* apply gtf filter quirk */
1639 ahci_gtf_filter_workaround(host);
1640
1641 /* initialize adapter */
1642 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1643 if (rc)
1644 return rc;
1645
1646 rc = ahci_pci_reset_controller(host);
1647 if (rc)
1648 return rc;
1649
1650 ahci_pci_init_controller(host);
1651 ahci_pci_print_info(host);
1652
1653 pci_set_master(pdev);
1654
1655 return ahci_host_activate(host, &ahci_sht);
1656 }
1657
1658 module_pci_driver(ahci_pci_driver);
1659
1660 MODULE_AUTHOR("Jeff Garzik");
1661 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1662 MODULE_LICENSE("GPL");
1663 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1664 MODULE_VERSION(DRV_VERSION);
1665