1 /* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Keyur Chudgar <kchudgar@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "xgene_enet_main.h"
22 #include "xgene_enet_hw.h"
23 #include "xgene_enet_xgmac.h"
24
xgene_enet_wr_csr(struct xgene_enet_pdata * pdata,u32 offset,u32 val)25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
26 u32 offset, u32 val)
27 {
28 void __iomem *addr = pdata->eth_csr_addr + offset;
29
30 iowrite32(val, addr);
31 }
32
xgene_enet_wr_ring_if(struct xgene_enet_pdata * pdata,u32 offset,u32 val)33 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
34 u32 offset, u32 val)
35 {
36 void __iomem *addr = pdata->eth_ring_if_addr + offset;
37
38 iowrite32(val, addr);
39 }
40
xgene_enet_wr_diag_csr(struct xgene_enet_pdata * pdata,u32 offset,u32 val)41 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
42 u32 offset, u32 val)
43 {
44 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
45
46 iowrite32(val, addr);
47 }
48
xgene_enet_wr_indirect(void __iomem * addr,void __iomem * wr,void __iomem * cmd,void __iomem * cmd_done,u32 wr_addr,u32 wr_data)49 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
50 void __iomem *cmd, void __iomem *cmd_done,
51 u32 wr_addr, u32 wr_data)
52 {
53 u32 done;
54 u8 wait = 10;
55
56 iowrite32(wr_addr, addr);
57 iowrite32(wr_data, wr);
58 iowrite32(XGENE_ENET_WR_CMD, cmd);
59
60 /* wait for write command to complete */
61 while (!(done = ioread32(cmd_done)) && wait--)
62 udelay(1);
63
64 if (!done)
65 return false;
66
67 iowrite32(0, cmd);
68
69 return true;
70 }
71
xgene_enet_wr_mac(struct xgene_enet_pdata * pdata,u32 wr_addr,u32 wr_data)72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
73 u32 wr_addr, u32 wr_data)
74 {
75 void __iomem *addr, *wr, *cmd, *cmd_done;
76
77 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
78 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
79 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
80 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
81
82 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
83 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
84 wr_addr);
85 }
86
xgene_enet_rd_csr(struct xgene_enet_pdata * pdata,u32 offset,u32 * val)87 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
88 u32 offset, u32 *val)
89 {
90 void __iomem *addr = pdata->eth_csr_addr + offset;
91
92 *val = ioread32(addr);
93 }
94
xgene_enet_rd_diag_csr(struct xgene_enet_pdata * pdata,u32 offset,u32 * val)95 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
96 u32 offset, u32 *val)
97 {
98 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
99
100 *val = ioread32(addr);
101 }
102
xgene_enet_rd_indirect(void __iomem * addr,void __iomem * rd,void __iomem * cmd,void __iomem * cmd_done,u32 rd_addr,u32 * rd_data)103 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
104 void __iomem *cmd, void __iomem *cmd_done,
105 u32 rd_addr, u32 *rd_data)
106 {
107 u32 done;
108 u8 wait = 10;
109
110 iowrite32(rd_addr, addr);
111 iowrite32(XGENE_ENET_RD_CMD, cmd);
112
113 /* wait for read command to complete */
114 while (!(done = ioread32(cmd_done)) && wait--)
115 udelay(1);
116
117 if (!done)
118 return false;
119
120 *rd_data = ioread32(rd);
121 iowrite32(0, cmd);
122
123 return true;
124 }
xgene_enet_rd_mac(struct xgene_enet_pdata * pdata,u32 rd_addr,u32 * rd_data)125 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
126 u32 rd_addr, u32 *rd_data)
127 {
128 void __iomem *addr, *rd, *cmd, *cmd_done;
129
130 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
131 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
132 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
133 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
134
135 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
136 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
137 rd_addr);
138 }
139
xgene_enet_ecc_init(struct xgene_enet_pdata * pdata)140 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
141 {
142 struct net_device *ndev = pdata->ndev;
143 u32 data;
144 u8 wait = 10;
145
146 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
147 do {
148 usleep_range(100, 110);
149 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
150 } while ((data != 0xffffffff) && wait--);
151
152 if (data != 0xffffffff) {
153 netdev_err(ndev, "Failed to release memory from shutdown\n");
154 return -ENODEV;
155 }
156
157 return 0;
158 }
159
xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata * pdata)160 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
161 {
162 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
163 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
164 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
165 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
166 }
167
xgene_xgmac_reset(struct xgene_enet_pdata * pdata)168 static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
169 {
170 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
171 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
172 }
173
xgene_xgmac_set_mac_addr(struct xgene_enet_pdata * pdata)174 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
175 {
176 u32 addr0, addr1;
177 u8 *dev_addr = pdata->ndev->dev_addr;
178
179 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
180 (dev_addr[1] << 8) | dev_addr[0];
181 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
182
183 xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
184 xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
185 }
186
xgene_xgmac_set_mss(struct xgene_enet_pdata * pdata)187 static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
188 {
189 xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
190 }
191
xgene_enet_link_status(struct xgene_enet_pdata * pdata)192 static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
193 {
194 u32 data;
195
196 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
197
198 return data;
199 }
200
xgene_xgmac_init(struct xgene_enet_pdata * pdata)201 static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
202 {
203 u32 data;
204
205 xgene_xgmac_reset(pdata);
206
207 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
208 data |= HSTPPEN;
209 data &= ~HSTLENCHK;
210 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
211
212 xgene_xgmac_set_mac_addr(pdata);
213 xgene_xgmac_set_mss(pdata);
214
215 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
216 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
217 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
218
219 xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
220 xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
221 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
222 data |= BIT(12);
223 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
224 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
225 }
226
xgene_xgmac_rx_enable(struct xgene_enet_pdata * pdata)227 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
228 {
229 u32 data;
230
231 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
232 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
233 }
234
xgene_xgmac_tx_enable(struct xgene_enet_pdata * pdata)235 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
236 {
237 u32 data;
238
239 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
240 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
241 }
242
xgene_xgmac_rx_disable(struct xgene_enet_pdata * pdata)243 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
244 {
245 u32 data;
246
247 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
248 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
249 }
250
xgene_xgmac_tx_disable(struct xgene_enet_pdata * pdata)251 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
252 {
253 u32 data;
254
255 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
256 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
257 }
258
xgene_enet_reset(struct xgene_enet_pdata * pdata)259 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
260 {
261 if (!xgene_ring_mgr_init(pdata))
262 return -ENODEV;
263
264 if (!IS_ERR(pdata->clk)) {
265 clk_prepare_enable(pdata->clk);
266 clk_disable_unprepare(pdata->clk);
267 clk_prepare_enable(pdata->clk);
268 }
269
270 xgene_enet_ecc_init(pdata);
271 xgene_enet_config_ring_if_assoc(pdata);
272
273 return 0;
274 }
275
xgene_enet_xgcle_bypass(struct xgene_enet_pdata * pdata,u32 dst_ring_num,u16 bufpool_id)276 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
277 u32 dst_ring_num, u16 bufpool_id)
278 {
279 u32 cb, fpsel;
280
281 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
282 cb |= CFG_CLE_BYPASS_EN0;
283 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
284 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
285
286 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
287 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
288 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
289 CFG_CLE_FPSEL0_SET(&cb, fpsel);
290 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
291 }
292
xgene_enet_shutdown(struct xgene_enet_pdata * pdata)293 static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
294 {
295 if (!IS_ERR(pdata->clk))
296 clk_disable_unprepare(pdata->clk);
297 }
298
xgene_enet_link_state(struct work_struct * work)299 static void xgene_enet_link_state(struct work_struct *work)
300 {
301 struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
302 struct xgene_enet_pdata, link_work);
303 struct net_device *ndev = pdata->ndev;
304 u32 link_status, poll_interval;
305
306 link_status = xgene_enet_link_status(pdata);
307 if (link_status) {
308 if (!netif_carrier_ok(ndev)) {
309 netif_carrier_on(ndev);
310 xgene_xgmac_init(pdata);
311 xgene_xgmac_rx_enable(pdata);
312 xgene_xgmac_tx_enable(pdata);
313 netdev_info(ndev, "Link is Up - 10Gbps\n");
314 }
315 poll_interval = PHY_POLL_LINK_ON;
316 } else {
317 if (netif_carrier_ok(ndev)) {
318 xgene_xgmac_rx_disable(pdata);
319 xgene_xgmac_tx_disable(pdata);
320 netif_carrier_off(ndev);
321 netdev_info(ndev, "Link is Down\n");
322 }
323 poll_interval = PHY_POLL_LINK_OFF;
324 }
325
326 schedule_delayed_work(&pdata->link_work, poll_interval);
327 }
328
329 struct xgene_mac_ops xgene_xgmac_ops = {
330 .init = xgene_xgmac_init,
331 .reset = xgene_xgmac_reset,
332 .rx_enable = xgene_xgmac_rx_enable,
333 .tx_enable = xgene_xgmac_tx_enable,
334 .rx_disable = xgene_xgmac_rx_disable,
335 .tx_disable = xgene_xgmac_tx_disable,
336 .set_mac_addr = xgene_xgmac_set_mac_addr,
337 .set_mss = xgene_xgmac_set_mss,
338 .link_state = xgene_enet_link_state
339 };
340
341 struct xgene_port_ops xgene_xgport_ops = {
342 .reset = xgene_enet_reset,
343 .cle_bypass = xgene_enet_xgcle_bypass,
344 .shutdown = xgene_enet_shutdown,
345 };
346