1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/phy.h>
118 #include <linux/mdio.h>
119 #include <linux/clk.h>
120 #include <linux/bitrev.h>
121 #include <linux/crc32.h>
122
123 #include "xgbe.h"
124 #include "xgbe-common.h"
125
xgbe_usec_to_riwt(struct xgbe_prv_data * pdata,unsigned int usec)126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
127 unsigned int usec)
128 {
129 unsigned long rate;
130 unsigned int ret;
131
132 DBGPR("-->xgbe_usec_to_riwt\n");
133
134 rate = pdata->sysclk_rate;
135
136 /*
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
141 */
142 ret = (usec * (rate / 1000000)) / 256;
143
144 DBGPR("<--xgbe_usec_to_riwt\n");
145
146 return ret;
147 }
148
xgbe_riwt_to_usec(struct xgbe_prv_data * pdata,unsigned int riwt)149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
150 unsigned int riwt)
151 {
152 unsigned long rate;
153 unsigned int ret;
154
155 DBGPR("-->xgbe_riwt_to_usec\n");
156
157 rate = pdata->sysclk_rate;
158
159 /*
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
164 */
165 ret = (riwt * 256) / (rate / 1000000);
166
167 DBGPR("<--xgbe_riwt_to_usec\n");
168
169 return ret;
170 }
171
xgbe_config_pblx8(struct xgbe_prv_data * pdata)172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
173 {
174 struct xgbe_channel *channel;
175 unsigned int i;
176
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
180 pdata->pblx8);
181
182 return 0;
183 }
184
xgbe_get_tx_pbl_val(struct xgbe_prv_data * pdata)185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
186 {
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
188 }
189
xgbe_config_tx_pbl_val(struct xgbe_prv_data * pdata)190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
191 {
192 struct xgbe_channel *channel;
193 unsigned int i;
194
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
198 break;
199
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
201 pdata->tx_pbl);
202 }
203
204 return 0;
205 }
206
xgbe_get_rx_pbl_val(struct xgbe_prv_data * pdata)207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
208 {
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
210 }
211
xgbe_config_rx_pbl_val(struct xgbe_prv_data * pdata)212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
213 {
214 struct xgbe_channel *channel;
215 unsigned int i;
216
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
220 break;
221
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
223 pdata->rx_pbl);
224 }
225
226 return 0;
227 }
228
xgbe_config_osp_mode(struct xgbe_prv_data * pdata)229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
230 {
231 struct xgbe_channel *channel;
232 unsigned int i;
233
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
237 break;
238
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
240 pdata->tx_osp_mode);
241 }
242
243 return 0;
244 }
245
xgbe_config_rsf_mode(struct xgbe_prv_data * pdata,unsigned int val)246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
247 {
248 unsigned int i;
249
250 for (i = 0; i < pdata->rx_q_count; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
252
253 return 0;
254 }
255
xgbe_config_tsf_mode(struct xgbe_prv_data * pdata,unsigned int val)256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
257 {
258 unsigned int i;
259
260 for (i = 0; i < pdata->tx_q_count; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
262
263 return 0;
264 }
265
xgbe_config_rx_threshold(struct xgbe_prv_data * pdata,unsigned int val)266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
267 unsigned int val)
268 {
269 unsigned int i;
270
271 for (i = 0; i < pdata->rx_q_count; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
273
274 return 0;
275 }
276
xgbe_config_tx_threshold(struct xgbe_prv_data * pdata,unsigned int val)277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
278 unsigned int val)
279 {
280 unsigned int i;
281
282 for (i = 0; i < pdata->tx_q_count; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
284
285 return 0;
286 }
287
xgbe_config_rx_coalesce(struct xgbe_prv_data * pdata)288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
289 {
290 struct xgbe_channel *channel;
291 unsigned int i;
292
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
296 break;
297
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
299 pdata->rx_riwt);
300 }
301
302 return 0;
303 }
304
xgbe_config_tx_coalesce(struct xgbe_prv_data * pdata)305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
306 {
307 return 0;
308 }
309
xgbe_config_rx_buffer_size(struct xgbe_prv_data * pdata)310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
311 {
312 struct xgbe_channel *channel;
313 unsigned int i;
314
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
318 break;
319
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
321 pdata->rx_buf_size);
322 }
323 }
324
xgbe_config_tso_mode(struct xgbe_prv_data * pdata)325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
326 {
327 struct xgbe_channel *channel;
328 unsigned int i;
329
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
333 break;
334
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
336 }
337 }
338
xgbe_config_sph_mode(struct xgbe_prv_data * pdata)339 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
340 {
341 struct xgbe_channel *channel;
342 unsigned int i;
343
344 channel = pdata->channel;
345 for (i = 0; i < pdata->channel_count; i++, channel++) {
346 if (!channel->rx_ring)
347 break;
348
349 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
350 }
351
352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
353 }
354
xgbe_write_rss_reg(struct xgbe_prv_data * pdata,unsigned int type,unsigned int index,unsigned int val)355 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
356 unsigned int index, unsigned int val)
357 {
358 unsigned int wait;
359 int ret = 0;
360
361 mutex_lock(&pdata->rss_mutex);
362
363 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
364 ret = -EBUSY;
365 goto unlock;
366 }
367
368 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
369
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
373 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
374
375 wait = 1000;
376 while (wait--) {
377 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
378 goto unlock;
379
380 usleep_range(1000, 1500);
381 }
382
383 ret = -EBUSY;
384
385 unlock:
386 mutex_unlock(&pdata->rss_mutex);
387
388 return ret;
389 }
390
xgbe_write_rss_hash_key(struct xgbe_prv_data * pdata)391 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
392 {
393 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
394 unsigned int *key = (unsigned int *)&pdata->rss_key;
395 int ret;
396
397 while (key_regs--) {
398 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
399 key_regs, *key++);
400 if (ret)
401 return ret;
402 }
403
404 return 0;
405 }
406
xgbe_write_rss_lookup_table(struct xgbe_prv_data * pdata)407 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
408 {
409 unsigned int i;
410 int ret;
411
412 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
413 ret = xgbe_write_rss_reg(pdata,
414 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
415 pdata->rss_table[i]);
416 if (ret)
417 return ret;
418 }
419
420 return 0;
421 }
422
xgbe_set_rss_hash_key(struct xgbe_prv_data * pdata,const u8 * key)423 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
424 {
425 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
426
427 return xgbe_write_rss_hash_key(pdata);
428 }
429
xgbe_set_rss_lookup_table(struct xgbe_prv_data * pdata,const u32 * table)430 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
431 const u32 *table)
432 {
433 unsigned int i;
434
435 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
436 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
437
438 return xgbe_write_rss_lookup_table(pdata);
439 }
440
xgbe_enable_rss(struct xgbe_prv_data * pdata)441 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
442 {
443 int ret;
444
445 if (!pdata->hw_feat.rss)
446 return -EOPNOTSUPP;
447
448 /* Program the hash key */
449 ret = xgbe_write_rss_hash_key(pdata);
450 if (ret)
451 return ret;
452
453 /* Program the lookup table */
454 ret = xgbe_write_rss_lookup_table(pdata);
455 if (ret)
456 return ret;
457
458 /* Set the RSS options */
459 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
460
461 /* Enable RSS */
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
463
464 return 0;
465 }
466
xgbe_disable_rss(struct xgbe_prv_data * pdata)467 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
468 {
469 if (!pdata->hw_feat.rss)
470 return -EOPNOTSUPP;
471
472 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
473
474 return 0;
475 }
476
xgbe_config_rss(struct xgbe_prv_data * pdata)477 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
478 {
479 int ret;
480
481 if (!pdata->hw_feat.rss)
482 return;
483
484 if (pdata->netdev->features & NETIF_F_RXHASH)
485 ret = xgbe_enable_rss(pdata);
486 else
487 ret = xgbe_disable_rss(pdata);
488
489 if (ret)
490 netdev_err(pdata->netdev,
491 "error configuring RSS, RSS disabled\n");
492 }
493
xgbe_disable_tx_flow_control(struct xgbe_prv_data * pdata)494 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
495 {
496 unsigned int max_q_count, q_count;
497 unsigned int reg, reg_val;
498 unsigned int i;
499
500 /* Clear MTL flow control */
501 for (i = 0; i < pdata->rx_q_count; i++)
502 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
503
504 /* Clear MAC flow control */
505 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
506 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
507 reg = MAC_Q0TFCR;
508 for (i = 0; i < q_count; i++) {
509 reg_val = XGMAC_IOREAD(pdata, reg);
510 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
511 XGMAC_IOWRITE(pdata, reg, reg_val);
512
513 reg += MAC_QTFCR_INC;
514 }
515
516 return 0;
517 }
518
xgbe_enable_tx_flow_control(struct xgbe_prv_data * pdata)519 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
520 {
521 unsigned int max_q_count, q_count;
522 unsigned int reg, reg_val;
523 unsigned int i;
524
525 /* Set MTL flow control */
526 for (i = 0; i < pdata->rx_q_count; i++)
527 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
528
529 /* Set MAC flow control */
530 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
531 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
532 reg = MAC_Q0TFCR;
533 for (i = 0; i < q_count; i++) {
534 reg_val = XGMAC_IOREAD(pdata, reg);
535
536 /* Enable transmit flow control */
537 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
538 /* Set pause time */
539 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
540
541 XGMAC_IOWRITE(pdata, reg, reg_val);
542
543 reg += MAC_QTFCR_INC;
544 }
545
546 return 0;
547 }
548
xgbe_disable_rx_flow_control(struct xgbe_prv_data * pdata)549 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
550 {
551 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
552
553 return 0;
554 }
555
xgbe_enable_rx_flow_control(struct xgbe_prv_data * pdata)556 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
557 {
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
559
560 return 0;
561 }
562
xgbe_config_tx_flow_control(struct xgbe_prv_data * pdata)563 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
564 {
565 struct ieee_pfc *pfc = pdata->pfc;
566
567 if (pdata->tx_pause || (pfc && pfc->pfc_en))
568 xgbe_enable_tx_flow_control(pdata);
569 else
570 xgbe_disable_tx_flow_control(pdata);
571
572 return 0;
573 }
574
xgbe_config_rx_flow_control(struct xgbe_prv_data * pdata)575 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
576 {
577 struct ieee_pfc *pfc = pdata->pfc;
578
579 if (pdata->rx_pause || (pfc && pfc->pfc_en))
580 xgbe_enable_rx_flow_control(pdata);
581 else
582 xgbe_disable_rx_flow_control(pdata);
583
584 return 0;
585 }
586
xgbe_config_flow_control(struct xgbe_prv_data * pdata)587 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
588 {
589 struct ieee_pfc *pfc = pdata->pfc;
590
591 xgbe_config_tx_flow_control(pdata);
592 xgbe_config_rx_flow_control(pdata);
593
594 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
595 (pfc && pfc->pfc_en) ? 1 : 0);
596 }
597
xgbe_enable_dma_interrupts(struct xgbe_prv_data * pdata)598 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
599 {
600 struct xgbe_channel *channel;
601 unsigned int dma_ch_isr, dma_ch_ier;
602 unsigned int i;
603
604 channel = pdata->channel;
605 for (i = 0; i < pdata->channel_count; i++, channel++) {
606 /* Clear all the interrupts which are set */
607 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
608 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
609
610 /* Clear all interrupt enable bits */
611 dma_ch_ier = 0;
612
613 /* Enable following interrupts
614 * NIE - Normal Interrupt Summary Enable
615 * AIE - Abnormal Interrupt Summary Enable
616 * FBEE - Fatal Bus Error Enable
617 */
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
620 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
621
622 if (channel->tx_ring) {
623 /* Enable the following Tx interrupts
624 * TIE - Transmit Interrupt Enable (unless using
625 * per channel interrupts)
626 */
627 if (!pdata->per_channel_irq)
628 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
629 }
630 if (channel->rx_ring) {
631 /* Enable following Rx interrupts
632 * RBUE - Receive Buffer Unavailable Enable
633 * RIE - Receive Interrupt Enable (unless using
634 * per channel interrupts)
635 */
636 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
637 if (!pdata->per_channel_irq)
638 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
639 }
640
641 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
642 }
643 }
644
xgbe_enable_mtl_interrupts(struct xgbe_prv_data * pdata)645 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
646 {
647 unsigned int mtl_q_isr;
648 unsigned int q_count, i;
649
650 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
651 for (i = 0; i < q_count; i++) {
652 /* Clear all the interrupts which are set */
653 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
654 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
655
656 /* No MTL interrupts to be enabled */
657 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
658 }
659 }
660
xgbe_enable_mac_interrupts(struct xgbe_prv_data * pdata)661 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
662 {
663 unsigned int mac_ier = 0;
664
665 /* Enable Timestamp interrupt */
666 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
667
668 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
669
670 /* Enable all counter interrupts */
671 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
672 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
673 }
674
xgbe_set_gmii_speed(struct xgbe_prv_data * pdata)675 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
676 {
677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
678 return 0;
679
680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
681
682 return 0;
683 }
684
xgbe_set_gmii_2500_speed(struct xgbe_prv_data * pdata)685 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
686 {
687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
688 return 0;
689
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
691
692 return 0;
693 }
694
xgbe_set_xgmii_speed(struct xgbe_prv_data * pdata)695 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
696 {
697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
698 return 0;
699
700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
701
702 return 0;
703 }
704
xgbe_set_promiscuous_mode(struct xgbe_prv_data * pdata,unsigned int enable)705 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
706 unsigned int enable)
707 {
708 unsigned int val = enable ? 1 : 0;
709
710 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
711 return 0;
712
713 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
714 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
715
716 return 0;
717 }
718
xgbe_set_all_multicast_mode(struct xgbe_prv_data * pdata,unsigned int enable)719 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
720 unsigned int enable)
721 {
722 unsigned int val = enable ? 1 : 0;
723
724 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
725 return 0;
726
727 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
728 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
729
730 return 0;
731 }
732
xgbe_set_mac_reg(struct xgbe_prv_data * pdata,struct netdev_hw_addr * ha,unsigned int * mac_reg)733 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
734 struct netdev_hw_addr *ha, unsigned int *mac_reg)
735 {
736 unsigned int mac_addr_hi, mac_addr_lo;
737 u8 *mac_addr;
738
739 mac_addr_lo = 0;
740 mac_addr_hi = 0;
741
742 if (ha) {
743 mac_addr = (u8 *)&mac_addr_lo;
744 mac_addr[0] = ha->addr[0];
745 mac_addr[1] = ha->addr[1];
746 mac_addr[2] = ha->addr[2];
747 mac_addr[3] = ha->addr[3];
748 mac_addr = (u8 *)&mac_addr_hi;
749 mac_addr[0] = ha->addr[4];
750 mac_addr[1] = ha->addr[5];
751
752 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
753 *mac_reg);
754
755 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
756 }
757
758 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
759 *mac_reg += MAC_MACA_INC;
760 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
761 *mac_reg += MAC_MACA_INC;
762 }
763
xgbe_set_mac_addn_addrs(struct xgbe_prv_data * pdata)764 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
765 {
766 struct net_device *netdev = pdata->netdev;
767 struct netdev_hw_addr *ha;
768 unsigned int mac_reg;
769 unsigned int addn_macs;
770
771 mac_reg = MAC_MACA1HR;
772 addn_macs = pdata->hw_feat.addn_mac;
773
774 if (netdev_uc_count(netdev) > addn_macs) {
775 xgbe_set_promiscuous_mode(pdata, 1);
776 } else {
777 netdev_for_each_uc_addr(ha, netdev) {
778 xgbe_set_mac_reg(pdata, ha, &mac_reg);
779 addn_macs--;
780 }
781
782 if (netdev_mc_count(netdev) > addn_macs) {
783 xgbe_set_all_multicast_mode(pdata, 1);
784 } else {
785 netdev_for_each_mc_addr(ha, netdev) {
786 xgbe_set_mac_reg(pdata, ha, &mac_reg);
787 addn_macs--;
788 }
789 }
790 }
791
792 /* Clear remaining additional MAC address entries */
793 while (addn_macs--)
794 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
795 }
796
xgbe_set_mac_hash_table(struct xgbe_prv_data * pdata)797 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
798 {
799 struct net_device *netdev = pdata->netdev;
800 struct netdev_hw_addr *ha;
801 unsigned int hash_reg;
802 unsigned int hash_table_shift, hash_table_count;
803 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
804 u32 crc;
805 unsigned int i;
806
807 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
808 hash_table_count = pdata->hw_feat.hash_table_size / 32;
809 memset(hash_table, 0, sizeof(hash_table));
810
811 /* Build the MAC Hash Table register values */
812 netdev_for_each_uc_addr(ha, netdev) {
813 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
814 crc >>= hash_table_shift;
815 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
816 }
817
818 netdev_for_each_mc_addr(ha, netdev) {
819 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
820 crc >>= hash_table_shift;
821 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
822 }
823
824 /* Set the MAC Hash Table registers */
825 hash_reg = MAC_HTR0;
826 for (i = 0; i < hash_table_count; i++) {
827 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
828 hash_reg += MAC_HTR_INC;
829 }
830 }
831
xgbe_add_mac_addresses(struct xgbe_prv_data * pdata)832 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
833 {
834 if (pdata->hw_feat.hash_table_size)
835 xgbe_set_mac_hash_table(pdata);
836 else
837 xgbe_set_mac_addn_addrs(pdata);
838
839 return 0;
840 }
841
xgbe_set_mac_address(struct xgbe_prv_data * pdata,u8 * addr)842 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
843 {
844 unsigned int mac_addr_hi, mac_addr_lo;
845
846 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
847 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
848 (addr[1] << 8) | (addr[0] << 0);
849
850 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
851 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
852
853 return 0;
854 }
855
xgbe_config_rx_mode(struct xgbe_prv_data * pdata)856 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
857 {
858 struct net_device *netdev = pdata->netdev;
859 unsigned int pr_mode, am_mode;
860
861 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
862 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
863
864 xgbe_set_promiscuous_mode(pdata, pr_mode);
865 xgbe_set_all_multicast_mode(pdata, am_mode);
866
867 xgbe_add_mac_addresses(pdata);
868
869 return 0;
870 }
871
xgbe_read_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)872 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
873 int mmd_reg)
874 {
875 unsigned int mmd_address;
876 int mmd_data;
877
878 if (mmd_reg & MII_ADDR_C45)
879 mmd_address = mmd_reg & ~MII_ADDR_C45;
880 else
881 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
882
883 /* The PCS registers are accessed using mmio. The underlying APB3
884 * management interface uses indirect addressing to access the MMD
885 * register sets. This requires accessing of the PCS register in two
886 * phases, an address phase and a data phase.
887 *
888 * The mmio interface is based on 32-bit offsets and values. All
889 * register offsets must therefore be adjusted by left shifting the
890 * offset 2 bits and reading 32 bits of data.
891 */
892 mutex_lock(&pdata->xpcs_mutex);
893 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
894 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
895 mutex_unlock(&pdata->xpcs_mutex);
896
897 return mmd_data;
898 }
899
xgbe_write_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)900 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
901 int mmd_reg, int mmd_data)
902 {
903 unsigned int mmd_address;
904
905 if (mmd_reg & MII_ADDR_C45)
906 mmd_address = mmd_reg & ~MII_ADDR_C45;
907 else
908 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
909
910 /* If the PCS is changing modes, match the MAC speed to it */
911 if (((mmd_address >> 16) == MDIO_MMD_PCS) &&
912 ((mmd_address & 0xffff) == MDIO_CTRL2)) {
913 struct phy_device *phydev = pdata->phydev;
914
915 if (mmd_data & MDIO_PCS_CTRL2_TYPE) {
916 /* KX mode */
917 if (phydev->supported & SUPPORTED_1000baseKX_Full)
918 xgbe_set_gmii_speed(pdata);
919 else
920 xgbe_set_gmii_2500_speed(pdata);
921 } else {
922 /* KR mode */
923 xgbe_set_xgmii_speed(pdata);
924 }
925 }
926
927 /* The PCS registers are accessed using mmio. The underlying APB3
928 * management interface uses indirect addressing to access the MMD
929 * register sets. This requires accessing of the PCS register in two
930 * phases, an address phase and a data phase.
931 *
932 * The mmio interface is based on 32-bit offsets and values. All
933 * register offsets must therefore be adjusted by left shifting the
934 * offset 2 bits and reading 32 bits of data.
935 */
936 mutex_lock(&pdata->xpcs_mutex);
937 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
938 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
939 mutex_unlock(&pdata->xpcs_mutex);
940 }
941
xgbe_tx_complete(struct xgbe_ring_desc * rdesc)942 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
943 {
944 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
945 }
946
xgbe_disable_rx_csum(struct xgbe_prv_data * pdata)947 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
948 {
949 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
950
951 return 0;
952 }
953
xgbe_enable_rx_csum(struct xgbe_prv_data * pdata)954 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
955 {
956 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
957
958 return 0;
959 }
960
xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data * pdata)961 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
962 {
963 /* Put the VLAN tag in the Rx descriptor */
964 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
965
966 /* Don't check the VLAN type */
967 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
968
969 /* Check only C-TAG (0x8100) packets */
970 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
971
972 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
973 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
974
975 /* Enable VLAN tag stripping */
976 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
977
978 return 0;
979 }
980
xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data * pdata)981 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
982 {
983 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
984
985 return 0;
986 }
987
xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data * pdata)988 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
989 {
990 /* Enable VLAN filtering */
991 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
992
993 /* Enable VLAN Hash Table filtering */
994 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
995
996 /* Disable VLAN tag inverse matching */
997 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
998
999 /* Only filter on the lower 12-bits of the VLAN tag */
1000 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
1001
1002 /* In order for the VLAN Hash Table filtering to be effective,
1003 * the VLAN tag identifier in the VLAN Tag Register must not
1004 * be zero. Set the VLAN tag identifier to "1" to enable the
1005 * VLAN Hash Table filtering. This implies that a VLAN tag of
1006 * 1 will always pass filtering.
1007 */
1008 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
1009
1010 return 0;
1011 }
1012
xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data * pdata)1013 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
1014 {
1015 /* Disable VLAN filtering */
1016 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
1017
1018 return 0;
1019 }
1020
1021 #ifndef CRCPOLY_LE
1022 #define CRCPOLY_LE 0xedb88320
1023 #endif
xgbe_vid_crc32_le(__le16 vid_le)1024 static u32 xgbe_vid_crc32_le(__le16 vid_le)
1025 {
1026 u32 poly = CRCPOLY_LE;
1027 u32 crc = ~0;
1028 u32 temp = 0;
1029 unsigned char *data = (unsigned char *)&vid_le;
1030 unsigned char data_byte = 0;
1031 int i, bits;
1032
1033 bits = get_bitmask_order(VLAN_VID_MASK);
1034 for (i = 0; i < bits; i++) {
1035 if ((i % 8) == 0)
1036 data_byte = data[i / 8];
1037
1038 temp = ((crc & 1) ^ data_byte) & 1;
1039 crc >>= 1;
1040 data_byte >>= 1;
1041
1042 if (temp)
1043 crc ^= poly;
1044 }
1045
1046 return crc;
1047 }
1048
xgbe_update_vlan_hash_table(struct xgbe_prv_data * pdata)1049 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1050 {
1051 u32 crc;
1052 u16 vid;
1053 __le16 vid_le;
1054 u16 vlan_hash_table = 0;
1055
1056 /* Generate the VLAN Hash Table value */
1057 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1058 /* Get the CRC32 value of the VLAN ID */
1059 vid_le = cpu_to_le16(vid);
1060 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1061
1062 vlan_hash_table |= (1 << crc);
1063 }
1064
1065 /* Set the VLAN Hash Table filtering register */
1066 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1067
1068 return 0;
1069 }
1070
xgbe_tx_desc_reset(struct xgbe_ring_data * rdata)1071 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1072 {
1073 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1074
1075 /* Reset the Tx descriptor
1076 * Set buffer 1 (lo) address to zero
1077 * Set buffer 1 (hi) address to zero
1078 * Reset all other control bits (IC, TTSE, B2L & B1L)
1079 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1080 */
1081 rdesc->desc0 = 0;
1082 rdesc->desc1 = 0;
1083 rdesc->desc2 = 0;
1084 rdesc->desc3 = 0;
1085
1086 /* Make sure ownership is written to the descriptor */
1087 dma_wmb();
1088 }
1089
xgbe_tx_desc_init(struct xgbe_channel * channel)1090 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1091 {
1092 struct xgbe_ring *ring = channel->tx_ring;
1093 struct xgbe_ring_data *rdata;
1094 int i;
1095 int start_index = ring->cur;
1096
1097 DBGPR("-->tx_desc_init\n");
1098
1099 /* Initialze all descriptors */
1100 for (i = 0; i < ring->rdesc_count; i++) {
1101 rdata = XGBE_GET_DESC_DATA(ring, i);
1102
1103 /* Initialize Tx descriptor */
1104 xgbe_tx_desc_reset(rdata);
1105 }
1106
1107 /* Update the total number of Tx descriptors */
1108 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1109
1110 /* Update the starting address of descriptor ring */
1111 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1112 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1113 upper_32_bits(rdata->rdesc_dma));
1114 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1115 lower_32_bits(rdata->rdesc_dma));
1116
1117 DBGPR("<--tx_desc_init\n");
1118 }
1119
xgbe_rx_desc_reset(struct xgbe_prv_data * pdata,struct xgbe_ring_data * rdata,unsigned int index)1120 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1121 struct xgbe_ring_data *rdata, unsigned int index)
1122 {
1123 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1124 unsigned int rx_usecs = pdata->rx_usecs;
1125 unsigned int rx_frames = pdata->rx_frames;
1126 unsigned int inte;
1127
1128 if (!rx_usecs && !rx_frames) {
1129 /* No coalescing, interrupt for every descriptor */
1130 inte = 1;
1131 } else {
1132 /* Set interrupt based on Rx frame coalescing setting */
1133 if (rx_frames && !((index + 1) % rx_frames))
1134 inte = 1;
1135 else
1136 inte = 0;
1137 }
1138
1139 /* Reset the Rx descriptor
1140 * Set buffer 1 (lo) address to header dma address (lo)
1141 * Set buffer 1 (hi) address to header dma address (hi)
1142 * Set buffer 2 (lo) address to buffer dma address (lo)
1143 * Set buffer 2 (hi) address to buffer dma address (hi) and
1144 * set control bits OWN and INTE
1145 */
1146 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma));
1147 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma));
1148 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma));
1149 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma));
1150
1151 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
1152
1153 /* Since the Rx DMA engine is likely running, make sure everything
1154 * is written to the descriptor(s) before setting the OWN bit
1155 * for the descriptor
1156 */
1157 dma_wmb();
1158
1159 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1160
1161 /* Make sure ownership is written to the descriptor */
1162 dma_wmb();
1163 }
1164
xgbe_rx_desc_init(struct xgbe_channel * channel)1165 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1166 {
1167 struct xgbe_prv_data *pdata = channel->pdata;
1168 struct xgbe_ring *ring = channel->rx_ring;
1169 struct xgbe_ring_data *rdata;
1170 unsigned int start_index = ring->cur;
1171 unsigned int i;
1172
1173 DBGPR("-->rx_desc_init\n");
1174
1175 /* Initialize all descriptors */
1176 for (i = 0; i < ring->rdesc_count; i++) {
1177 rdata = XGBE_GET_DESC_DATA(ring, i);
1178
1179 /* Initialize Rx descriptor */
1180 xgbe_rx_desc_reset(pdata, rdata, i);
1181 }
1182
1183 /* Update the total number of Rx descriptors */
1184 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1185
1186 /* Update the starting address of descriptor ring */
1187 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1188 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1189 upper_32_bits(rdata->rdesc_dma));
1190 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1191 lower_32_bits(rdata->rdesc_dma));
1192
1193 /* Update the Rx Descriptor Tail Pointer */
1194 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1195 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1196 lower_32_bits(rdata->rdesc_dma));
1197
1198 DBGPR("<--rx_desc_init\n");
1199 }
1200
xgbe_update_tstamp_addend(struct xgbe_prv_data * pdata,unsigned int addend)1201 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1202 unsigned int addend)
1203 {
1204 /* Set the addend register value and tell the device */
1205 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1206 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1207
1208 /* Wait for addend update to complete */
1209 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1210 udelay(5);
1211 }
1212
xgbe_set_tstamp_time(struct xgbe_prv_data * pdata,unsigned int sec,unsigned int nsec)1213 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1214 unsigned int nsec)
1215 {
1216 /* Set the time values and tell the device */
1217 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1218 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1219 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1220
1221 /* Wait for time update to complete */
1222 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1223 udelay(5);
1224 }
1225
xgbe_get_tstamp_time(struct xgbe_prv_data * pdata)1226 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1227 {
1228 u64 nsec;
1229
1230 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1231 nsec *= NSEC_PER_SEC;
1232 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1233
1234 return nsec;
1235 }
1236
xgbe_get_tx_tstamp(struct xgbe_prv_data * pdata)1237 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1238 {
1239 unsigned int tx_snr;
1240 u64 nsec;
1241
1242 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1243 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1244 return 0;
1245
1246 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1247 nsec *= NSEC_PER_SEC;
1248 nsec += tx_snr;
1249
1250 return nsec;
1251 }
1252
xgbe_get_rx_tstamp(struct xgbe_packet_data * packet,struct xgbe_ring_desc * rdesc)1253 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1254 struct xgbe_ring_desc *rdesc)
1255 {
1256 u64 nsec;
1257
1258 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1259 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1260 nsec = le32_to_cpu(rdesc->desc1);
1261 nsec <<= 32;
1262 nsec |= le32_to_cpu(rdesc->desc0);
1263 if (nsec != 0xffffffffffffffffULL) {
1264 packet->rx_tstamp = nsec;
1265 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1266 RX_TSTAMP, 1);
1267 }
1268 }
1269 }
1270
xgbe_config_tstamp(struct xgbe_prv_data * pdata,unsigned int mac_tscr)1271 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1272 unsigned int mac_tscr)
1273 {
1274 /* Set one nano-second accuracy */
1275 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1276
1277 /* Set fine timestamp update */
1278 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1279
1280 /* Overwrite earlier timestamps */
1281 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1282
1283 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1284
1285 /* Exit if timestamping is not enabled */
1286 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1287 return 0;
1288
1289 /* Initialize time registers */
1290 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1291 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1292 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1293 xgbe_set_tstamp_time(pdata, 0, 0);
1294
1295 /* Initialize the timecounter */
1296 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1297 ktime_to_ns(ktime_get_real()));
1298
1299 return 0;
1300 }
1301
xgbe_config_dcb_tc(struct xgbe_prv_data * pdata)1302 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1303 {
1304 struct ieee_ets *ets = pdata->ets;
1305 unsigned int total_weight, min_weight, weight;
1306 unsigned int i;
1307
1308 if (!ets)
1309 return;
1310
1311 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1312 * traffic class is using ETS algorithm)
1313 */
1314 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1315
1316 /* Set Traffic Class algorithms */
1317 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1318 min_weight = total_weight / 100;
1319 if (!min_weight)
1320 min_weight = 1;
1321
1322 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1323 switch (ets->tc_tsa[i]) {
1324 case IEEE_8021QAZ_TSA_STRICT:
1325 DBGPR(" TC%u using SP\n", i);
1326 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1327 MTL_TSA_SP);
1328 break;
1329 case IEEE_8021QAZ_TSA_ETS:
1330 weight = total_weight * ets->tc_tx_bw[i] / 100;
1331 weight = clamp(weight, min_weight, total_weight);
1332
1333 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1334 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1335 MTL_TSA_ETS);
1336 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1337 weight);
1338 break;
1339 }
1340 }
1341 }
1342
xgbe_config_dcb_pfc(struct xgbe_prv_data * pdata)1343 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1344 {
1345 struct ieee_pfc *pfc = pdata->pfc;
1346 struct ieee_ets *ets = pdata->ets;
1347 unsigned int mask, reg, reg_val;
1348 unsigned int tc, prio;
1349
1350 if (!pfc || !ets)
1351 return;
1352
1353 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1354 mask = 0;
1355 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1356 if ((pfc->pfc_en & (1 << prio)) &&
1357 (ets->prio_tc[prio] == tc))
1358 mask |= (1 << prio);
1359 }
1360 mask &= 0xff;
1361
1362 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1363 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1364 reg_val = XGMAC_IOREAD(pdata, reg);
1365
1366 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1367 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1368
1369 XGMAC_IOWRITE(pdata, reg, reg_val);
1370 }
1371
1372 xgbe_config_flow_control(pdata);
1373 }
1374
xgbe_tx_start_xmit(struct xgbe_channel * channel,struct xgbe_ring * ring)1375 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1376 struct xgbe_ring *ring)
1377 {
1378 struct xgbe_prv_data *pdata = channel->pdata;
1379 struct xgbe_ring_data *rdata;
1380
1381 /* Make sure everything is written before the register write */
1382 wmb();
1383
1384 /* Issue a poll command to Tx DMA by writing address
1385 * of next immediate free descriptor */
1386 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1387 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1388 lower_32_bits(rdata->rdesc_dma));
1389
1390 /* Start the Tx timer */
1391 if (pdata->tx_usecs && !channel->tx_timer_active) {
1392 channel->tx_timer_active = 1;
1393 mod_timer(&channel->tx_timer,
1394 jiffies + usecs_to_jiffies(pdata->tx_usecs));
1395 }
1396
1397 ring->tx.xmit_more = 0;
1398 }
1399
xgbe_dev_xmit(struct xgbe_channel * channel)1400 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1401 {
1402 struct xgbe_prv_data *pdata = channel->pdata;
1403 struct xgbe_ring *ring = channel->tx_ring;
1404 struct xgbe_ring_data *rdata;
1405 struct xgbe_ring_desc *rdesc;
1406 struct xgbe_packet_data *packet = &ring->packet_data;
1407 unsigned int csum, tso, vlan;
1408 unsigned int tso_context, vlan_context;
1409 unsigned int tx_set_ic;
1410 int start_index = ring->cur;
1411 int cur_index = ring->cur;
1412 int i;
1413
1414 DBGPR("-->xgbe_dev_xmit\n");
1415
1416 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1417 CSUM_ENABLE);
1418 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1419 TSO_ENABLE);
1420 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1421 VLAN_CTAG);
1422
1423 if (tso && (packet->mss != ring->tx.cur_mss))
1424 tso_context = 1;
1425 else
1426 tso_context = 0;
1427
1428 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1429 vlan_context = 1;
1430 else
1431 vlan_context = 0;
1432
1433 /* Determine if an interrupt should be generated for this Tx:
1434 * Interrupt:
1435 * - Tx frame count exceeds the frame count setting
1436 * - Addition of Tx frame count to the frame count since the
1437 * last interrupt was set exceeds the frame count setting
1438 * No interrupt:
1439 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1440 * - Addition of Tx frame count to the frame count since the
1441 * last interrupt was set does not exceed the frame count setting
1442 */
1443 ring->coalesce_count += packet->tx_packets;
1444 if (!pdata->tx_frames)
1445 tx_set_ic = 0;
1446 else if (packet->tx_packets > pdata->tx_frames)
1447 tx_set_ic = 1;
1448 else if ((ring->coalesce_count % pdata->tx_frames) <
1449 packet->tx_packets)
1450 tx_set_ic = 1;
1451 else
1452 tx_set_ic = 0;
1453
1454 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1455 rdesc = rdata->rdesc;
1456
1457 /* Create a context descriptor if this is a TSO packet */
1458 if (tso_context || vlan_context) {
1459 if (tso_context) {
1460 DBGPR(" TSO context descriptor, mss=%u\n",
1461 packet->mss);
1462
1463 /* Set the MSS size */
1464 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1465 MSS, packet->mss);
1466
1467 /* Mark it as a CONTEXT descriptor */
1468 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1469 CTXT, 1);
1470
1471 /* Indicate this descriptor contains the MSS */
1472 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1473 TCMSSV, 1);
1474
1475 ring->tx.cur_mss = packet->mss;
1476 }
1477
1478 if (vlan_context) {
1479 DBGPR(" VLAN context descriptor, ctag=%u\n",
1480 packet->vlan_ctag);
1481
1482 /* Mark it as a CONTEXT descriptor */
1483 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1484 CTXT, 1);
1485
1486 /* Set the VLAN tag */
1487 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1488 VT, packet->vlan_ctag);
1489
1490 /* Indicate this descriptor contains the VLAN tag */
1491 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1492 VLTV, 1);
1493
1494 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1495 }
1496
1497 cur_index++;
1498 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1499 rdesc = rdata->rdesc;
1500 }
1501
1502 /* Update buffer address (for TSO this is the header) */
1503 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1504 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1505
1506 /* Update the buffer length */
1507 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1508 rdata->skb_dma_len);
1509
1510 /* VLAN tag insertion check */
1511 if (vlan)
1512 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1513 TX_NORMAL_DESC2_VLAN_INSERT);
1514
1515 /* Timestamp enablement check */
1516 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1517 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1518
1519 /* Mark it as First Descriptor */
1520 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1521
1522 /* Mark it as a NORMAL descriptor */
1523 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1524
1525 /* Set OWN bit if not the first descriptor */
1526 if (cur_index != start_index)
1527 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1528
1529 if (tso) {
1530 /* Enable TSO */
1531 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1532 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1533 packet->tcp_payload_len);
1534 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1535 packet->tcp_header_len / 4);
1536 } else {
1537 /* Enable CRC and Pad Insertion */
1538 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1539
1540 /* Enable HW CSUM */
1541 if (csum)
1542 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1543 CIC, 0x3);
1544
1545 /* Set the total length to be transmitted */
1546 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1547 packet->length);
1548 }
1549
1550 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1551 cur_index++;
1552 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1553 rdesc = rdata->rdesc;
1554
1555 /* Update buffer address */
1556 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1557 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1558
1559 /* Update the buffer length */
1560 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1561 rdata->skb_dma_len);
1562
1563 /* Set OWN bit */
1564 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1565
1566 /* Mark it as NORMAL descriptor */
1567 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1568
1569 /* Enable HW CSUM */
1570 if (csum)
1571 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1572 CIC, 0x3);
1573 }
1574
1575 /* Set LAST bit for the last descriptor */
1576 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1577
1578 /* Set IC bit based on Tx coalescing settings */
1579 if (tx_set_ic)
1580 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1581
1582 /* Save the Tx info to report back during cleanup */
1583 rdata->tx.packets = packet->tx_packets;
1584 rdata->tx.bytes = packet->tx_bytes;
1585
1586 /* In case the Tx DMA engine is running, make sure everything
1587 * is written to the descriptor(s) before setting the OWN bit
1588 * for the first descriptor
1589 */
1590 dma_wmb();
1591
1592 /* Set OWN bit for the first descriptor */
1593 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1594 rdesc = rdata->rdesc;
1595 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1596
1597 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1598 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1599 #endif
1600
1601 /* Make sure ownership is written to the descriptor */
1602 dma_wmb();
1603
1604 ring->cur = cur_index + 1;
1605 if (!packet->skb->xmit_more ||
1606 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1607 channel->queue_index)))
1608 xgbe_tx_start_xmit(channel, ring);
1609 else
1610 ring->tx.xmit_more = 1;
1611
1612 DBGPR(" %s: descriptors %u to %u written\n",
1613 channel->name, start_index & (ring->rdesc_count - 1),
1614 (ring->cur - 1) & (ring->rdesc_count - 1));
1615
1616 DBGPR("<--xgbe_dev_xmit\n");
1617 }
1618
xgbe_dev_read(struct xgbe_channel * channel)1619 static int xgbe_dev_read(struct xgbe_channel *channel)
1620 {
1621 struct xgbe_ring *ring = channel->rx_ring;
1622 struct xgbe_ring_data *rdata;
1623 struct xgbe_ring_desc *rdesc;
1624 struct xgbe_packet_data *packet = &ring->packet_data;
1625 struct net_device *netdev = channel->pdata->netdev;
1626 unsigned int err, etlt, l34t;
1627
1628 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1629
1630 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1631 rdesc = rdata->rdesc;
1632
1633 /* Check for data availability */
1634 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1635 return 1;
1636
1637 /* Make sure descriptor fields are read after reading the OWN bit */
1638 dma_rmb();
1639
1640 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1641 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1642 #endif
1643
1644 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1645 /* Timestamp Context Descriptor */
1646 xgbe_get_rx_tstamp(packet, rdesc);
1647
1648 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1649 CONTEXT, 1);
1650 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1651 CONTEXT_NEXT, 0);
1652 return 0;
1653 }
1654
1655 /* Normal Descriptor, be sure Context Descriptor bit is off */
1656 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1657
1658 /* Indicate if a Context Descriptor is next */
1659 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1660 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1661 CONTEXT_NEXT, 1);
1662
1663 /* Get the header length */
1664 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD))
1665 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1666 RX_NORMAL_DESC2, HL);
1667
1668 /* Get the RSS hash */
1669 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1670 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1671 RSS_HASH, 1);
1672
1673 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1674
1675 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1676 switch (l34t) {
1677 case RX_DESC3_L34T_IPV4_TCP:
1678 case RX_DESC3_L34T_IPV4_UDP:
1679 case RX_DESC3_L34T_IPV6_TCP:
1680 case RX_DESC3_L34T_IPV6_UDP:
1681 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1682 break;
1683 default:
1684 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1685 }
1686 }
1687
1688 /* Get the packet length */
1689 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1690
1691 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1692 /* Not all the data has been transferred for this packet */
1693 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1694 INCOMPLETE, 1);
1695 return 0;
1696 }
1697
1698 /* This is the last of the data for this packet */
1699 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1700 INCOMPLETE, 0);
1701
1702 /* Set checksum done indicator as appropriate */
1703 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1704 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1705 CSUM_DONE, 1);
1706
1707 /* Check for errors (only valid in last descriptor) */
1708 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1709 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1710 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1711
1712 if (!err || !etlt) {
1713 /* No error if err is 0 or etlt is 0 */
1714 if ((etlt == 0x09) &&
1715 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1716 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1717 VLAN_CTAG, 1);
1718 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1719 RX_NORMAL_DESC0,
1720 OVT);
1721 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1722 }
1723 } else {
1724 if ((etlt == 0x05) || (etlt == 0x06))
1725 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1726 CSUM_DONE, 0);
1727 else
1728 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1729 FRAME, 1);
1730 }
1731
1732 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1733 ring->cur & (ring->rdesc_count - 1), ring->cur);
1734
1735 return 0;
1736 }
1737
xgbe_is_context_desc(struct xgbe_ring_desc * rdesc)1738 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1739 {
1740 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1741 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1742 }
1743
xgbe_is_last_desc(struct xgbe_ring_desc * rdesc)1744 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1745 {
1746 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1747 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1748 }
1749
xgbe_enable_int(struct xgbe_channel * channel,enum xgbe_int int_id)1750 static int xgbe_enable_int(struct xgbe_channel *channel,
1751 enum xgbe_int int_id)
1752 {
1753 unsigned int dma_ch_ier;
1754
1755 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1756
1757 switch (int_id) {
1758 case XGMAC_INT_DMA_CH_SR_TI:
1759 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1760 break;
1761 case XGMAC_INT_DMA_CH_SR_TPS:
1762 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1763 break;
1764 case XGMAC_INT_DMA_CH_SR_TBU:
1765 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1766 break;
1767 case XGMAC_INT_DMA_CH_SR_RI:
1768 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1769 break;
1770 case XGMAC_INT_DMA_CH_SR_RBU:
1771 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1772 break;
1773 case XGMAC_INT_DMA_CH_SR_RPS:
1774 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1775 break;
1776 case XGMAC_INT_DMA_CH_SR_TI_RI:
1777 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1778 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1779 break;
1780 case XGMAC_INT_DMA_CH_SR_FBE:
1781 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1782 break;
1783 case XGMAC_INT_DMA_ALL:
1784 dma_ch_ier |= channel->saved_ier;
1785 break;
1786 default:
1787 return -1;
1788 }
1789
1790 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1791
1792 return 0;
1793 }
1794
xgbe_disable_int(struct xgbe_channel * channel,enum xgbe_int int_id)1795 static int xgbe_disable_int(struct xgbe_channel *channel,
1796 enum xgbe_int int_id)
1797 {
1798 unsigned int dma_ch_ier;
1799
1800 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1801
1802 switch (int_id) {
1803 case XGMAC_INT_DMA_CH_SR_TI:
1804 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1805 break;
1806 case XGMAC_INT_DMA_CH_SR_TPS:
1807 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1808 break;
1809 case XGMAC_INT_DMA_CH_SR_TBU:
1810 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1811 break;
1812 case XGMAC_INT_DMA_CH_SR_RI:
1813 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1814 break;
1815 case XGMAC_INT_DMA_CH_SR_RBU:
1816 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1817 break;
1818 case XGMAC_INT_DMA_CH_SR_RPS:
1819 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1820 break;
1821 case XGMAC_INT_DMA_CH_SR_TI_RI:
1822 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1823 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1824 break;
1825 case XGMAC_INT_DMA_CH_SR_FBE:
1826 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1827 break;
1828 case XGMAC_INT_DMA_ALL:
1829 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1830 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1831 break;
1832 default:
1833 return -1;
1834 }
1835
1836 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1837
1838 return 0;
1839 }
1840
xgbe_exit(struct xgbe_prv_data * pdata)1841 static int xgbe_exit(struct xgbe_prv_data *pdata)
1842 {
1843 unsigned int count = 2000;
1844
1845 DBGPR("-->xgbe_exit\n");
1846
1847 /* Issue a software reset */
1848 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1849 usleep_range(10, 15);
1850
1851 /* Poll Until Poll Condition */
1852 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1853 usleep_range(500, 600);
1854
1855 if (!count)
1856 return -EBUSY;
1857
1858 DBGPR("<--xgbe_exit\n");
1859
1860 return 0;
1861 }
1862
xgbe_flush_tx_queues(struct xgbe_prv_data * pdata)1863 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1864 {
1865 unsigned int i, count;
1866
1867 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1868 return 0;
1869
1870 for (i = 0; i < pdata->tx_q_count; i++)
1871 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1872
1873 /* Poll Until Poll Condition */
1874 for (i = 0; i < pdata->tx_q_count; i++) {
1875 count = 2000;
1876 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1877 MTL_Q_TQOMR, FTQ))
1878 usleep_range(500, 600);
1879
1880 if (!count)
1881 return -EBUSY;
1882 }
1883
1884 return 0;
1885 }
1886
xgbe_config_dma_bus(struct xgbe_prv_data * pdata)1887 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1888 {
1889 /* Set enhanced addressing mode */
1890 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1891
1892 /* Set the System Bus mode */
1893 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1894 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1895 }
1896
xgbe_config_dma_cache(struct xgbe_prv_data * pdata)1897 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1898 {
1899 unsigned int arcache, awcache;
1900
1901 arcache = 0;
1902 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1903 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1904 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1905 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1906 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1907 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1908 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1909
1910 awcache = 0;
1911 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1912 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1913 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1914 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1915 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1916 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1917 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1918 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1919 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1920 }
1921
xgbe_config_mtl_mode(struct xgbe_prv_data * pdata)1922 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1923 {
1924 unsigned int i;
1925
1926 /* Set Tx to weighted round robin scheduling algorithm */
1927 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1928
1929 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1930 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1931 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1932 MTL_TSA_ETS);
1933 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1934 }
1935
1936 /* Set Rx to strict priority algorithm */
1937 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1938 }
1939
xgbe_calculate_per_queue_fifo(unsigned int fifo_size,unsigned int queue_count)1940 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1941 unsigned int queue_count)
1942 {
1943 unsigned int q_fifo_size = 0;
1944 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1945
1946 /* Calculate Tx/Rx fifo share per queue */
1947 switch (fifo_size) {
1948 case 0:
1949 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1950 break;
1951 case 1:
1952 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1953 break;
1954 case 2:
1955 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1956 break;
1957 case 3:
1958 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1959 break;
1960 case 4:
1961 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1962 break;
1963 case 5:
1964 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1965 break;
1966 case 6:
1967 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1968 break;
1969 case 7:
1970 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1971 break;
1972 case 8:
1973 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1974 break;
1975 case 9:
1976 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1977 break;
1978 case 10:
1979 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1980 break;
1981 case 11:
1982 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1983 break;
1984 }
1985
1986 /* The configured value is not the actual amount of fifo RAM */
1987 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1988
1989 q_fifo_size = q_fifo_size / queue_count;
1990
1991 /* Set the queue fifo size programmable value */
1992 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1993 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1994 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1995 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1996 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1997 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1998 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1999 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
2000 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
2001 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
2002 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
2003 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
2004 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
2005 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
2006 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
2007 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
2008 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
2009 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
2010 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
2011 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
2012 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
2013 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
2014
2015 return p_fifo;
2016 }
2017
xgbe_config_tx_fifo_size(struct xgbe_prv_data * pdata)2018 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2019 {
2020 enum xgbe_mtl_fifo_size fifo_size;
2021 unsigned int i;
2022
2023 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
2024 pdata->tx_q_count);
2025
2026 for (i = 0; i < pdata->tx_q_count; i++)
2027 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
2028
2029 netdev_notice(pdata->netdev,
2030 "%d Tx hardware queues, %d byte fifo per queue\n",
2031 pdata->tx_q_count, ((fifo_size + 1) * 256));
2032 }
2033
xgbe_config_rx_fifo_size(struct xgbe_prv_data * pdata)2034 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2035 {
2036 enum xgbe_mtl_fifo_size fifo_size;
2037 unsigned int i;
2038
2039 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
2040 pdata->rx_q_count);
2041
2042 for (i = 0; i < pdata->rx_q_count; i++)
2043 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
2044
2045 netdev_notice(pdata->netdev,
2046 "%d Rx hardware queues, %d byte fifo per queue\n",
2047 pdata->rx_q_count, ((fifo_size + 1) * 256));
2048 }
2049
xgbe_config_queue_mapping(struct xgbe_prv_data * pdata)2050 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2051 {
2052 unsigned int qptc, qptc_extra, queue;
2053 unsigned int prio_queues;
2054 unsigned int ppq, ppq_extra, prio;
2055 unsigned int mask;
2056 unsigned int i, j, reg, reg_val;
2057
2058 /* Map the MTL Tx Queues to Traffic Classes
2059 * Note: Tx Queues >= Traffic Classes
2060 */
2061 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2062 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2063
2064 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2065 for (j = 0; j < qptc; j++) {
2066 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2067 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2068 Q2TCMAP, i);
2069 pdata->q2tc_map[queue++] = i;
2070 }
2071
2072 if (i < qptc_extra) {
2073 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2074 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2075 Q2TCMAP, i);
2076 pdata->q2tc_map[queue++] = i;
2077 }
2078 }
2079
2080 /* Map the 8 VLAN priority values to available MTL Rx queues */
2081 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2082 pdata->rx_q_count);
2083 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2084 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2085
2086 reg = MAC_RQC2R;
2087 reg_val = 0;
2088 for (i = 0, prio = 0; i < prio_queues;) {
2089 mask = 0;
2090 for (j = 0; j < ppq; j++) {
2091 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2092 mask |= (1 << prio);
2093 pdata->prio2q_map[prio++] = i;
2094 }
2095
2096 if (i < ppq_extra) {
2097 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2098 mask |= (1 << prio);
2099 pdata->prio2q_map[prio++] = i;
2100 }
2101
2102 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2103
2104 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2105 continue;
2106
2107 XGMAC_IOWRITE(pdata, reg, reg_val);
2108 reg += MAC_RQC2_INC;
2109 reg_val = 0;
2110 }
2111
2112 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2113 reg = MTL_RQDCM0R;
2114 reg_val = 0;
2115 for (i = 0; i < pdata->rx_q_count;) {
2116 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2117
2118 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2119 continue;
2120
2121 XGMAC_IOWRITE(pdata, reg, reg_val);
2122
2123 reg += MTL_RQDCM_INC;
2124 reg_val = 0;
2125 }
2126 }
2127
xgbe_config_flow_control_threshold(struct xgbe_prv_data * pdata)2128 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2129 {
2130 unsigned int i;
2131
2132 for (i = 0; i < pdata->rx_q_count; i++) {
2133 /* Activate flow control when less than 4k left in fifo */
2134 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
2135
2136 /* De-activate flow control when more than 6k left in fifo */
2137 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
2138 }
2139 }
2140
xgbe_config_mac_address(struct xgbe_prv_data * pdata)2141 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2142 {
2143 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2144
2145 /* Filtering is done using perfect filtering and hash filtering */
2146 if (pdata->hw_feat.hash_table_size) {
2147 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2148 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2149 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2150 }
2151 }
2152
xgbe_config_jumbo_enable(struct xgbe_prv_data * pdata)2153 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2154 {
2155 unsigned int val;
2156
2157 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2158
2159 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2160 }
2161
xgbe_config_mac_speed(struct xgbe_prv_data * pdata)2162 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2163 {
2164 switch (pdata->phy_speed) {
2165 case SPEED_10000:
2166 xgbe_set_xgmii_speed(pdata);
2167 break;
2168
2169 case SPEED_2500:
2170 xgbe_set_gmii_2500_speed(pdata);
2171 break;
2172
2173 case SPEED_1000:
2174 xgbe_set_gmii_speed(pdata);
2175 break;
2176 }
2177 }
2178
xgbe_config_checksum_offload(struct xgbe_prv_data * pdata)2179 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2180 {
2181 if (pdata->netdev->features & NETIF_F_RXCSUM)
2182 xgbe_enable_rx_csum(pdata);
2183 else
2184 xgbe_disable_rx_csum(pdata);
2185 }
2186
xgbe_config_vlan_support(struct xgbe_prv_data * pdata)2187 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2188 {
2189 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2190 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2191 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2192
2193 /* Set the current VLAN Hash Table register value */
2194 xgbe_update_vlan_hash_table(pdata);
2195
2196 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2197 xgbe_enable_rx_vlan_filtering(pdata);
2198 else
2199 xgbe_disable_rx_vlan_filtering(pdata);
2200
2201 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2202 xgbe_enable_rx_vlan_stripping(pdata);
2203 else
2204 xgbe_disable_rx_vlan_stripping(pdata);
2205 }
2206
xgbe_mmc_read(struct xgbe_prv_data * pdata,unsigned int reg_lo)2207 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2208 {
2209 bool read_hi;
2210 u64 val;
2211
2212 switch (reg_lo) {
2213 /* These registers are always 64 bit */
2214 case MMC_TXOCTETCOUNT_GB_LO:
2215 case MMC_TXOCTETCOUNT_G_LO:
2216 case MMC_RXOCTETCOUNT_GB_LO:
2217 case MMC_RXOCTETCOUNT_G_LO:
2218 read_hi = true;
2219 break;
2220
2221 default:
2222 read_hi = false;
2223 };
2224
2225 val = XGMAC_IOREAD(pdata, reg_lo);
2226
2227 if (read_hi)
2228 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2229
2230 return val;
2231 }
2232
xgbe_tx_mmc_int(struct xgbe_prv_data * pdata)2233 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2234 {
2235 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2236 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2237
2238 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2239 stats->txoctetcount_gb +=
2240 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2241
2242 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2243 stats->txframecount_gb +=
2244 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2245
2246 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2247 stats->txbroadcastframes_g +=
2248 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2249
2250 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2251 stats->txmulticastframes_g +=
2252 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2253
2254 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2255 stats->tx64octets_gb +=
2256 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2257
2258 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2259 stats->tx65to127octets_gb +=
2260 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2261
2262 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2263 stats->tx128to255octets_gb +=
2264 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2265
2266 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2267 stats->tx256to511octets_gb +=
2268 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2269
2270 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2271 stats->tx512to1023octets_gb +=
2272 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2273
2274 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2275 stats->tx1024tomaxoctets_gb +=
2276 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2277
2278 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2279 stats->txunicastframes_gb +=
2280 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2281
2282 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2283 stats->txmulticastframes_gb +=
2284 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2285
2286 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2287 stats->txbroadcastframes_g +=
2288 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2289
2290 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2291 stats->txunderflowerror +=
2292 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2293
2294 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2295 stats->txoctetcount_g +=
2296 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2297
2298 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2299 stats->txframecount_g +=
2300 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2301
2302 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2303 stats->txpauseframes +=
2304 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2305
2306 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2307 stats->txvlanframes_g +=
2308 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2309 }
2310
xgbe_rx_mmc_int(struct xgbe_prv_data * pdata)2311 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2312 {
2313 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2314 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2315
2316 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2317 stats->rxframecount_gb +=
2318 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2319
2320 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2321 stats->rxoctetcount_gb +=
2322 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2323
2324 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2325 stats->rxoctetcount_g +=
2326 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2327
2328 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2329 stats->rxbroadcastframes_g +=
2330 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2331
2332 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2333 stats->rxmulticastframes_g +=
2334 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2335
2336 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2337 stats->rxcrcerror +=
2338 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2339
2340 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2341 stats->rxrunterror +=
2342 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2343
2344 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2345 stats->rxjabbererror +=
2346 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2347
2348 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2349 stats->rxundersize_g +=
2350 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2351
2352 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2353 stats->rxoversize_g +=
2354 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2355
2356 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2357 stats->rx64octets_gb +=
2358 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2359
2360 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2361 stats->rx65to127octets_gb +=
2362 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2363
2364 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2365 stats->rx128to255octets_gb +=
2366 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2367
2368 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2369 stats->rx256to511octets_gb +=
2370 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2371
2372 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2373 stats->rx512to1023octets_gb +=
2374 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2375
2376 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2377 stats->rx1024tomaxoctets_gb +=
2378 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2379
2380 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2381 stats->rxunicastframes_g +=
2382 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2383
2384 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2385 stats->rxlengtherror +=
2386 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2387
2388 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2389 stats->rxoutofrangetype +=
2390 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2391
2392 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2393 stats->rxpauseframes +=
2394 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2395
2396 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2397 stats->rxfifooverflow +=
2398 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2399
2400 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2401 stats->rxvlanframes_gb +=
2402 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2403
2404 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2405 stats->rxwatchdogerror +=
2406 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2407 }
2408
xgbe_read_mmc_stats(struct xgbe_prv_data * pdata)2409 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2410 {
2411 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2412
2413 /* Freeze counters */
2414 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2415
2416 stats->txoctetcount_gb +=
2417 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2418
2419 stats->txframecount_gb +=
2420 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2421
2422 stats->txbroadcastframes_g +=
2423 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2424
2425 stats->txmulticastframes_g +=
2426 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2427
2428 stats->tx64octets_gb +=
2429 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2430
2431 stats->tx65to127octets_gb +=
2432 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2433
2434 stats->tx128to255octets_gb +=
2435 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2436
2437 stats->tx256to511octets_gb +=
2438 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2439
2440 stats->tx512to1023octets_gb +=
2441 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2442
2443 stats->tx1024tomaxoctets_gb +=
2444 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2445
2446 stats->txunicastframes_gb +=
2447 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2448
2449 stats->txmulticastframes_gb +=
2450 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2451
2452 stats->txbroadcastframes_g +=
2453 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2454
2455 stats->txunderflowerror +=
2456 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2457
2458 stats->txoctetcount_g +=
2459 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2460
2461 stats->txframecount_g +=
2462 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2463
2464 stats->txpauseframes +=
2465 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2466
2467 stats->txvlanframes_g +=
2468 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2469
2470 stats->rxframecount_gb +=
2471 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2472
2473 stats->rxoctetcount_gb +=
2474 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2475
2476 stats->rxoctetcount_g +=
2477 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2478
2479 stats->rxbroadcastframes_g +=
2480 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2481
2482 stats->rxmulticastframes_g +=
2483 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2484
2485 stats->rxcrcerror +=
2486 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2487
2488 stats->rxrunterror +=
2489 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2490
2491 stats->rxjabbererror +=
2492 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2493
2494 stats->rxundersize_g +=
2495 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2496
2497 stats->rxoversize_g +=
2498 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2499
2500 stats->rx64octets_gb +=
2501 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2502
2503 stats->rx65to127octets_gb +=
2504 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2505
2506 stats->rx128to255octets_gb +=
2507 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2508
2509 stats->rx256to511octets_gb +=
2510 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2511
2512 stats->rx512to1023octets_gb +=
2513 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2514
2515 stats->rx1024tomaxoctets_gb +=
2516 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2517
2518 stats->rxunicastframes_g +=
2519 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2520
2521 stats->rxlengtherror +=
2522 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2523
2524 stats->rxoutofrangetype +=
2525 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2526
2527 stats->rxpauseframes +=
2528 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2529
2530 stats->rxfifooverflow +=
2531 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2532
2533 stats->rxvlanframes_gb +=
2534 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2535
2536 stats->rxwatchdogerror +=
2537 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2538
2539 /* Un-freeze counters */
2540 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2541 }
2542
xgbe_config_mmc(struct xgbe_prv_data * pdata)2543 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2544 {
2545 /* Set counters to reset on read */
2546 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2547
2548 /* Reset the counters */
2549 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2550 }
2551
xgbe_prepare_tx_stop(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2552 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2553 struct xgbe_channel *channel)
2554 {
2555 unsigned int tx_dsr, tx_pos, tx_qidx;
2556 unsigned int tx_status;
2557 unsigned long tx_timeout;
2558
2559 /* Calculate the status register to read and the position within */
2560 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2561 tx_dsr = DMA_DSR0;
2562 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2563 DMA_DSR0_TPS_START;
2564 } else {
2565 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2566
2567 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2568 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2569 DMA_DSRX_TPS_START;
2570 }
2571
2572 /* The Tx engine cannot be stopped if it is actively processing
2573 * descriptors. Wait for the Tx engine to enter the stopped or
2574 * suspended state. Don't wait forever though...
2575 */
2576 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2577 while (time_before(jiffies, tx_timeout)) {
2578 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2579 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2580 if ((tx_status == DMA_TPS_STOPPED) ||
2581 (tx_status == DMA_TPS_SUSPENDED))
2582 break;
2583
2584 usleep_range(500, 1000);
2585 }
2586
2587 if (!time_before(jiffies, tx_timeout))
2588 netdev_info(pdata->netdev,
2589 "timed out waiting for Tx DMA channel %u to stop\n",
2590 channel->queue_index);
2591 }
2592
xgbe_enable_tx(struct xgbe_prv_data * pdata)2593 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2594 {
2595 struct xgbe_channel *channel;
2596 unsigned int i;
2597
2598 /* Enable each Tx DMA channel */
2599 channel = pdata->channel;
2600 for (i = 0; i < pdata->channel_count; i++, channel++) {
2601 if (!channel->tx_ring)
2602 break;
2603
2604 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2605 }
2606
2607 /* Enable each Tx queue */
2608 for (i = 0; i < pdata->tx_q_count; i++)
2609 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2610 MTL_Q_ENABLED);
2611
2612 /* Enable MAC Tx */
2613 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2614 }
2615
xgbe_disable_tx(struct xgbe_prv_data * pdata)2616 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2617 {
2618 struct xgbe_channel *channel;
2619 unsigned int i;
2620
2621 /* Prepare for Tx DMA channel stop */
2622 channel = pdata->channel;
2623 for (i = 0; i < pdata->channel_count; i++, channel++) {
2624 if (!channel->tx_ring)
2625 break;
2626
2627 xgbe_prepare_tx_stop(pdata, channel);
2628 }
2629
2630 /* Disable MAC Tx */
2631 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2632
2633 /* Disable each Tx queue */
2634 for (i = 0; i < pdata->tx_q_count; i++)
2635 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2636
2637 /* Disable each Tx DMA channel */
2638 channel = pdata->channel;
2639 for (i = 0; i < pdata->channel_count; i++, channel++) {
2640 if (!channel->tx_ring)
2641 break;
2642
2643 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2644 }
2645 }
2646
xgbe_enable_rx(struct xgbe_prv_data * pdata)2647 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2648 {
2649 struct xgbe_channel *channel;
2650 unsigned int reg_val, i;
2651
2652 /* Enable each Rx DMA channel */
2653 channel = pdata->channel;
2654 for (i = 0; i < pdata->channel_count; i++, channel++) {
2655 if (!channel->rx_ring)
2656 break;
2657
2658 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2659 }
2660
2661 /* Enable each Rx queue */
2662 reg_val = 0;
2663 for (i = 0; i < pdata->rx_q_count; i++)
2664 reg_val |= (0x02 << (i << 1));
2665 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2666
2667 /* Enable MAC Rx */
2668 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2669 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2670 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2671 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2672 }
2673
xgbe_disable_rx(struct xgbe_prv_data * pdata)2674 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2675 {
2676 struct xgbe_channel *channel;
2677 unsigned int i;
2678
2679 /* Disable MAC Rx */
2680 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2681 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2682 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2683 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2684
2685 /* Disable each Rx queue */
2686 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2687
2688 /* Disable each Rx DMA channel */
2689 channel = pdata->channel;
2690 for (i = 0; i < pdata->channel_count; i++, channel++) {
2691 if (!channel->rx_ring)
2692 break;
2693
2694 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2695 }
2696 }
2697
xgbe_powerup_tx(struct xgbe_prv_data * pdata)2698 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2699 {
2700 struct xgbe_channel *channel;
2701 unsigned int i;
2702
2703 /* Enable each Tx DMA channel */
2704 channel = pdata->channel;
2705 for (i = 0; i < pdata->channel_count; i++, channel++) {
2706 if (!channel->tx_ring)
2707 break;
2708
2709 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2710 }
2711
2712 /* Enable MAC Tx */
2713 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2714 }
2715
xgbe_powerdown_tx(struct xgbe_prv_data * pdata)2716 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2717 {
2718 struct xgbe_channel *channel;
2719 unsigned int i;
2720
2721 /* Prepare for Tx DMA channel stop */
2722 channel = pdata->channel;
2723 for (i = 0; i < pdata->channel_count; i++, channel++) {
2724 if (!channel->tx_ring)
2725 break;
2726
2727 xgbe_prepare_tx_stop(pdata, channel);
2728 }
2729
2730 /* Disable MAC Tx */
2731 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2732
2733 /* Disable each Tx DMA channel */
2734 channel = pdata->channel;
2735 for (i = 0; i < pdata->channel_count; i++, channel++) {
2736 if (!channel->tx_ring)
2737 break;
2738
2739 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2740 }
2741 }
2742
xgbe_powerup_rx(struct xgbe_prv_data * pdata)2743 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2744 {
2745 struct xgbe_channel *channel;
2746 unsigned int i;
2747
2748 /* Enable each Rx DMA channel */
2749 channel = pdata->channel;
2750 for (i = 0; i < pdata->channel_count; i++, channel++) {
2751 if (!channel->rx_ring)
2752 break;
2753
2754 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2755 }
2756 }
2757
xgbe_powerdown_rx(struct xgbe_prv_data * pdata)2758 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2759 {
2760 struct xgbe_channel *channel;
2761 unsigned int i;
2762
2763 /* Disable each Rx DMA channel */
2764 channel = pdata->channel;
2765 for (i = 0; i < pdata->channel_count; i++, channel++) {
2766 if (!channel->rx_ring)
2767 break;
2768
2769 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2770 }
2771 }
2772
xgbe_init(struct xgbe_prv_data * pdata)2773 static int xgbe_init(struct xgbe_prv_data *pdata)
2774 {
2775 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2776 int ret;
2777
2778 DBGPR("-->xgbe_init\n");
2779
2780 /* Flush Tx queues */
2781 ret = xgbe_flush_tx_queues(pdata);
2782 if (ret)
2783 return ret;
2784
2785 /*
2786 * Initialize DMA related features
2787 */
2788 xgbe_config_dma_bus(pdata);
2789 xgbe_config_dma_cache(pdata);
2790 xgbe_config_osp_mode(pdata);
2791 xgbe_config_pblx8(pdata);
2792 xgbe_config_tx_pbl_val(pdata);
2793 xgbe_config_rx_pbl_val(pdata);
2794 xgbe_config_rx_coalesce(pdata);
2795 xgbe_config_tx_coalesce(pdata);
2796 xgbe_config_rx_buffer_size(pdata);
2797 xgbe_config_tso_mode(pdata);
2798 xgbe_config_sph_mode(pdata);
2799 xgbe_config_rss(pdata);
2800 desc_if->wrapper_tx_desc_init(pdata);
2801 desc_if->wrapper_rx_desc_init(pdata);
2802 xgbe_enable_dma_interrupts(pdata);
2803
2804 /*
2805 * Initialize MTL related features
2806 */
2807 xgbe_config_mtl_mode(pdata);
2808 xgbe_config_queue_mapping(pdata);
2809 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2810 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2811 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2812 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2813 xgbe_config_tx_fifo_size(pdata);
2814 xgbe_config_rx_fifo_size(pdata);
2815 xgbe_config_flow_control_threshold(pdata);
2816 /*TODO: Error Packet and undersized good Packet forwarding enable
2817 (FEP and FUP)
2818 */
2819 xgbe_config_dcb_tc(pdata);
2820 xgbe_config_dcb_pfc(pdata);
2821 xgbe_enable_mtl_interrupts(pdata);
2822
2823 /*
2824 * Initialize MAC related features
2825 */
2826 xgbe_config_mac_address(pdata);
2827 xgbe_config_rx_mode(pdata);
2828 xgbe_config_jumbo_enable(pdata);
2829 xgbe_config_flow_control(pdata);
2830 xgbe_config_mac_speed(pdata);
2831 xgbe_config_checksum_offload(pdata);
2832 xgbe_config_vlan_support(pdata);
2833 xgbe_config_mmc(pdata);
2834 xgbe_enable_mac_interrupts(pdata);
2835
2836 DBGPR("<--xgbe_init\n");
2837
2838 return 0;
2839 }
2840
xgbe_init_function_ptrs_dev(struct xgbe_hw_if * hw_if)2841 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2842 {
2843 DBGPR("-->xgbe_init_function_ptrs\n");
2844
2845 hw_if->tx_complete = xgbe_tx_complete;
2846
2847 hw_if->set_mac_address = xgbe_set_mac_address;
2848 hw_if->config_rx_mode = xgbe_config_rx_mode;
2849
2850 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2851 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2852
2853 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2854 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2855 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2856 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2857 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2858
2859 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2860 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2861
2862 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2863 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2864 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2865
2866 hw_if->enable_tx = xgbe_enable_tx;
2867 hw_if->disable_tx = xgbe_disable_tx;
2868 hw_if->enable_rx = xgbe_enable_rx;
2869 hw_if->disable_rx = xgbe_disable_rx;
2870
2871 hw_if->powerup_tx = xgbe_powerup_tx;
2872 hw_if->powerdown_tx = xgbe_powerdown_tx;
2873 hw_if->powerup_rx = xgbe_powerup_rx;
2874 hw_if->powerdown_rx = xgbe_powerdown_rx;
2875
2876 hw_if->dev_xmit = xgbe_dev_xmit;
2877 hw_if->dev_read = xgbe_dev_read;
2878 hw_if->enable_int = xgbe_enable_int;
2879 hw_if->disable_int = xgbe_disable_int;
2880 hw_if->init = xgbe_init;
2881 hw_if->exit = xgbe_exit;
2882
2883 /* Descriptor related Sequences have to be initialized here */
2884 hw_if->tx_desc_init = xgbe_tx_desc_init;
2885 hw_if->rx_desc_init = xgbe_rx_desc_init;
2886 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2887 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2888 hw_if->is_last_desc = xgbe_is_last_desc;
2889 hw_if->is_context_desc = xgbe_is_context_desc;
2890 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
2891
2892 /* For FLOW ctrl */
2893 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2894 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2895
2896 /* For RX coalescing */
2897 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2898 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2899 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2900 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2901
2902 /* For RX and TX threshold config */
2903 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2904 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2905
2906 /* For RX and TX Store and Forward Mode config */
2907 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2908 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2909
2910 /* For TX DMA Operating on Second Frame config */
2911 hw_if->config_osp_mode = xgbe_config_osp_mode;
2912
2913 /* For RX and TX PBL config */
2914 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2915 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2916 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2917 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2918 hw_if->config_pblx8 = xgbe_config_pblx8;
2919
2920 /* For MMC statistics support */
2921 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2922 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2923 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2924
2925 /* For PTP config */
2926 hw_if->config_tstamp = xgbe_config_tstamp;
2927 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2928 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2929 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2930 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2931
2932 /* For Data Center Bridging config */
2933 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2934 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2935
2936 /* For Receive Side Scaling */
2937 hw_if->enable_rss = xgbe_enable_rss;
2938 hw_if->disable_rss = xgbe_disable_rss;
2939 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2940 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
2941
2942 DBGPR("<--xgbe_init_function_ptrs\n");
2943 }
2944