1 /* 2 * bfin_sport - Analog Devices BF6XX SPORT registers 3 * 4 * Copyright (c) 2012 Analog Devices Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #ifndef _BFIN_SPORT3_H_ 21 #define _BFIN_SPORT3_H_ 22 23 #include <linux/types.h> 24 25 #define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */ 26 #define SPORT_CTL_DTYPE 0x00000006 /* Data type select */ 27 #define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */ 28 #define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */ 29 #define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */ 30 #define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */ 31 #define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */ 32 #define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */ 33 #define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */ 34 #define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */ 35 #define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */ 36 #define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */ 37 #define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */ 38 #define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */ 39 #define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */ 40 #define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */ 41 #define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */ 42 #define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */ 43 #define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */ 44 #define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */ 45 #define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */ 46 #define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */ 47 #define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */ 48 #define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */ 49 #define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */ 50 #define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */ 51 #define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */ 52 #define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */ 53 #define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */ 54 #define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */ 55 #define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */ 56 #define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */ 57 #define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */ 58 59 #define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */ 60 #define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */ 61 62 #define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */ 63 #define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */ 64 #define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */ 65 #define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */ 66 #define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */ 67 68 #define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ 69 #define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */ 70 71 #define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */ 72 #define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */ 73 #define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */ 74 #define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */ 75 #define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */ 76 #define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */ 77 78 #define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */ 79 80 #define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */ 81 #define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */ 82 #define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */ 83 84 struct sport_register { 85 u32 spctl; 86 u32 div; 87 u32 spmctl; 88 u32 spcs0; 89 u32 spcs1; 90 u32 spcs2; 91 u32 spcs3; 92 u32 spcnt; 93 u32 sperrctl; 94 u32 spmstat; 95 u32 spctl2; 96 u32 txa; 97 u32 rxa; 98 u32 txb; 99 u32 rxb; 100 u32 revid; 101 }; 102 103 struct bfin_snd_platform_data { 104 const unsigned short *pin_req; 105 }; 106 107 #endif 108