1 /*
2 * TI Palmas
3 *
4 * Copyright 2011-2013 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
18
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/extcon.h>
24 #include <linux/usb/phy_companion.h>
25
26 #define PALMAS_NUM_CLIENTS 3
27
28 /* The ID_REVISION NUMBERS */
29 #define PALMAS_CHIP_OLD_ID 0x0000
30 #define PALMAS_CHIP_ID 0xC035
31 #define PALMAS_CHIP_CHARGER_ID 0xC036
32
33 #define TPS65917_RESERVED -1
34
35 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
36 ((a) == PALMAS_CHIP_ID))
37 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
38
39 /**
40 * Palmas PMIC feature types
41 *
42 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
43 * regulator.
44 *
45 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
46 * specific feature (above) or not. Return non-zero, if yes.
47 */
48 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
49 #define PALMAS_PMIC_HAS(b, f) \
50 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
51
52 struct palmas_pmic;
53 struct palmas_gpadc;
54 struct palmas_resource;
55 struct palmas_usb;
56 struct palmas_pmic_driver_data;
57 struct palmas_pmic_platform_data;
58
59 enum palmas_usb_state {
60 PALMAS_USB_STATE_DISCONNECT,
61 PALMAS_USB_STATE_VBUS,
62 PALMAS_USB_STATE_ID,
63 };
64
65 struct palmas {
66 struct device *dev;
67
68 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
69 struct regmap *regmap[PALMAS_NUM_CLIENTS];
70
71 /* Stored chip id */
72 int id;
73
74 unsigned int features;
75 /* IRQ Data */
76 int irq;
77 u32 irq_mask;
78 struct mutex irq_lock;
79 struct regmap_irq_chip_data *irq_data;
80
81 struct palmas_pmic_driver_data *pmic_ddata;
82
83 /* Child Devices */
84 struct palmas_pmic *pmic;
85 struct palmas_gpadc *gpadc;
86 struct palmas_resource *resource;
87 struct palmas_usb *usb;
88
89 /* GPIO MUXing */
90 u8 gpio_muxed;
91 u8 led_muxed;
92 u8 pwm_muxed;
93 };
94
95 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
96 PALMAS_EXT_CONTROL_ENABLE2 | \
97 PALMAS_EXT_CONTROL_NSLEEP)
98
99 struct palmas_sleep_requestor_info {
100 int id;
101 int reg_offset;
102 int bit_pos;
103 };
104
105 struct palmas_regs_info {
106 char *name;
107 char *sname;
108 u8 vsel_addr;
109 u8 ctrl_addr;
110 u8 tstep_addr;
111 int sleep_id;
112 };
113
114 struct palmas_pmic_driver_data {
115 int smps_start;
116 int smps_end;
117 int ldo_begin;
118 int ldo_end;
119 int max_reg;
120 bool has_regen3;
121 struct palmas_regs_info *palmas_regs_info;
122 struct of_regulator_match *palmas_matches;
123 struct palmas_sleep_requestor_info *sleep_req_info;
124 int (*smps_register)(struct palmas_pmic *pmic,
125 struct palmas_pmic_driver_data *ddata,
126 struct palmas_pmic_platform_data *pdata,
127 const char *pdev_name,
128 struct regulator_config config);
129 int (*ldo_register)(struct palmas_pmic *pmic,
130 struct palmas_pmic_driver_data *ddata,
131 struct palmas_pmic_platform_data *pdata,
132 const char *pdev_name,
133 struct regulator_config config);
134 };
135
136 struct palmas_gpadc_platform_data {
137 /* Channel 3 current source is only enabled during conversion */
138 int ch3_current;
139
140 /* Channel 0 current source can be used for battery detection.
141 * If used for battery detection this will cause a permanent current
142 * consumption depending on current level set here.
143 */
144 int ch0_current;
145
146 /* default BAT_REMOVAL_DAT setting on device probe */
147 int bat_removal;
148
149 /* Sets the START_POLARITY bit in the RT_CTRL register */
150 int start_polarity;
151 };
152
153 struct palmas_reg_init {
154 /* warm_rest controls the voltage levels after a warm reset
155 *
156 * 0: reload default values from OTP on warm reset
157 * 1: maintain voltage from VSEL on warm reset
158 */
159 int warm_reset;
160
161 /* roof_floor controls whether the regulator uses the i2c style
162 * of DVS or uses the method where a GPIO or other control method is
163 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
164 *
165 * For SMPS
166 *
167 * 0: i2c selection of voltage
168 * 1: pin selection of voltage.
169 *
170 * For LDO unused
171 */
172 int roof_floor;
173
174 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
175 * the data sheet.
176 *
177 * For SMPS
178 *
179 * 0: Off
180 * 1: AUTO
181 * 2: ECO
182 * 3: Forced PWM
183 *
184 * For LDO
185 *
186 * 0: Off
187 * 1: On
188 */
189 int mode_sleep;
190
191 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
192 * register. Set this is the default voltage set in OTP needs
193 * to be overridden.
194 */
195 u8 vsel;
196
197 };
198
199 enum palmas_regulators {
200 /* SMPS regulators */
201 PALMAS_REG_SMPS12,
202 PALMAS_REG_SMPS123,
203 PALMAS_REG_SMPS3,
204 PALMAS_REG_SMPS45,
205 PALMAS_REG_SMPS457,
206 PALMAS_REG_SMPS6,
207 PALMAS_REG_SMPS7,
208 PALMAS_REG_SMPS8,
209 PALMAS_REG_SMPS9,
210 PALMAS_REG_SMPS10_OUT2,
211 PALMAS_REG_SMPS10_OUT1,
212 /* LDO regulators */
213 PALMAS_REG_LDO1,
214 PALMAS_REG_LDO2,
215 PALMAS_REG_LDO3,
216 PALMAS_REG_LDO4,
217 PALMAS_REG_LDO5,
218 PALMAS_REG_LDO6,
219 PALMAS_REG_LDO7,
220 PALMAS_REG_LDO8,
221 PALMAS_REG_LDO9,
222 PALMAS_REG_LDOLN,
223 PALMAS_REG_LDOUSB,
224 /* External regulators */
225 PALMAS_REG_REGEN1,
226 PALMAS_REG_REGEN2,
227 PALMAS_REG_REGEN3,
228 PALMAS_REG_SYSEN1,
229 PALMAS_REG_SYSEN2,
230 /* Total number of regulators */
231 PALMAS_NUM_REGS,
232 };
233
234 enum tps65917_regulators {
235 /* SMPS regulators */
236 TPS65917_REG_SMPS1,
237 TPS65917_REG_SMPS2,
238 TPS65917_REG_SMPS3,
239 TPS65917_REG_SMPS4,
240 TPS65917_REG_SMPS5,
241 /* LDO regulators */
242 TPS65917_REG_LDO1,
243 TPS65917_REG_LDO2,
244 TPS65917_REG_LDO3,
245 TPS65917_REG_LDO4,
246 TPS65917_REG_LDO5,
247 TPS65917_REG_REGEN1,
248 TPS65917_REG_REGEN2,
249 TPS65917_REG_REGEN3,
250
251 /* Total number of regulators */
252 TPS65917_NUM_REGS,
253 };
254
255 /* External controll signal name */
256 enum {
257 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
258 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
259 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
260 };
261
262 /*
263 * Palmas device resources can be controlled externally for
264 * enabling/disabling it rather than register write through i2c.
265 * Add the external controlled requestor ID for different resources.
266 */
267 enum palmas_external_requestor_id {
268 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
269 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
270 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
271 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
272 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
273 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
274 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
275 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
276 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
277 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
278 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
279 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
280 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
281 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
282 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
283 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
284 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
285 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
286 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
287 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
288 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
289 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
290 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
291 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
292 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
293 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
294
295 /* Last entry */
296 PALMAS_EXTERNAL_REQSTR_ID_MAX,
297 };
298
299 enum tps65917_external_requestor_id {
300 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
301 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
302 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
303 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
304 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
305 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
306 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
307 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
308 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
309 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
310 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
311 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
312 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
313 /* Last entry */
314 TPS65917_EXTERNAL_REQSTR_ID_MAX,
315 };
316
317 struct palmas_pmic_platform_data {
318 /* An array of pointers to regulator init data indexed by regulator
319 * ID
320 */
321 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
322
323 /* An array of pointers to structures containing sleep mode and DVS
324 * configuration for regulators indexed by ID
325 */
326 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
327
328 /* use LDO6 for vibrator control */
329 int ldo6_vibrator;
330
331 /* Enable tracking mode of LDO8 */
332 bool enable_ldo8_tracking;
333 };
334
335 struct palmas_usb_platform_data {
336 /* Do we enable the wakeup comparator on probe */
337 int wakeup;
338 };
339
340 struct palmas_resource_platform_data {
341 int regen1_mode_sleep;
342 int regen2_mode_sleep;
343 int sysen1_mode_sleep;
344 int sysen2_mode_sleep;
345
346 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
347 u8 nsleep_res;
348 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
349 u8 nsleep_smps;
350 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
351 u8 nsleep_ldo1;
352 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
353 u8 nsleep_ldo2;
354
355 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
356 u8 enable1_res;
357 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
358 u8 enable1_smps;
359 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
360 u8 enable1_ldo1;
361 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
362 u8 enable1_ldo2;
363
364 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
365 u8 enable2_res;
366 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
367 u8 enable2_smps;
368 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
369 u8 enable2_ldo1;
370 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
371 u8 enable2_ldo2;
372 };
373
374 struct palmas_clk_platform_data {
375 int clk32kg_mode_sleep;
376 int clk32kgaudio_mode_sleep;
377 };
378
379 struct palmas_platform_data {
380 int irq_flags;
381 int gpio_base;
382
383 /* bit value to be loaded to the POWER_CTRL register */
384 u8 power_ctrl;
385
386 /*
387 * boolean to select if we want to configure muxing here
388 * then the two value to load into the registers if true
389 */
390 int mux_from_pdata;
391 u8 pad1, pad2;
392 bool pm_off;
393
394 struct palmas_pmic_platform_data *pmic_pdata;
395 struct palmas_gpadc_platform_data *gpadc_pdata;
396 struct palmas_usb_platform_data *usb_pdata;
397 struct palmas_resource_platform_data *resource_pdata;
398 struct palmas_clk_platform_data *clk_pdata;
399 };
400
401 struct palmas_gpadc_calibration {
402 s32 gain;
403 s32 gain_error;
404 s32 offset_error;
405 };
406
407 struct palmas_gpadc {
408 struct device *dev;
409 struct palmas *palmas;
410
411 int ch3_current;
412 int ch0_current;
413
414 int gpadc_force;
415
416 int bat_removal;
417
418 struct mutex reading_lock;
419 struct completion irq_complete;
420
421 int eoc_sw_irq;
422
423 struct palmas_gpadc_calibration *palmas_cal_tbl;
424
425 int conv0_channel;
426 int conv1_channel;
427 int rt_channel;
428 };
429
430 struct palmas_gpadc_result {
431 s32 raw_code;
432 s32 corrected_code;
433 s32 result;
434 };
435
436 #define PALMAS_MAX_CHANNELS 16
437
438 /* Define the tps65917 IRQ numbers */
439 enum tps65917_irqs {
440 /* INT1 registers */
441 TPS65917_RESERVED1,
442 TPS65917_PWRON_IRQ,
443 TPS65917_LONG_PRESS_KEY_IRQ,
444 TPS65917_RESERVED2,
445 TPS65917_PWRDOWN_IRQ,
446 TPS65917_HOTDIE_IRQ,
447 TPS65917_VSYS_MON_IRQ,
448 TPS65917_RESERVED3,
449 /* INT2 registers */
450 TPS65917_RESERVED4,
451 TPS65917_OTP_ERROR_IRQ,
452 TPS65917_WDT_IRQ,
453 TPS65917_RESERVED5,
454 TPS65917_RESET_IN_IRQ,
455 TPS65917_FSD_IRQ,
456 TPS65917_SHORT_IRQ,
457 TPS65917_RESERVED6,
458 /* INT3 registers */
459 TPS65917_GPADC_AUTO_0_IRQ,
460 TPS65917_GPADC_AUTO_1_IRQ,
461 TPS65917_GPADC_EOC_SW_IRQ,
462 TPS65917_RESREVED6,
463 TPS65917_RESERVED7,
464 TPS65917_RESERVED8,
465 TPS65917_RESERVED9,
466 TPS65917_VBUS_IRQ,
467 /* INT4 registers */
468 TPS65917_GPIO_0_IRQ,
469 TPS65917_GPIO_1_IRQ,
470 TPS65917_GPIO_2_IRQ,
471 TPS65917_GPIO_3_IRQ,
472 TPS65917_GPIO_4_IRQ,
473 TPS65917_GPIO_5_IRQ,
474 TPS65917_GPIO_6_IRQ,
475 TPS65917_RESERVED10,
476 /* Total Number IRQs */
477 TPS65917_NUM_IRQ,
478 };
479
480 /* Define the palmas IRQ numbers */
481 enum palmas_irqs {
482 /* INT1 registers */
483 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
484 PALMAS_PWRON_IRQ,
485 PALMAS_LONG_PRESS_KEY_IRQ,
486 PALMAS_RPWRON_IRQ,
487 PALMAS_PWRDOWN_IRQ,
488 PALMAS_HOTDIE_IRQ,
489 PALMAS_VSYS_MON_IRQ,
490 PALMAS_VBAT_MON_IRQ,
491 /* INT2 registers */
492 PALMAS_RTC_ALARM_IRQ,
493 PALMAS_RTC_TIMER_IRQ,
494 PALMAS_WDT_IRQ,
495 PALMAS_BATREMOVAL_IRQ,
496 PALMAS_RESET_IN_IRQ,
497 PALMAS_FBI_BB_IRQ,
498 PALMAS_SHORT_IRQ,
499 PALMAS_VAC_ACOK_IRQ,
500 /* INT3 registers */
501 PALMAS_GPADC_AUTO_0_IRQ,
502 PALMAS_GPADC_AUTO_1_IRQ,
503 PALMAS_GPADC_EOC_SW_IRQ,
504 PALMAS_GPADC_EOC_RT_IRQ,
505 PALMAS_ID_OTG_IRQ,
506 PALMAS_ID_IRQ,
507 PALMAS_VBUS_OTG_IRQ,
508 PALMAS_VBUS_IRQ,
509 /* INT4 registers */
510 PALMAS_GPIO_0_IRQ,
511 PALMAS_GPIO_1_IRQ,
512 PALMAS_GPIO_2_IRQ,
513 PALMAS_GPIO_3_IRQ,
514 PALMAS_GPIO_4_IRQ,
515 PALMAS_GPIO_5_IRQ,
516 PALMAS_GPIO_6_IRQ,
517 PALMAS_GPIO_7_IRQ,
518 /* Total Number IRQs */
519 PALMAS_NUM_IRQ,
520 };
521
522 struct palmas_pmic {
523 struct palmas *palmas;
524 struct device *dev;
525 struct regulator_desc desc[PALMAS_NUM_REGS];
526 struct regulator_dev *rdev[PALMAS_NUM_REGS];
527 struct mutex mutex;
528
529 int smps123;
530 int smps457;
531 int smps12;
532
533 int range[PALMAS_REG_SMPS10_OUT1];
534 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
535 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
536 };
537
538 struct palmas_resource {
539 struct palmas *palmas;
540 struct device *dev;
541 };
542
543 struct palmas_usb {
544 struct palmas *palmas;
545 struct device *dev;
546
547 struct extcon_dev *edev;
548
549 int id_otg_irq;
550 int id_irq;
551 int vbus_otg_irq;
552 int vbus_irq;
553
554 enum palmas_usb_state linkstat;
555 int wakeup;
556 bool enable_vbus_detection;
557 bool enable_id_detection;
558 };
559
560 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
561
562 enum usb_irq_events {
563 /* Wakeup events from INT3 */
564 PALMAS_USB_ID_WAKEPUP,
565 PALMAS_USB_VBUS_WAKEUP,
566
567 /* ID_OTG_EVENTS */
568 PALMAS_USB_ID_GND,
569 N_PALMAS_USB_ID_GND,
570 PALMAS_USB_ID_C,
571 N_PALMAS_USB_ID_C,
572 PALMAS_USB_ID_B,
573 N_PALMAS_USB_ID_B,
574 PALMAS_USB_ID_A,
575 N_PALMAS_USB_ID_A,
576 PALMAS_USB_ID_FLOAT,
577 N_PALMAS_USB_ID_FLOAT,
578
579 /* VBUS_OTG_EVENTS */
580 PALMAS_USB_VB_SESS_END,
581 N_PALMAS_USB_VB_SESS_END,
582 PALMAS_USB_VB_SESS_VLD,
583 N_PALMAS_USB_VB_SESS_VLD,
584 PALMAS_USB_VA_SESS_VLD,
585 N_PALMAS_USB_VA_SESS_VLD,
586 PALMAS_USB_VA_VBUS_VLD,
587 N_PALMAS_USB_VA_VBUS_VLD,
588 PALMAS_USB_VADP_SNS,
589 N_PALMAS_USB_VADP_SNS,
590 PALMAS_USB_VADP_PRB,
591 N_PALMAS_USB_VADP_PRB,
592 PALMAS_USB_VOTG_SESS_VLD,
593 N_PALMAS_USB_VOTG_SESS_VLD,
594 };
595
596 /* defines so we can store the mux settings */
597 #define PALMAS_GPIO_0_MUXED (1 << 0)
598 #define PALMAS_GPIO_1_MUXED (1 << 1)
599 #define PALMAS_GPIO_2_MUXED (1 << 2)
600 #define PALMAS_GPIO_3_MUXED (1 << 3)
601 #define PALMAS_GPIO_4_MUXED (1 << 4)
602 #define PALMAS_GPIO_5_MUXED (1 << 5)
603 #define PALMAS_GPIO_6_MUXED (1 << 6)
604 #define PALMAS_GPIO_7_MUXED (1 << 7)
605
606 #define PALMAS_LED1_MUXED (1 << 0)
607 #define PALMAS_LED2_MUXED (1 << 1)
608
609 #define PALMAS_PWM1_MUXED (1 << 0)
610 #define PALMAS_PWM2_MUXED (1 << 1)
611
612 /* helper macro to get correct slave number */
613 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
614 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
615
616 /* Base addresses of IP blocks in Palmas */
617 #define PALMAS_SMPS_DVS_BASE 0x020
618 #define PALMAS_RTC_BASE 0x100
619 #define PALMAS_VALIDITY_BASE 0x118
620 #define PALMAS_SMPS_BASE 0x120
621 #define PALMAS_LDO_BASE 0x150
622 #define PALMAS_DVFS_BASE 0x180
623 #define PALMAS_PMU_CONTROL_BASE 0x1A0
624 #define PALMAS_RESOURCE_BASE 0x1D4
625 #define PALMAS_PU_PD_OD_BASE 0x1F0
626 #define PALMAS_LED_BASE 0x200
627 #define PALMAS_INTERRUPT_BASE 0x210
628 #define PALMAS_USB_OTG_BASE 0x250
629 #define PALMAS_VIBRATOR_BASE 0x270
630 #define PALMAS_GPIO_BASE 0x280
631 #define PALMAS_USB_BASE 0x290
632 #define PALMAS_GPADC_BASE 0x2C0
633 #define PALMAS_TRIM_GPADC_BASE 0x3CD
634
635 /* Registers for function RTC */
636 #define PALMAS_SECONDS_REG 0x00
637 #define PALMAS_MINUTES_REG 0x01
638 #define PALMAS_HOURS_REG 0x02
639 #define PALMAS_DAYS_REG 0x03
640 #define PALMAS_MONTHS_REG 0x04
641 #define PALMAS_YEARS_REG 0x05
642 #define PALMAS_WEEKS_REG 0x06
643 #define PALMAS_ALARM_SECONDS_REG 0x08
644 #define PALMAS_ALARM_MINUTES_REG 0x09
645 #define PALMAS_ALARM_HOURS_REG 0x0A
646 #define PALMAS_ALARM_DAYS_REG 0x0B
647 #define PALMAS_ALARM_MONTHS_REG 0x0C
648 #define PALMAS_ALARM_YEARS_REG 0x0D
649 #define PALMAS_RTC_CTRL_REG 0x10
650 #define PALMAS_RTC_STATUS_REG 0x11
651 #define PALMAS_RTC_INTERRUPTS_REG 0x12
652 #define PALMAS_RTC_COMP_LSB_REG 0x13
653 #define PALMAS_RTC_COMP_MSB_REG 0x14
654 #define PALMAS_RTC_RES_PROG_REG 0x15
655 #define PALMAS_RTC_RESET_STATUS_REG 0x16
656
657 /* Bit definitions for SECONDS_REG */
658 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
659 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
660 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
661 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
662
663 /* Bit definitions for MINUTES_REG */
664 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
665 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
666 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
667 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
668
669 /* Bit definitions for HOURS_REG */
670 #define PALMAS_HOURS_REG_PM_NAM 0x80
671 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
672 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
673 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
674 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
675 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
676
677 /* Bit definitions for DAYS_REG */
678 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
679 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
680 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F
681 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
682
683 /* Bit definitions for MONTHS_REG */
684 #define PALMAS_MONTHS_REG_MONTH1 0x10
685 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
686 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
687 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
688
689 /* Bit definitions for YEARS_REG */
690 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
691 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
692 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
693 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
694
695 /* Bit definitions for WEEKS_REG */
696 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
697 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
698
699 /* Bit definitions for ALARM_SECONDS_REG */
700 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
701 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
702 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
703 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
704
705 /* Bit definitions for ALARM_MINUTES_REG */
706 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
707 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
708 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
709 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
710
711 /* Bit definitions for ALARM_HOURS_REG */
712 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
713 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
714 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
715 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
716 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
717 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
718
719 /* Bit definitions for ALARM_DAYS_REG */
720 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
721 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
722 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
723 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
724
725 /* Bit definitions for ALARM_MONTHS_REG */
726 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
727 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
728 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
729 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
730
731 /* Bit definitions for ALARM_YEARS_REG */
732 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
733 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
734 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
735 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
736
737 /* Bit definitions for RTC_CTRL_REG */
738 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
739 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
740 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
741 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
742 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
743 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
744 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
745 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
746 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
747 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
748 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
749 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
750 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
751 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
752 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
753 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
754
755 /* Bit definitions for RTC_STATUS_REG */
756 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
757 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
758 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
759 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
760 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
761 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
762 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
763 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
764 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
765 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
766 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
767 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
768 #define PALMAS_RTC_STATUS_REG_RUN 0x02
769 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
770
771 /* Bit definitions for RTC_INTERRUPTS_REG */
772 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
773 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
774 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
775 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
776 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
777 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
778 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
779 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
780
781 /* Bit definitions for RTC_COMP_LSB_REG */
782 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
783 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
784
785 /* Bit definitions for RTC_COMP_MSB_REG */
786 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
787 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
788
789 /* Bit definitions for RTC_RES_PROG_REG */
790 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
791 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
792
793 /* Bit definitions for RTC_RESET_STATUS_REG */
794 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
795 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
796
797 /* Registers for function BACKUP */
798 #define PALMAS_BACKUP0 0x00
799 #define PALMAS_BACKUP1 0x01
800 #define PALMAS_BACKUP2 0x02
801 #define PALMAS_BACKUP3 0x03
802 #define PALMAS_BACKUP4 0x04
803 #define PALMAS_BACKUP5 0x05
804 #define PALMAS_BACKUP6 0x06
805 #define PALMAS_BACKUP7 0x07
806
807 /* Bit definitions for BACKUP0 */
808 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF
809 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
810
811 /* Bit definitions for BACKUP1 */
812 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF
813 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
814
815 /* Bit definitions for BACKUP2 */
816 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF
817 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
818
819 /* Bit definitions for BACKUP3 */
820 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF
821 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
822
823 /* Bit definitions for BACKUP4 */
824 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF
825 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
826
827 /* Bit definitions for BACKUP5 */
828 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF
829 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
830
831 /* Bit definitions for BACKUP6 */
832 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF
833 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
834
835 /* Bit definitions for BACKUP7 */
836 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF
837 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
838
839 /* Registers for function SMPS */
840 #define PALMAS_SMPS12_CTRL 0x00
841 #define PALMAS_SMPS12_TSTEP 0x01
842 #define PALMAS_SMPS12_FORCE 0x02
843 #define PALMAS_SMPS12_VOLTAGE 0x03
844 #define PALMAS_SMPS3_CTRL 0x04
845 #define PALMAS_SMPS3_VOLTAGE 0x07
846 #define PALMAS_SMPS45_CTRL 0x08
847 #define PALMAS_SMPS45_TSTEP 0x09
848 #define PALMAS_SMPS45_FORCE 0x0A
849 #define PALMAS_SMPS45_VOLTAGE 0x0B
850 #define PALMAS_SMPS6_CTRL 0x0C
851 #define PALMAS_SMPS6_TSTEP 0x0D
852 #define PALMAS_SMPS6_FORCE 0x0E
853 #define PALMAS_SMPS6_VOLTAGE 0x0F
854 #define PALMAS_SMPS7_CTRL 0x10
855 #define PALMAS_SMPS7_VOLTAGE 0x13
856 #define PALMAS_SMPS8_CTRL 0x14
857 #define PALMAS_SMPS8_TSTEP 0x15
858 #define PALMAS_SMPS8_FORCE 0x16
859 #define PALMAS_SMPS8_VOLTAGE 0x17
860 #define PALMAS_SMPS9_CTRL 0x18
861 #define PALMAS_SMPS9_VOLTAGE 0x1B
862 #define PALMAS_SMPS10_CTRL 0x1C
863 #define PALMAS_SMPS10_STATUS 0x1F
864 #define PALMAS_SMPS_CTRL 0x24
865 #define PALMAS_SMPS_PD_CTRL 0x25
866 #define PALMAS_SMPS_DITHER_EN 0x26
867 #define PALMAS_SMPS_THERMAL_EN 0x27
868 #define PALMAS_SMPS_THERMAL_STATUS 0x28
869 #define PALMAS_SMPS_SHORT_STATUS 0x29
870 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
871 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
872 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
873
874 /* Bit definitions for SMPS12_CTRL */
875 #define PALMAS_SMPS12_CTRL_WR_S 0x80
876 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
877 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
878 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
879 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
880 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
881 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
882 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
883 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
884 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
885
886 /* Bit definitions for SMPS12_TSTEP */
887 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
888 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
889
890 /* Bit definitions for SMPS12_FORCE */
891 #define PALMAS_SMPS12_FORCE_CMD 0x80
892 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
893 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
894 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
895
896 /* Bit definitions for SMPS12_VOLTAGE */
897 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
898 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
899 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
900 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
901
902 /* Bit definitions for SMPS3_CTRL */
903 #define PALMAS_SMPS3_CTRL_WR_S 0x80
904 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
905 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
906 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
907 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
908 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
909 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
910 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
911
912 /* Bit definitions for SMPS3_VOLTAGE */
913 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
914 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
915 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
916 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
917
918 /* Bit definitions for SMPS45_CTRL */
919 #define PALMAS_SMPS45_CTRL_WR_S 0x80
920 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
921 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
922 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
923 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
924 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
925 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
926 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
927 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
928 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
929
930 /* Bit definitions for SMPS45_TSTEP */
931 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
932 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
933
934 /* Bit definitions for SMPS45_FORCE */
935 #define PALMAS_SMPS45_FORCE_CMD 0x80
936 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
937 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
938 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
939
940 /* Bit definitions for SMPS45_VOLTAGE */
941 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
942 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
943 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
944 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
945
946 /* Bit definitions for SMPS6_CTRL */
947 #define PALMAS_SMPS6_CTRL_WR_S 0x80
948 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
949 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
950 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
951 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
952 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
953 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
954 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
955 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
956 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
957
958 /* Bit definitions for SMPS6_TSTEP */
959 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
960 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
961
962 /* Bit definitions for SMPS6_FORCE */
963 #define PALMAS_SMPS6_FORCE_CMD 0x80
964 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
965 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
966 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
967
968 /* Bit definitions for SMPS6_VOLTAGE */
969 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
970 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
971 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
972 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
973
974 /* Bit definitions for SMPS7_CTRL */
975 #define PALMAS_SMPS7_CTRL_WR_S 0x80
976 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
977 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
978 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
979 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
980 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
981 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
982 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
983
984 /* Bit definitions for SMPS7_VOLTAGE */
985 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
986 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
987 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
988 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
989
990 /* Bit definitions for SMPS8_CTRL */
991 #define PALMAS_SMPS8_CTRL_WR_S 0x80
992 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
993 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
994 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
995 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
996 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
997 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
998 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
999 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1000 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1001
1002 /* Bit definitions for SMPS8_TSTEP */
1003 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1004 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1005
1006 /* Bit definitions for SMPS8_FORCE */
1007 #define PALMAS_SMPS8_FORCE_CMD 0x80
1008 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1009 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1010 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1011
1012 /* Bit definitions for SMPS8_VOLTAGE */
1013 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1014 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1015 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1016 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1017
1018 /* Bit definitions for SMPS9_CTRL */
1019 #define PALMAS_SMPS9_CTRL_WR_S 0x80
1020 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1021 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1022 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1023 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1024 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1025 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1026 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1027
1028 /* Bit definitions for SMPS9_VOLTAGE */
1029 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1030 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1031 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1032 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1033
1034 /* Bit definitions for SMPS10_CTRL */
1035 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1036 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1037 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1038 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1039
1040 /* Bit definitions for SMPS10_STATUS */
1041 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1042 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1043
1044 /* Bit definitions for SMPS_CTRL */
1045 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1046 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1047 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1048 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1049 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1050 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1051 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1052 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1053
1054 /* Bit definitions for SMPS_PD_CTRL */
1055 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1056 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1057 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1058 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1059 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1060 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1061 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1062 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1063 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1064 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1065 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1066 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1067 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1068 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1069
1070 /* Bit definitions for SMPS_THERMAL_EN */
1071 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1072 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1073 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1074 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1075 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1076 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1077 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1078 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1079 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1080 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1081
1082 /* Bit definitions for SMPS_THERMAL_STATUS */
1083 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1084 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1085 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1086 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1087 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1088 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1089 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1090 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1091 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1092 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1093
1094 /* Bit definitions for SMPS_SHORT_STATUS */
1095 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1096 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1097 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1098 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1099 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1100 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1101 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1102 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1103 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1104 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1105 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1106 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1107 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1108 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1109 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1110 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1111
1112 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1113 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1114 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1115 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1116 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1117 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1118 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1119 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1120 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1121 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1122 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1123 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1124 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1125 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1126 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1127
1128 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1129 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1130 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1131 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1132 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1133 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1134 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1135 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1136 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1137 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1138 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1139 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1140 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1141 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1142 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1143 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1144 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1145
1146 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1147 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1148 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1149 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1150 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1151 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1152 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1153 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1154 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1155
1156 /* Registers for function LDO */
1157 #define PALMAS_LDO1_CTRL 0x00
1158 #define PALMAS_LDO1_VOLTAGE 0x01
1159 #define PALMAS_LDO2_CTRL 0x02
1160 #define PALMAS_LDO2_VOLTAGE 0x03
1161 #define PALMAS_LDO3_CTRL 0x04
1162 #define PALMAS_LDO3_VOLTAGE 0x05
1163 #define PALMAS_LDO4_CTRL 0x06
1164 #define PALMAS_LDO4_VOLTAGE 0x07
1165 #define PALMAS_LDO5_CTRL 0x08
1166 #define PALMAS_LDO5_VOLTAGE 0x09
1167 #define PALMAS_LDO6_CTRL 0x0A
1168 #define PALMAS_LDO6_VOLTAGE 0x0B
1169 #define PALMAS_LDO7_CTRL 0x0C
1170 #define PALMAS_LDO7_VOLTAGE 0x0D
1171 #define PALMAS_LDO8_CTRL 0x0E
1172 #define PALMAS_LDO8_VOLTAGE 0x0F
1173 #define PALMAS_LDO9_CTRL 0x10
1174 #define PALMAS_LDO9_VOLTAGE 0x11
1175 #define PALMAS_LDOLN_CTRL 0x12
1176 #define PALMAS_LDOLN_VOLTAGE 0x13
1177 #define PALMAS_LDOUSB_CTRL 0x14
1178 #define PALMAS_LDOUSB_VOLTAGE 0x15
1179 #define PALMAS_LDO_CTRL 0x1A
1180 #define PALMAS_LDO_PD_CTRL1 0x1B
1181 #define PALMAS_LDO_PD_CTRL2 0x1C
1182 #define PALMAS_LDO_SHORT_STATUS1 0x1D
1183 #define PALMAS_LDO_SHORT_STATUS2 0x1E
1184
1185 /* Bit definitions for LDO1_CTRL */
1186 #define PALMAS_LDO1_CTRL_WR_S 0x80
1187 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1188 #define PALMAS_LDO1_CTRL_STATUS 0x10
1189 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1190 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1191 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1192 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1193 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1194
1195 /* Bit definitions for LDO1_VOLTAGE */
1196 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1197 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1198
1199 /* Bit definitions for LDO2_CTRL */
1200 #define PALMAS_LDO2_CTRL_WR_S 0x80
1201 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1202 #define PALMAS_LDO2_CTRL_STATUS 0x10
1203 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1204 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1205 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1206 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1207 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1208
1209 /* Bit definitions for LDO2_VOLTAGE */
1210 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1211 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1212
1213 /* Bit definitions for LDO3_CTRL */
1214 #define PALMAS_LDO3_CTRL_WR_S 0x80
1215 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1216 #define PALMAS_LDO3_CTRL_STATUS 0x10
1217 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1218 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1219 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1220 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1221 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1222
1223 /* Bit definitions for LDO3_VOLTAGE */
1224 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1225 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1226
1227 /* Bit definitions for LDO4_CTRL */
1228 #define PALMAS_LDO4_CTRL_WR_S 0x80
1229 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1230 #define PALMAS_LDO4_CTRL_STATUS 0x10
1231 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1232 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1233 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1234 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1235 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1236
1237 /* Bit definitions for LDO4_VOLTAGE */
1238 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1239 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1240
1241 /* Bit definitions for LDO5_CTRL */
1242 #define PALMAS_LDO5_CTRL_WR_S 0x80
1243 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1244 #define PALMAS_LDO5_CTRL_STATUS 0x10
1245 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1246 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1247 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1248 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1249 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1250
1251 /* Bit definitions for LDO5_VOLTAGE */
1252 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1253 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1254
1255 /* Bit definitions for LDO6_CTRL */
1256 #define PALMAS_LDO6_CTRL_WR_S 0x80
1257 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1258 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1259 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1260 #define PALMAS_LDO6_CTRL_STATUS 0x10
1261 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1262 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1263 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1264 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1265 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1266
1267 /* Bit definitions for LDO6_VOLTAGE */
1268 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1269 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1270
1271 /* Bit definitions for LDO7_CTRL */
1272 #define PALMAS_LDO7_CTRL_WR_S 0x80
1273 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1274 #define PALMAS_LDO7_CTRL_STATUS 0x10
1275 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1276 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1277 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1278 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1279 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1280
1281 /* Bit definitions for LDO7_VOLTAGE */
1282 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1283 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1284
1285 /* Bit definitions for LDO8_CTRL */
1286 #define PALMAS_LDO8_CTRL_WR_S 0x80
1287 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1288 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1289 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1290 #define PALMAS_LDO8_CTRL_STATUS 0x10
1291 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1292 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1293 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1294 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1295 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1296
1297 /* Bit definitions for LDO8_VOLTAGE */
1298 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1299 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1300
1301 /* Bit definitions for LDO9_CTRL */
1302 #define PALMAS_LDO9_CTRL_WR_S 0x80
1303 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1304 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1305 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1306 #define PALMAS_LDO9_CTRL_STATUS 0x10
1307 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1308 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1309 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1310 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1311 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1312
1313 /* Bit definitions for LDO9_VOLTAGE */
1314 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1315 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1316
1317 /* Bit definitions for LDOLN_CTRL */
1318 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1319 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1320 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1321 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1322 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1323 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1324 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1325 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1326
1327 /* Bit definitions for LDOLN_VOLTAGE */
1328 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1329 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1330
1331 /* Bit definitions for LDOUSB_CTRL */
1332 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1333 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1334 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1335 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1336 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1337 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1338 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1339 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1340
1341 /* Bit definitions for LDOUSB_VOLTAGE */
1342 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1343 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1344
1345 /* Bit definitions for LDO_CTRL */
1346 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1347 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1348
1349 /* Bit definitions for LDO_PD_CTRL1 */
1350 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1351 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1352 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1353 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1354 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1355 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1356 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1357 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1358 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1359 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1360 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1361 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1362 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1363 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1364 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1365 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1366
1367 /* Bit definitions for LDO_PD_CTRL2 */
1368 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1369 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1370 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1371 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1372 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1373 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1374
1375 /* Bit definitions for LDO_SHORT_STATUS1 */
1376 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1377 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1378 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1379 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1380 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1381 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1382 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1383 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1384 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1385 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1386 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1387 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1388 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1389 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1390 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1391 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1392
1393 /* Bit definitions for LDO_SHORT_STATUS2 */
1394 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1395 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1396 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1397 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1398 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1399 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1400 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1401 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1402
1403 /* Registers for function PMU_CONTROL */
1404 #define PALMAS_DEV_CTRL 0x00
1405 #define PALMAS_POWER_CTRL 0x01
1406 #define PALMAS_VSYS_LO 0x02
1407 #define PALMAS_VSYS_MON 0x03
1408 #define PALMAS_VBAT_MON 0x04
1409 #define PALMAS_WATCHDOG 0x05
1410 #define PALMAS_BOOT_STATUS 0x06
1411 #define PALMAS_BATTERY_BOUNCE 0x07
1412 #define PALMAS_BACKUP_BATTERY_CTRL 0x08
1413 #define PALMAS_LONG_PRESS_KEY 0x09
1414 #define PALMAS_OSC_THERM_CTRL 0x0A
1415 #define PALMAS_BATDEBOUNCING 0x0B
1416 #define PALMAS_SWOFF_HWRST 0x0F
1417 #define PALMAS_SWOFF_COLDRST 0x10
1418 #define PALMAS_SWOFF_STATUS 0x11
1419 #define PALMAS_PMU_CONFIG 0x12
1420 #define PALMAS_SPARE 0x14
1421 #define PALMAS_PMU_SECONDARY_INT 0x15
1422 #define PALMAS_SW_REVISION 0x17
1423 #define PALMAS_EXT_CHRG_CTRL 0x18
1424 #define PALMAS_PMU_SECONDARY_INT2 0x19
1425
1426 /* Bit definitions for DEV_CTRL */
1427 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1428 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1429 #define PALMAS_DEV_CTRL_SW_RST 0x02
1430 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1431 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1432 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1433
1434 /* Bit definitions for POWER_CTRL */
1435 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1436 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1437 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1438 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1439 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1440 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1441
1442 /* Bit definitions for VSYS_LO */
1443 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1444 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1445
1446 /* Bit definitions for VSYS_MON */
1447 #define PALMAS_VSYS_MON_ENABLE 0x80
1448 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1449 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1450 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1451
1452 /* Bit definitions for VBAT_MON */
1453 #define PALMAS_VBAT_MON_ENABLE 0x80
1454 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1455 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1456 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1457
1458 /* Bit definitions for WATCHDOG */
1459 #define PALMAS_WATCHDOG_LOCK 0x20
1460 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1461 #define PALMAS_WATCHDOG_ENABLE 0x10
1462 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1463 #define PALMAS_WATCHDOG_MODE 0x08
1464 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1465 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1466 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1467
1468 /* Bit definitions for BOOT_STATUS */
1469 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1470 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1471 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1472 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1473
1474 /* Bit definitions for BATTERY_BOUNCE */
1475 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1476 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1477
1478 /* Bit definitions for BACKUP_BATTERY_CTRL */
1479 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1480 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1481 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1482 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1483 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1484 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1485 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1486 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1487 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1488 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1489 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1490 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1491 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1492 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1493
1494 /* Bit definitions for LONG_PRESS_KEY */
1495 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1496 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1497 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1498 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1499 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1500 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1501 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1502 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1503
1504 /* Bit definitions for OSC_THERM_CTRL */
1505 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1506 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1507 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1508 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1509 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1510 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1511 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1512 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1513 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1514 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1515 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1516 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1517 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1518 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1519
1520 /* Bit definitions for BATDEBOUNCING */
1521 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1522 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1523 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1524 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1525 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1526 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1527
1528 /* Bit definitions for SWOFF_HWRST */
1529 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1530 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1531 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1532 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1533 #define PALMAS_SWOFF_HWRST_WTD 0x20
1534 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1535 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1536 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1537 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1538 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1539 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1540 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1541 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1542 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1543 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1544 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1545
1546 /* Bit definitions for SWOFF_COLDRST */
1547 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1548 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1549 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1550 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1551 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1552 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1553 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1554 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1555 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1556 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1557 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1558 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1559 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1560 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1561 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1562 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1563
1564 /* Bit definitions for SWOFF_STATUS */
1565 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1566 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1567 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1568 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1569 #define PALMAS_SWOFF_STATUS_WTD 0x20
1570 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1571 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1572 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1573 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1574 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1575 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1576 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1577 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1578 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1579 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1580 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1581
1582 /* Bit definitions for PMU_CONFIG */
1583 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1584 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1585 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1586 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1587 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1588 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1589 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1590 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1591 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1592 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1593
1594 /* Bit definitions for SPARE */
1595 #define PALMAS_SPARE_SPARE_MASK 0xf8
1596 #define PALMAS_SPARE_SPARE_SHIFT 0x03
1597 #define PALMAS_SPARE_REGEN3_OD 0x04
1598 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1599 #define PALMAS_SPARE_REGEN2_OD 0x02
1600 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1601 #define PALMAS_SPARE_REGEN1_OD 0x01
1602 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1603
1604 /* Bit definitions for PMU_SECONDARY_INT */
1605 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1606 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1607 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1608 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1609 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1610 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1611 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1612 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1613 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1614 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1615 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1616 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1617 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1618 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1619 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1620 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1621
1622 /* Bit definitions for SW_REVISION */
1623 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1624 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1625
1626 /* Bit definitions for EXT_CHRG_CTRL */
1627 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1628 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1629 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1630 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1631 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1632 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1633 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1634 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1635 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1636 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1637 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1638 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1639
1640 /* Bit definitions for PMU_SECONDARY_INT2 */
1641 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1642 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1643 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1644 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1645 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1646 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1647 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1648 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1649
1650 /* Registers for function RESOURCE */
1651 #define PALMAS_CLK32KG_CTRL 0x00
1652 #define PALMAS_CLK32KGAUDIO_CTRL 0x01
1653 #define PALMAS_REGEN1_CTRL 0x02
1654 #define PALMAS_REGEN2_CTRL 0x03
1655 #define PALMAS_SYSEN1_CTRL 0x04
1656 #define PALMAS_SYSEN2_CTRL 0x05
1657 #define PALMAS_NSLEEP_RES_ASSIGN 0x06
1658 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1659 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1660 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1661 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1662 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1663 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1664 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1665 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1666 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1667 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1668 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1669 #define PALMAS_REGEN3_CTRL 0x12
1670
1671 /* Bit definitions for CLK32KG_CTRL */
1672 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1673 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1674 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1675 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1676 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1677 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1678
1679 /* Bit definitions for CLK32KGAUDIO_CTRL */
1680 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1681 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1682 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1683 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1684 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1685 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1686 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1687 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1688
1689 /* Bit definitions for REGEN1_CTRL */
1690 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1691 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1692 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1693 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1694 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1695 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1696
1697 /* Bit definitions for REGEN2_CTRL */
1698 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1699 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1700 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1701 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1702 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1703 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1704
1705 /* Bit definitions for SYSEN1_CTRL */
1706 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1707 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1708 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1709 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1710 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1711 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1712
1713 /* Bit definitions for SYSEN2_CTRL */
1714 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1715 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1716 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1717 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1718 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1719 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1720
1721 /* Bit definitions for NSLEEP_RES_ASSIGN */
1722 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1723 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1724 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1725 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1726 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1727 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1728 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1729 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1730 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1731 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1732 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1733 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1734 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1735 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1736
1737 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1738 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1739 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1740 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1741 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1742 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1743 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1744 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1745 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1746 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1747 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1748 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1749 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1750 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1751 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1752 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1753 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1754
1755 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1756 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1757 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1758 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1759 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1760 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1761 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1762 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1763 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1764 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1765 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1766 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1767 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1768 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1769 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1770 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1771 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1772
1773 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1774 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1775 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1776 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1777 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1778 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1779 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1780
1781 /* Bit definitions for ENABLE1_RES_ASSIGN */
1782 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1783 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1784 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1785 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1786 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1787 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1788 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1789 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1790 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1791 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1792 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1793 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1794 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1795 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1796
1797 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1798 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1799 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1800 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1801 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1802 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1803 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1804 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1805 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1806 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1807 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1808 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1809 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1810 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1811 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1812 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1813 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1814
1815 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1816 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1817 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1818 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1819 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1820 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1821 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1822 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1823 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1824 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1825 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1826 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1827 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1828 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1829 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1830 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1831 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1832
1833 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1834 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1835 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1836 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1837 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1838 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1839 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1840
1841 /* Bit definitions for ENABLE2_RES_ASSIGN */
1842 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1843 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1844 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1845 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1846 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1847 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1848 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1849 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1850 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1851 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1852 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1853 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1854 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1855 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1856
1857 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1858 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1859 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1860 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1861 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1862 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1863 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1864 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1865 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1866 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1867 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1868 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1869 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1870 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1871 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1872 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1873 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1874
1875 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1876 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1877 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1878 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1879 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1880 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1881 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1882 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1883 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1884 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1885 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1886 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1887 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1888 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1889 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1890 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1891 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1892
1893 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1894 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1895 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1896 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1897 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1898 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1899 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1900
1901 /* Bit definitions for REGEN3_CTRL */
1902 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1903 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1904 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1905 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1906 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1907 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1908
1909 /* Registers for function PAD_CONTROL */
1910 #define PALMAS_OD_OUTPUT_CTRL2 0x02
1911 #define PALMAS_POLARITY_CTRL2 0x03
1912 #define PALMAS_PU_PD_INPUT_CTRL1 0x04
1913 #define PALMAS_PU_PD_INPUT_CTRL2 0x05
1914 #define PALMAS_PU_PD_INPUT_CTRL3 0x06
1915 #define PALMAS_PU_PD_INPUT_CTRL5 0x07
1916 #define PALMAS_OD_OUTPUT_CTRL 0x08
1917 #define PALMAS_POLARITY_CTRL 0x09
1918 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1919 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1920 #define PALMAS_I2C_SPI 0x0C
1921 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1922 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1923 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1924
1925 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1926 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1927 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1928 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1929 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1930 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1931 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1932 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1933 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1934 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1935 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1936
1937 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1938 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1939 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1940 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1941 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1942 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1943 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1944 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1945 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1946 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1947 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1948 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1949 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1950
1951 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1952 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1953 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1954 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1955 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1956 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1957 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1958 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1959 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1960
1961 /* Bit definitions for OD_OUTPUT_CTRL */
1962 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1963 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1964 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1965 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1966 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1967 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1968 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1969 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1970
1971 /* Bit definitions for POLARITY_CTRL */
1972 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1973 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1974 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1975 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
1976 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1977 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
1978 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1979 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
1980 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1981 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
1982 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1983 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
1984 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1985 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
1986 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1987 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
1988
1989 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1990 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1991 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
1992 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1993 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
1994 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1995 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
1996 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1997 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
1998 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1999 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2000 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2001 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2002
2003 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2004 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2005 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2006 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2007 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2008 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2009 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2010 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2011 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2012
2013 /* Bit definitions for I2C_SPI */
2014 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2015 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2016 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2017 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2018 #define PALMAS_I2C_SPI_ID_I2C2 0x20
2019 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2020 #define PALMAS_I2C_SPI_I2C_SPI 0x10
2021 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2022 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2023 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2024
2025 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2026 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2027 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2028 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2029 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2030 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2031 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2032 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2033 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2034
2035 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2036 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2037 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2038 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2039 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2040
2041 /* Registers for function LED_PWM */
2042 #define PALMAS_LED_PERIOD_CTRL 0x00
2043 #define PALMAS_LED_CTRL 0x01
2044 #define PALMAS_PWM_CTRL1 0x02
2045 #define PALMAS_PWM_CTRL2 0x03
2046
2047 /* Bit definitions for LED_PERIOD_CTRL */
2048 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2049 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2050 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2051 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2052
2053 /* Bit definitions for LED_CTRL */
2054 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2055 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2056 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2057 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2058 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2059 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2060 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2061 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2062
2063 /* Bit definitions for PWM_CTRL1 */
2064 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2065 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2066 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2067 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2068
2069 /* Bit definitions for PWM_CTRL2 */
2070 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2071 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2072
2073 /* Registers for function INTERRUPT */
2074 #define PALMAS_INT1_STATUS 0x00
2075 #define PALMAS_INT1_MASK 0x01
2076 #define PALMAS_INT1_LINE_STATE 0x02
2077 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2078 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2079 #define PALMAS_INT2_STATUS 0x05
2080 #define PALMAS_INT2_MASK 0x06
2081 #define PALMAS_INT2_LINE_STATE 0x07
2082 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2083 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2084 #define PALMAS_INT3_STATUS 0x0A
2085 #define PALMAS_INT3_MASK 0x0B
2086 #define PALMAS_INT3_LINE_STATE 0x0C
2087 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2088 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2089 #define PALMAS_INT4_STATUS 0x0F
2090 #define PALMAS_INT4_MASK 0x10
2091 #define PALMAS_INT4_LINE_STATE 0x11
2092 #define PALMAS_INT4_EDGE_DETECT1 0x12
2093 #define PALMAS_INT4_EDGE_DETECT2 0x13
2094 #define PALMAS_INT_CTRL 0x14
2095
2096 /* Bit definitions for INT1_STATUS */
2097 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
2098 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2099 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
2100 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2101 #define PALMAS_INT1_STATUS_HOTDIE 0x20
2102 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2103 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
2104 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2105 #define PALMAS_INT1_STATUS_RPWRON 0x08
2106 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2107 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2108 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2109 #define PALMAS_INT1_STATUS_PWRON 0x02
2110 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2111 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2112 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2113
2114 /* Bit definitions for INT1_MASK */
2115 #define PALMAS_INT1_MASK_VBAT_MON 0x80
2116 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2117 #define PALMAS_INT1_MASK_VSYS_MON 0x40
2118 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2119 #define PALMAS_INT1_MASK_HOTDIE 0x20
2120 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2121 #define PALMAS_INT1_MASK_PWRDOWN 0x10
2122 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2123 #define PALMAS_INT1_MASK_RPWRON 0x08
2124 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2125 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2126 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2127 #define PALMAS_INT1_MASK_PWRON 0x02
2128 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2129 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2130 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2131
2132 /* Bit definitions for INT1_LINE_STATE */
2133 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2134 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2135 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2136 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2137 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2138 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2139 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2140 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2141 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2142 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2143 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2144 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2145 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
2146 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2147 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2148 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2149
2150 /* Bit definitions for INT2_STATUS */
2151 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2152 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2153 #define PALMAS_INT2_STATUS_SHORT 0x40
2154 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2155 #define PALMAS_INT2_STATUS_FBI_BB 0x20
2156 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2157 #define PALMAS_INT2_STATUS_RESET_IN 0x10
2158 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2159 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2160 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2161 #define PALMAS_INT2_STATUS_WDT 0x04
2162 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2163 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2164 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2165 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2166 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2167
2168 /* Bit definitions for INT2_MASK */
2169 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
2170 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2171 #define PALMAS_INT2_MASK_SHORT 0x40
2172 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2173 #define PALMAS_INT2_MASK_FBI_BB 0x20
2174 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2175 #define PALMAS_INT2_MASK_RESET_IN 0x10
2176 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2177 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
2178 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2179 #define PALMAS_INT2_MASK_WDT 0x04
2180 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2181 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
2182 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2183 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
2184 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2185
2186 /* Bit definitions for INT2_LINE_STATE */
2187 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2188 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2189 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
2190 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2191 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2192 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2193 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2194 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2195 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2196 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2197 #define PALMAS_INT2_LINE_STATE_WDT 0x04
2198 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2199 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2200 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2201 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2202 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2203
2204 /* Bit definitions for INT3_STATUS */
2205 #define PALMAS_INT3_STATUS_VBUS 0x80
2206 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2207 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2208 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2209 #define PALMAS_INT3_STATUS_ID 0x20
2210 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2211 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2212 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2213 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2214 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2215 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2216 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2217 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2218 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2219 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2220 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2221
2222 /* Bit definitions for INT3_MASK */
2223 #define PALMAS_INT3_MASK_VBUS 0x80
2224 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2225 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2226 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2227 #define PALMAS_INT3_MASK_ID 0x20
2228 #define PALMAS_INT3_MASK_ID_SHIFT 0x05
2229 #define PALMAS_INT3_MASK_ID_OTG 0x10
2230 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2231 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2232 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2233 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2234 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2235 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2236 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2237 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2238 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2239
2240 /* Bit definitions for INT3_LINE_STATE */
2241 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2242 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2243 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2244 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2245 #define PALMAS_INT3_LINE_STATE_ID 0x20
2246 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2247 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2248 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2249 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2250 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2251 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2252 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2253 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2254 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2255 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2256 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2257
2258 /* Bit definitions for INT4_STATUS */
2259 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2260 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2261 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2262 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2263 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2264 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2265 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2266 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2267 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2268 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2269 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2270 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2271 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2272 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2273 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2274 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2275
2276 /* Bit definitions for INT4_MASK */
2277 #define PALMAS_INT4_MASK_GPIO_7 0x80
2278 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2279 #define PALMAS_INT4_MASK_GPIO_6 0x40
2280 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2281 #define PALMAS_INT4_MASK_GPIO_5 0x20
2282 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2283 #define PALMAS_INT4_MASK_GPIO_4 0x10
2284 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2285 #define PALMAS_INT4_MASK_GPIO_3 0x08
2286 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2287 #define PALMAS_INT4_MASK_GPIO_2 0x04
2288 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2289 #define PALMAS_INT4_MASK_GPIO_1 0x02
2290 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2291 #define PALMAS_INT4_MASK_GPIO_0 0x01
2292 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2293
2294 /* Bit definitions for INT4_LINE_STATE */
2295 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2296 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2297 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2298 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2299 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2300 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2301 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2302 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2303 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2304 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2305 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2306 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2307 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2308 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2309 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2310 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2311
2312 /* Bit definitions for INT4_EDGE_DETECT1 */
2313 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2314 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2315 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2316 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2317 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2318 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2319 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2320 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2321 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2322 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2323 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2324 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2325 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2326 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2327 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2328 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2329
2330 /* Bit definitions for INT4_EDGE_DETECT2 */
2331 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2332 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2333 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2334 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2335 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2336 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2337 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2338 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2339 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2340 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2341 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2342 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2343 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2344 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2345 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2346 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2347
2348 /* Bit definitions for INT_CTRL */
2349 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2350 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2351 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2352 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2353
2354 /* Registers for function USB_OTG */
2355 #define PALMAS_USB_WAKEUP 0x03
2356 #define PALMAS_USB_VBUS_CTRL_SET 0x04
2357 #define PALMAS_USB_VBUS_CTRL_CLR 0x05
2358 #define PALMAS_USB_ID_CTRL_SET 0x06
2359 #define PALMAS_USB_ID_CTRL_CLEAR 0x07
2360 #define PALMAS_USB_VBUS_INT_SRC 0x08
2361 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2362 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2363 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2364 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2365 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2366 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2367 #define PALMAS_USB_ID_INT_SRC 0x0F
2368 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2369 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2370 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2371 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2372 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2373 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2374 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2375 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2376 #define PALMAS_USB_OTG_ADP_LOW 0x18
2377 #define PALMAS_USB_OTG_ADP_RISE 0x19
2378 #define PALMAS_USB_OTG_REVISION 0x1A
2379
2380 /* Bit definitions for USB_WAKEUP */
2381 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2382 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2383
2384 /* Bit definitions for USB_VBUS_CTRL_SET */
2385 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2386 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2387 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2388 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2389 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2390 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2391 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2392 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2393 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2394 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2395
2396 /* Bit definitions for USB_VBUS_CTRL_CLR */
2397 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2398 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2399 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2400 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2401 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2402 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2403 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2404 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2405 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2406 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2407
2408 /* Bit definitions for USB_ID_CTRL_SET */
2409 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2410 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2411 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2412 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2413 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2414 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2415 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2416 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2417 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2418 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2419 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2420 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2421
2422 /* Bit definitions for USB_ID_CTRL_CLEAR */
2423 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2424 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2425 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2426 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2427 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2428 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2429 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2430 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2431 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2432 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2433 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2434 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2435
2436 /* Bit definitions for USB_VBUS_INT_SRC */
2437 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2438 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2439 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2440 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2441 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2442 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2443 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2444 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2445 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2446 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2447 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2448 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2449 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2450 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2451
2452 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2453 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2454 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2455 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2456 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2457 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2458 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2459 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2460 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2461 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2462 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2463 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2464 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2465 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2466 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2467 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2468 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2469
2470 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2471 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2472 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2473 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2474 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2475 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2476 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2477 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2478 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2479 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2480 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2481 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2482 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2483 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2484 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2485 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2486 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2487
2488 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2489 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2490 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2491 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2492 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2493 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2494 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2495 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2496 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2497 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2498 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2499 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2500 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2501 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2502 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2503
2504 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2505 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2506 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2507 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2508 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2509 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2510 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2511 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2512 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2513 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2514 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2515 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2516 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2517 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2518 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2519
2520 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2521 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2522 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2523 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2524 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2525 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2526 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2527 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2528 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2529 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2530 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2531 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2532 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2533 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2534 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2535 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2536 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2537
2538 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2539 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2540 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2541 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2542 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2543 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2544 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2545 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2546 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2547 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2548 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2549 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2550 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2551 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2552 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2553 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2554 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2555
2556 /* Bit definitions for USB_ID_INT_SRC */
2557 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2558 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2559 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2560 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2561 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2562 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2563 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2564 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2565 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2566 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2567
2568 /* Bit definitions for USB_ID_INT_LATCH_SET */
2569 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2570 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2571 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2572 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2573 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2574 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2575 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2576 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2577 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2578 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2579
2580 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2581 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2582 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2583 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2584 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2585 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2586 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2587 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2588 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2589 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2590 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2591
2592 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2593 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2594 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2595 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2596 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2597 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2598 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2599 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2600 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2601 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2602 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2603
2604 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2605 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2606 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2607 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2608 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2609 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2610 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2611 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2612 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2613 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2614 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2615
2616 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2617 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2618 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2619 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2620 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2621 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2622 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2623 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2624 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2625 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2626 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2627
2628 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2629 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2630 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2631 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2632 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2633 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2634 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2635 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2636 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2637 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2638 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2639
2640 /* Bit definitions for USB_OTG_ADP_CTRL */
2641 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2642 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2643 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2644 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2645
2646 /* Bit definitions for USB_OTG_ADP_HIGH */
2647 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2648 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2649
2650 /* Bit definitions for USB_OTG_ADP_LOW */
2651 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2652 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2653
2654 /* Bit definitions for USB_OTG_ADP_RISE */
2655 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2656 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2657
2658 /* Bit definitions for USB_OTG_REVISION */
2659 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2660 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2661
2662 /* Registers for function VIBRATOR */
2663 #define PALMAS_VIBRA_CTRL 0x00
2664
2665 /* Bit definitions for VIBRA_CTRL */
2666 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2667 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2668 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2669 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2670
2671 /* Registers for function GPIO */
2672 #define PALMAS_GPIO_DATA_IN 0x00
2673 #define PALMAS_GPIO_DATA_DIR 0x01
2674 #define PALMAS_GPIO_DATA_OUT 0x02
2675 #define PALMAS_GPIO_DEBOUNCE_EN 0x03
2676 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2677 #define PALMAS_GPIO_SET_DATA_OUT 0x05
2678 #define PALMAS_PU_PD_GPIO_CTRL1 0x06
2679 #define PALMAS_PU_PD_GPIO_CTRL2 0x07
2680 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2681 #define PALMAS_GPIO_DATA_IN2 0x09
2682 #define PALMAS_GPIO_DATA_DIR2 0x0A
2683 #define PALMAS_GPIO_DATA_OUT2 0x0B
2684 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2685 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2686 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2687 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2688 #define PALMAS_PU_PD_GPIO_CTRL4 0x10
2689 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2690
2691 /* Bit definitions for GPIO_DATA_IN */
2692 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2693 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2694 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2695 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2696 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2697 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2698 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2699 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2700 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2701 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2702 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2703 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2704 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2705 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2706 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2707 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2708
2709 /* Bit definitions for GPIO_DATA_DIR */
2710 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2711 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2712 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2713 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2714 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2715 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2716 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2717 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2718 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2719 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2720 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2721 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2722 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2723 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2724 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2725 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2726
2727 /* Bit definitions for GPIO_DATA_OUT */
2728 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2729 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2730 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2731 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2732 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2733 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2734 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2735 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2736 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2737 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2738 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2739 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2740 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2741 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2742 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2743 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2744
2745 /* Bit definitions for GPIO_DEBOUNCE_EN */
2746 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2747 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2748 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2749 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2750 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2751 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2752 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2753 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2754 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2755 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2756 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2757 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2758 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2759 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2760 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2761 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2762
2763 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2764 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2765 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2766 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2767 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2768 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2769 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2770 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2771 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2772 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2773 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2774 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2775 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2776 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2777 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2778 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2779 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2780
2781 /* Bit definitions for GPIO_SET_DATA_OUT */
2782 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2783 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2784 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2785 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2786 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2787 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2788 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2789 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2790 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2791 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2792 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2793 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2794 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2795 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2796 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2797 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2798
2799 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2800 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2801 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2802 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2803 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2804 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2805 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2806 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2807 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2808 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2809 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2810 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2811 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2812
2813 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2814 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2815 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2816 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2817 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2818 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2819 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2820 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2821 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2822 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2823 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2824 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2825 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2826 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2827 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2828
2829 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2830 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2831 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2832 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2833 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2834 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2835 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2836
2837 /* Registers for function GPADC */
2838 #define PALMAS_GPADC_CTRL1 0x00
2839 #define PALMAS_GPADC_CTRL2 0x01
2840 #define PALMAS_GPADC_RT_CTRL 0x02
2841 #define PALMAS_GPADC_AUTO_CTRL 0x03
2842 #define PALMAS_GPADC_STATUS 0x04
2843 #define PALMAS_GPADC_RT_SELECT 0x05
2844 #define PALMAS_GPADC_RT_CONV0_LSB 0x06
2845 #define PALMAS_GPADC_RT_CONV0_MSB 0x07
2846 #define PALMAS_GPADC_AUTO_SELECT 0x08
2847 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2848 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2849 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2850 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2851 #define PALMAS_GPADC_SW_SELECT 0x0D
2852 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2853 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2854 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2855 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2856 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2857 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2858 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2859 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2860
2861 /* Bit definitions for GPADC_CTRL1 */
2862 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2863 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2864 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2865 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2866 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2867 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2868 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2869 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2870 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2871 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2872
2873 /* Bit definitions for GPADC_CTRL2 */
2874 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2875 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2876
2877 /* Bit definitions for GPADC_RT_CTRL */
2878 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2879 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2880 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2881 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2882
2883 /* Bit definitions for GPADC_AUTO_CTRL */
2884 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2885 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2886 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2887 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2888 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2889 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2890 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2891 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2892 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2893 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2894
2895 /* Bit definitions for GPADC_STATUS */
2896 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2897 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2898
2899 /* Bit definitions for GPADC_RT_SELECT */
2900 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2901 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2902 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2903 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2904
2905 /* Bit definitions for GPADC_RT_CONV0_LSB */
2906 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2907 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2908
2909 /* Bit definitions for GPADC_RT_CONV0_MSB */
2910 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2911 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2912
2913 /* Bit definitions for GPADC_AUTO_SELECT */
2914 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2915 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2916 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2917 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2918
2919 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2920 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2921 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2922
2923 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2924 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2925 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2926
2927 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2928 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2929 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2930
2931 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2932 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2933 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2934
2935 /* Bit definitions for GPADC_SW_SELECT */
2936 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2937 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2938 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2939 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2940 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2941 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2942
2943 /* Bit definitions for GPADC_SW_CONV0_LSB */
2944 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2945 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2946
2947 /* Bit definitions for GPADC_SW_CONV0_MSB */
2948 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2949 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2950
2951 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2952 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2953 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2954
2955 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2956 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2957 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2958 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2959 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2960
2961 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2962 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2963 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2964
2965 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2966 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2967 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2968 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2969 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2970
2971 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2972 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2973 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2974 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2975 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2976 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2977 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2978
2979 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2980 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2981 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2982 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2983 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2984
2985 /* Registers for function GPADC */
2986 #define PALMAS_GPADC_TRIM1 0x00
2987 #define PALMAS_GPADC_TRIM2 0x01
2988 #define PALMAS_GPADC_TRIM3 0x02
2989 #define PALMAS_GPADC_TRIM4 0x03
2990 #define PALMAS_GPADC_TRIM5 0x04
2991 #define PALMAS_GPADC_TRIM6 0x05
2992 #define PALMAS_GPADC_TRIM7 0x06
2993 #define PALMAS_GPADC_TRIM8 0x07
2994 #define PALMAS_GPADC_TRIM9 0x08
2995 #define PALMAS_GPADC_TRIM10 0x09
2996 #define PALMAS_GPADC_TRIM11 0x0A
2997 #define PALMAS_GPADC_TRIM12 0x0B
2998 #define PALMAS_GPADC_TRIM13 0x0C
2999 #define PALMAS_GPADC_TRIM14 0x0D
3000 #define PALMAS_GPADC_TRIM15 0x0E
3001 #define PALMAS_GPADC_TRIM16 0x0F
3002
3003 /* TPS659038 regen2_ctrl offset iss different from palmas */
3004 #define TPS659038_REGEN2_CTRL 0x12
3005
3006 /* TPS65917 Interrupt registers */
3007
3008 /* Registers for function INTERRUPT */
3009 #define TPS65917_INT1_STATUS 0x00
3010 #define TPS65917_INT1_MASK 0x01
3011 #define TPS65917_INT1_LINE_STATE 0x02
3012 #define TPS65917_INT2_STATUS 0x05
3013 #define TPS65917_INT2_MASK 0x06
3014 #define TPS65917_INT2_LINE_STATE 0x07
3015 #define TPS65917_INT3_STATUS 0x0A
3016 #define TPS65917_INT3_MASK 0x0B
3017 #define TPS65917_INT3_LINE_STATE 0x0C
3018 #define TPS65917_INT4_STATUS 0x0F
3019 #define TPS65917_INT4_MASK 0x10
3020 #define TPS65917_INT4_LINE_STATE 0x11
3021 #define TPS65917_INT4_EDGE_DETECT1 0x12
3022 #define TPS65917_INT4_EDGE_DETECT2 0x13
3023 #define TPS65917_INT_CTRL 0x14
3024
3025 /* Bit definitions for INT1_STATUS */
3026 #define TPS65917_INT1_STATUS_VSYS_MON 0x40
3027 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3028 #define TPS65917_INT1_STATUS_HOTDIE 0x20
3029 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3030 #define TPS65917_INT1_STATUS_PWRDOWN 0x10
3031 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3032 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3033 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3034 #define TPS65917_INT1_STATUS_PWRON 0x02
3035 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3036
3037 /* Bit definitions for INT1_MASK */
3038 #define TPS65917_INT1_MASK_VSYS_MON 0x40
3039 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3040 #define TPS65917_INT1_MASK_HOTDIE 0x20
3041 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3042 #define TPS65917_INT1_MASK_PWRDOWN 0x10
3043 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3044 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3045 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3046 #define TPS65917_INT1_MASK_PWRON 0x02
3047 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3048
3049 /* Bit definitions for INT1_LINE_STATE */
3050 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3051 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3052 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3053 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3054 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3055 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3056 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3057 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3058 #define TPS65917_INT1_LINE_STATE_PWRON 0x02
3059 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3060
3061 /* Bit definitions for INT2_STATUS */
3062 #define TPS65917_INT2_STATUS_SHORT 0x40
3063 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3064 #define TPS65917_INT2_STATUS_FSD 0x20
3065 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3066 #define TPS65917_INT2_STATUS_RESET_IN 0x10
3067 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3068 #define TPS65917_INT2_STATUS_WDT 0x04
3069 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3070 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3071 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3072
3073 /* Bit definitions for INT2_MASK */
3074 #define TPS65917_INT2_MASK_SHORT 0x40
3075 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3076 #define TPS65917_INT2_MASK_FSD 0x20
3077 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3078 #define TPS65917_INT2_MASK_RESET_IN 0x10
3079 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3080 #define TPS65917_INT2_MASK_WDT 0x04
3081 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3082 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3083 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3084
3085 /* Bit definitions for INT2_LINE_STATE */
3086 #define TPS65917_INT2_LINE_STATE_SHORT 0x40
3087 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3088 #define TPS65917_INT2_LINE_STATE_FSD 0x20
3089 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3090 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3091 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3092 #define TPS65917_INT2_LINE_STATE_WDT 0x04
3093 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3094 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3095 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3096
3097 /* Bit definitions for INT3_STATUS */
3098 #define TPS65917_INT3_STATUS_VBUS 0x80
3099 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3100 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3101 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3102 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3103 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3104 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3105 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3106
3107 /* Bit definitions for INT3_MASK */
3108 #define TPS65917_INT3_MASK_VBUS 0x80
3109 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3110 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3111 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3112 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3113 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3114 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3115 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3116
3117 /* Bit definitions for INT3_LINE_STATE */
3118 #define TPS65917_INT3_LINE_STATE_VBUS 0x80
3119 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3120 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3121 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3122 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3123 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3124 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3125 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3126
3127 /* Bit definitions for INT4_STATUS */
3128 #define TPS65917_INT4_STATUS_GPIO_6 0x40
3129 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3130 #define TPS65917_INT4_STATUS_GPIO_5 0x20
3131 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3132 #define TPS65917_INT4_STATUS_GPIO_4 0x10
3133 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3134 #define TPS65917_INT4_STATUS_GPIO_3 0x08
3135 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3136 #define TPS65917_INT4_STATUS_GPIO_2 0x04
3137 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3138 #define TPS65917_INT4_STATUS_GPIO_1 0x02
3139 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3140 #define TPS65917_INT4_STATUS_GPIO_0 0x01
3141 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3142
3143 /* Bit definitions for INT4_MASK */
3144 #define TPS65917_INT4_MASK_GPIO_6 0x40
3145 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3146 #define TPS65917_INT4_MASK_GPIO_5 0x20
3147 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3148 #define TPS65917_INT4_MASK_GPIO_4 0x10
3149 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3150 #define TPS65917_INT4_MASK_GPIO_3 0x08
3151 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3152 #define TPS65917_INT4_MASK_GPIO_2 0x04
3153 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3154 #define TPS65917_INT4_MASK_GPIO_1 0x02
3155 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3156 #define TPS65917_INT4_MASK_GPIO_0 0x01
3157 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3158
3159 /* Bit definitions for INT4_LINE_STATE */
3160 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3161 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3162 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3163 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3164 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3165 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3166 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3167 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3168 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3169 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3170 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3171 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3172 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3173 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3174
3175 /* Bit definitions for INT4_EDGE_DETECT1 */
3176 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3177 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3178 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3179 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3180 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3181 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3182 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3183 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3184 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3185 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3186 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3187 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3188 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3189 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3190 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3191 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3192
3193 /* Bit definitions for INT4_EDGE_DETECT2 */
3194 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3195 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3196 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3197 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3198 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3199 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3200 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3201 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3202 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3203 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3204 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3205 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3206
3207 /* Bit definitions for INT_CTRL */
3208 #define TPS65917_INT_CTRL_INT_PENDING 0x04
3209 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3210 #define TPS65917_INT_CTRL_INT_CLEAR 0x01
3211 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3212
3213 /* TPS65917 SMPS Registers */
3214
3215 /* Registers for function SMPS */
3216 #define TPS65917_SMPS1_CTRL 0x00
3217 #define TPS65917_SMPS1_FORCE 0x02
3218 #define TPS65917_SMPS1_VOLTAGE 0x03
3219 #define TPS65917_SMPS2_CTRL 0x04
3220 #define TPS65917_SMPS2_FORCE 0x06
3221 #define TPS65917_SMPS2_VOLTAGE 0x07
3222 #define TPS65917_SMPS3_CTRL 0x0C
3223 #define TPS65917_SMPS3_FORCE 0x0E
3224 #define TPS65917_SMPS3_VOLTAGE 0x0F
3225 #define TPS65917_SMPS4_CTRL 0x10
3226 #define TPS65917_SMPS4_VOLTAGE 0x13
3227 #define TPS65917_SMPS5_CTRL 0x18
3228 #define TPS65917_SMPS5_VOLTAGE 0x1B
3229 #define TPS65917_SMPS_CTRL 0x24
3230 #define TPS65917_SMPS_PD_CTRL 0x25
3231 #define TPS65917_SMPS_THERMAL_EN 0x27
3232 #define TPS65917_SMPS_THERMAL_STATUS 0x28
3233 #define TPS65917_SMPS_SHORT_STATUS 0x29
3234 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3235 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3236 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3237
3238 /* Bit definitions for SMPS1_CTRL */
3239 #define TPS65917_SMPS1_CTRL_WR_S 0x80
3240 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3241 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3242 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3243 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3244 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3245 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3246 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3247 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3248 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3249
3250 /* Bit definitions for SMPS1_FORCE */
3251 #define TPS65917_SMPS1_FORCE_CMD 0x80
3252 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3253 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3254 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3255
3256 /* Bit definitions for SMPS1_VOLTAGE */
3257 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3258 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3259 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3260 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3261
3262 /* Bit definitions for SMPS2_CTRL */
3263 #define TPS65917_SMPS2_CTRL_WR_S 0x80
3264 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3265 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3266 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3267 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3268 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3269 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3270 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3271 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3272 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3273
3274 /* Bit definitions for SMPS2_FORCE */
3275 #define TPS65917_SMPS2_FORCE_CMD 0x80
3276 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3277 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3278 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3279
3280 /* Bit definitions for SMPS2_VOLTAGE */
3281 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3282 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3283 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3284 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3285
3286 /* Bit definitions for SMPS3_CTRL */
3287 #define TPS65917_SMPS3_CTRL_WR_S 0x80
3288 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3289 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3290 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3291 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3292 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3293 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3294 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3295 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3296 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3297
3298 /* Bit definitions for SMPS3_FORCE */
3299 #define TPS65917_SMPS3_FORCE_CMD 0x80
3300 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3301 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3302 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3303
3304 /* Bit definitions for SMPS3_VOLTAGE */
3305 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3306 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3307 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3308 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3309
3310 /* Bit definitions for SMPS4_CTRL */
3311 #define TPS65917_SMPS4_CTRL_WR_S 0x80
3312 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3313 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3314 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3315 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3316 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3317 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3318 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3319 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3320 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3321
3322 /* Bit definitions for SMPS4_VOLTAGE */
3323 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3324 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3325 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3326 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3327
3328 /* Bit definitions for SMPS5_CTRL */
3329 #define TPS65917_SMPS5_CTRL_WR_S 0x80
3330 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3331 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3332 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3333 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3334 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3335 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3336 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3337 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3338 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3339
3340 /* Bit definitions for SMPS5_VOLTAGE */
3341 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3342 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3343 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3344 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3345
3346 /* Bit definitions for SMPS_CTRL */
3347 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3348 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3349 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3350 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3351
3352 /* Bit definitions for SMPS_PD_CTRL */
3353 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3354 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3355 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3356 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3357 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3358 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3359 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3360 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3361 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3362 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3363
3364 /* Bit definitions for SMPS_THERMAL_EN */
3365 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3366 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3367 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3368 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3369 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3370 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3371
3372 /* Bit definitions for SMPS_THERMAL_STATUS */
3373 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3374 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3375 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3376 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3377 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3378 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3379
3380 /* Bit definitions for SMPS_SHORT_STATUS */
3381 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3382 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3383 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3384 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3385 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3386 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3387 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3388 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3389 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3390 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3391
3392 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3393 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3394 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3395 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3396 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3397 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3398 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3399 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3400 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3401 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3402 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3403
3404 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
3405 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3406 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3407 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3408 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3409 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3410 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3411 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3412 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3413 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3414 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3415
3416 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
3417 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3418 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3419 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3420 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3421
3422 /* Bit definitions for SMPS_PLL_CTRL */
3423
3424 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3425 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3426 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3427 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3428
3429 /* Registers for function LDO */
3430 #define TPS65917_LDO1_CTRL 0x00
3431 #define TPS65917_LDO1_VOLTAGE 0x01
3432 #define TPS65917_LDO2_CTRL 0x02
3433 #define TPS65917_LDO2_VOLTAGE 0x03
3434 #define TPS65917_LDO3_CTRL 0x04
3435 #define TPS65917_LDO3_VOLTAGE 0x05
3436 #define TPS65917_LDO4_CTRL 0x0E
3437 #define TPS65917_LDO4_VOLTAGE 0x0F
3438 #define TPS65917_LDO5_CTRL 0x12
3439 #define TPS65917_LDO5_VOLTAGE 0x13
3440 #define TPS65917_LDO_PD_CTRL1 0x1B
3441 #define TPS65917_LDO_PD_CTRL2 0x1C
3442 #define TPS65917_LDO_SHORT_STATUS1 0x1D
3443 #define TPS65917_LDO_SHORT_STATUS2 0x1E
3444 #define TPS65917_LDO_PD_CTRL3 0x2D
3445 #define TPS65917_LDO_SHORT_STATUS3 0x2E
3446
3447 /* Bit definitions for LDO1_CTRL */
3448 #define TPS65917_LDO1_CTRL_WR_S 0x80
3449 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3450 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3451 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3452 #define TPS65917_LDO1_CTRL_STATUS 0x10
3453 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3454 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3455 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3456 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3457 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3458
3459 /* Bit definitions for LDO1_VOLTAGE */
3460 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3461 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3462
3463 /* Bit definitions for LDO2_CTRL */
3464 #define TPS65917_LDO2_CTRL_WR_S 0x80
3465 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3466 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3467 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3468 #define TPS65917_LDO2_CTRL_STATUS 0x10
3469 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3470 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3471 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3472 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3473 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3474
3475 /* Bit definitions for LDO2_VOLTAGE */
3476 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3477 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3478
3479 /* Bit definitions for LDO3_CTRL */
3480 #define TPS65917_LDO3_CTRL_WR_S 0x80
3481 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3482 #define TPS65917_LDO3_CTRL_STATUS 0x10
3483 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3484 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3485 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3486 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3487 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3488
3489 /* Bit definitions for LDO3_VOLTAGE */
3490 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3491 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3492
3493 /* Bit definitions for LDO4_CTRL */
3494 #define TPS65917_LDO4_CTRL_WR_S 0x80
3495 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3496 #define TPS65917_LDO4_CTRL_STATUS 0x10
3497 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3498 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3499 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3500 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3501 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3502
3503 /* Bit definitions for LDO4_VOLTAGE */
3504 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3505 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3506
3507 /* Bit definitions for LDO5_CTRL */
3508 #define TPS65917_LDO5_CTRL_WR_S 0x80
3509 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3510 #define TPS65917_LDO5_CTRL_STATUS 0x10
3511 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3512 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3513 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3514 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3515 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3516
3517 /* Bit definitions for LDO5_VOLTAGE */
3518 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3519 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3520
3521 /* Bit definitions for LDO_PD_CTRL1 */
3522 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3523 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3524 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3525 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3526 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3527 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3528
3529 /* Bit definitions for LDO_PD_CTRL2 */
3530 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3531 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3532 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3533 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3534
3535 /* Bit definitions for LDO_PD_CTRL3 */
3536 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3537 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3538
3539 /* Bit definitions for LDO_SHORT_STATUS1 */
3540 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3541 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3542 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3543 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3544 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3545 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3546
3547 /* Bit definitions for LDO_SHORT_STATUS2 */
3548 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3549 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3550 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3551 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3552
3553 /* Bit definitions for LDO_SHORT_STATUS2 */
3554 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3555 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3556
3557 /* Bit definitions for REGEN1_CTRL */
3558 #define TPS65917_REGEN1_CTRL_STATUS 0x10
3559 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3560 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3561 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3562 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3563 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3564
3565 /* Bit definitions for PLLEN_CTRL */
3566 #define TPS65917_PLLEN_CTRL_STATUS 0x10
3567 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3568 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3569 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3570 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3571 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3572
3573 /* Bit definitions for REGEN2_CTRL */
3574 #define TPS65917_REGEN2_CTRL_STATUS 0x10
3575 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3576 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3577 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3578 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3579 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3580
3581 /* Bit definitions for NSLEEP_RES_ASSIGN */
3582 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3583 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3584 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3585 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3586 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3587 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3588 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3589 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3590
3591 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
3592 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3593 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3594 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3595 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3596 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3597 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3598 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3599 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3600 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3601 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3602
3603 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3604 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3605 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3606 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3607 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3608 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3609 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3610
3611 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3612 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3613 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3614 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3615 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3616
3617 /* Bit definitions for ENABLE1_RES_ASSIGN */
3618 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3619 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3620 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3621 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3622 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3623 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3624 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3625 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3626
3627 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
3628 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3629 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3630 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3631 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3632 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3633 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3634 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3635 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3636 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3637 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3638
3639 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3640 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3641 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3642 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3643 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3644 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3645 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3646
3647 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3648 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3649 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3650 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3651 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3652
3653 /* Bit definitions for ENABLE2_RES_ASSIGN */
3654 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3655 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3656 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3657 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3658 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3659 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3660 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3661 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3662
3663 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
3664 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3665 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3666 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3667 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3668 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3669 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3670 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3671 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3672 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3673 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3674
3675 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3676 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3677 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3678 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3679 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3680 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3681 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3682
3683 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3684 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3685 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3686 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3687 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3688
3689 /* Bit definitions for REGEN3_CTRL */
3690 #define TPS65917_REGEN3_CTRL_STATUS 0x10
3691 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3692 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3693 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3694 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3695 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3696
3697 /* Registers for function RESOURCE */
3698 #define TPS65917_REGEN1_CTRL 0x2
3699 #define TPS65917_PLLEN_CTRL 0x3
3700 #define TPS65917_NSLEEP_RES_ASSIGN 0x6
3701 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3702 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3703 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3704 #define TPS65917_ENABLE1_RES_ASSIGN 0xA
3705 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3706 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3707 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3708 #define TPS65917_ENABLE2_RES_ASSIGN 0xE
3709 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3710 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3711 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3712 #define TPS65917_REGEN2_CTRL 0x12
3713 #define TPS65917_REGEN3_CTRL 0x13
3714
palmas_read(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int * val)3715 static inline int palmas_read(struct palmas *palmas, unsigned int base,
3716 unsigned int reg, unsigned int *val)
3717 {
3718 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3719 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3720
3721 return regmap_read(palmas->regmap[slave_id], addr, val);
3722 }
3723
palmas_write(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int value)3724 static inline int palmas_write(struct palmas *palmas, unsigned int base,
3725 unsigned int reg, unsigned int value)
3726 {
3727 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3728 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3729
3730 return regmap_write(palmas->regmap[slave_id], addr, value);
3731 }
3732
palmas_bulk_write(struct palmas * palmas,unsigned int base,unsigned int reg,const void * val,size_t val_count)3733 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3734 unsigned int reg, const void *val, size_t val_count)
3735 {
3736 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3737 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3738
3739 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3740 val, val_count);
3741 }
3742
palmas_bulk_read(struct palmas * palmas,unsigned int base,unsigned int reg,void * val,size_t val_count)3743 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3744 unsigned int reg, void *val, size_t val_count)
3745 {
3746 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3747 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3748
3749 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3750 val, val_count);
3751 }
3752
palmas_update_bits(struct palmas * palmas,unsigned int base,unsigned int reg,unsigned int mask,unsigned int val)3753 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3754 unsigned int reg, unsigned int mask, unsigned int val)
3755 {
3756 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3757 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3758
3759 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3760 }
3761
palmas_irq_get_virq(struct palmas * palmas,int irq)3762 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3763 {
3764 return regmap_irq_get_virq(palmas->irq_data, irq);
3765 }
3766
3767
3768 int palmas_ext_control_req_config(struct palmas *palmas,
3769 enum palmas_external_requestor_id ext_control_req_id,
3770 int ext_ctrl, bool enable);
3771
3772 #endif /* __LINUX_MFD_PALMAS_H */
3773