1 /*
2 * CPU idle driver for Tegra CPUs
3 *
4 * Copyright (c) 2010-2012, NVIDIA Corporation.
5 * Copyright (c) 2011 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 * Gary King <gking@nvidia.com>
8 *
9 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22 #include <linux/clk/tegra.h>
23 #include <linux/tick.h>
24 #include <linux/cpuidle.h>
25 #include <linux/cpu_pm.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28
29 #include <asm/cpuidle.h>
30 #include <asm/smp_plat.h>
31 #include <asm/suspend.h>
32
33 #include "flowctrl.h"
34 #include "iomap.h"
35 #include "irq.h"
36 #include "pm.h"
37 #include "reset.h"
38 #include "sleep.h"
39
40 #ifdef CONFIG_PM_SLEEP
41 static bool abort_flag;
42 static atomic_t abort_barrier;
43 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
44 struct cpuidle_driver *drv,
45 int index);
46 #define TEGRA20_MAX_STATES 2
47 #else
48 #define TEGRA20_MAX_STATES 1
49 #endif
50
51 static struct cpuidle_driver tegra_idle_driver = {
52 .name = "tegra_idle",
53 .owner = THIS_MODULE,
54 .states = {
55 ARM_CPUIDLE_WFI_STATE_PWR(600),
56 #ifdef CONFIG_PM_SLEEP
57 {
58 .enter = tegra20_idle_lp2_coupled,
59 .exit_latency = 5000,
60 .target_residency = 10000,
61 .power_usage = 0,
62 .flags = CPUIDLE_FLAG_COUPLED,
63 .name = "powered-down",
64 .desc = "CPU power gated",
65 },
66 #endif
67 },
68 .state_count = TEGRA20_MAX_STATES,
69 .safe_state_index = 0,
70 };
71
72 #ifdef CONFIG_PM_SLEEP
73 #ifdef CONFIG_SMP
tegra20_reset_sleeping_cpu_1(void)74 static int tegra20_reset_sleeping_cpu_1(void)
75 {
76 int ret = 0;
77
78 tegra_pen_lock();
79
80 if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
81 tegra20_cpu_shutdown(1);
82 else
83 ret = -EINVAL;
84
85 tegra_pen_unlock();
86
87 return ret;
88 }
89
tegra20_wake_cpu1_from_reset(void)90 static void tegra20_wake_cpu1_from_reset(void)
91 {
92 tegra_pen_lock();
93
94 tegra20_cpu_clear_resettable();
95
96 /* enable cpu clock on cpu */
97 tegra_enable_cpu_clock(1);
98
99 /* take the CPU out of reset */
100 tegra_cpu_out_of_reset(1);
101
102 /* unhalt the cpu */
103 flowctrl_write_cpu_halt(1, 0);
104
105 tegra_pen_unlock();
106 }
107
tegra20_reset_cpu_1(void)108 static int tegra20_reset_cpu_1(void)
109 {
110 if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
111 return 0;
112
113 tegra20_wake_cpu1_from_reset();
114 return -EBUSY;
115 }
116 #else
tegra20_wake_cpu1_from_reset(void)117 static inline void tegra20_wake_cpu1_from_reset(void)
118 {
119 }
120
tegra20_reset_cpu_1(void)121 static inline int tegra20_reset_cpu_1(void)
122 {
123 return 0;
124 }
125 #endif
126
tegra20_cpu_cluster_power_down(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)127 static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
128 struct cpuidle_driver *drv,
129 int index)
130 {
131 while (tegra20_cpu_is_resettable_soon())
132 cpu_relax();
133
134 if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
135 return false;
136
137 tick_broadcast_enter();
138
139 tegra_idle_lp2_last();
140
141 tick_broadcast_exit();
142
143 if (cpu_online(1))
144 tegra20_wake_cpu1_from_reset();
145
146 return true;
147 }
148
149 #ifdef CONFIG_SMP
tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)150 static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
151 struct cpuidle_driver *drv,
152 int index)
153 {
154 tick_broadcast_enter();
155
156 cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
157
158 tegra20_cpu_clear_resettable();
159
160 tick_broadcast_exit();
161
162 return true;
163 }
164 #else
tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)165 static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
166 struct cpuidle_driver *drv,
167 int index)
168 {
169 return true;
170 }
171 #endif
172
tegra20_idle_lp2_coupled(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)173 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
174 struct cpuidle_driver *drv,
175 int index)
176 {
177 bool entered_lp2 = false;
178
179 if (tegra_pending_sgi())
180 ACCESS_ONCE(abort_flag) = true;
181
182 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
183
184 if (abort_flag) {
185 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
186 abort_flag = false; /* clean flag for next coming */
187 return -EINTR;
188 }
189
190 local_fiq_disable();
191
192 tegra_set_cpu_in_lp2();
193 cpu_pm_enter();
194
195 if (dev->cpu == 0)
196 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
197 else
198 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
199
200 cpu_pm_exit();
201 tegra_clear_cpu_in_lp2();
202
203 local_fiq_enable();
204
205 smp_rmb();
206
207 return entered_lp2 ? index : 0;
208 }
209 #endif
210
211 /*
212 * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
213 * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
214 * this, simply disable LP2 if the PCI driver and DT node are both enabled.
215 */
tegra20_cpuidle_pcie_irqs_in_use(void)216 void tegra20_cpuidle_pcie_irqs_in_use(void)
217 {
218 pr_info_once(
219 "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
220 tegra_idle_driver.states[1].disabled = true;
221 }
222
tegra20_cpuidle_init(void)223 int __init tegra20_cpuidle_init(void)
224 {
225 return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
226 }
227