1 /*
2  *  Intel SST Haswell/Broadwell IPC Support
3  *
4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License version
8  * 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16 
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/device.h>
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/platform_device.h>
29 #include <linux/kthread.h>
30 #include <linux/firmware.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/debugfs.h>
33 #include <linux/pm_runtime.h>
34 #include <sound/asound.h>
35 
36 #include "sst-haswell-ipc.h"
37 #include "../common/sst-dsp.h"
38 #include "../common/sst-dsp-priv.h"
39 #include "../common/sst-ipc.h"
40 
41 /* Global Message - Generic */
42 #define IPC_GLB_TYPE_SHIFT	24
43 #define IPC_GLB_TYPE_MASK	(0x1f << IPC_GLB_TYPE_SHIFT)
44 #define IPC_GLB_TYPE(x)		(x << IPC_GLB_TYPE_SHIFT)
45 
46 /* Global Message - Reply */
47 #define IPC_GLB_REPLY_SHIFT	0
48 #define IPC_GLB_REPLY_MASK	(0x1f << IPC_GLB_REPLY_SHIFT)
49 #define IPC_GLB_REPLY_TYPE(x)	(x << IPC_GLB_REPLY_TYPE_SHIFT)
50 
51 /* Stream Message - Generic */
52 #define IPC_STR_TYPE_SHIFT	20
53 #define IPC_STR_TYPE_MASK	(0xf << IPC_STR_TYPE_SHIFT)
54 #define IPC_STR_TYPE(x)		(x << IPC_STR_TYPE_SHIFT)
55 #define IPC_STR_ID_SHIFT	16
56 #define IPC_STR_ID_MASK		(0xf << IPC_STR_ID_SHIFT)
57 #define IPC_STR_ID(x)		(x << IPC_STR_ID_SHIFT)
58 
59 /* Stream Message - Reply */
60 #define IPC_STR_REPLY_SHIFT	0
61 #define IPC_STR_REPLY_MASK	(0x1f << IPC_STR_REPLY_SHIFT)
62 
63 /* Stream Stage Message - Generic */
64 #define IPC_STG_TYPE_SHIFT	12
65 #define IPC_STG_TYPE_MASK	(0xf << IPC_STG_TYPE_SHIFT)
66 #define IPC_STG_TYPE(x)		(x << IPC_STG_TYPE_SHIFT)
67 #define IPC_STG_ID_SHIFT	10
68 #define IPC_STG_ID_MASK		(0x3 << IPC_STG_ID_SHIFT)
69 #define IPC_STG_ID(x)		(x << IPC_STG_ID_SHIFT)
70 
71 /* Stream Stage Message - Reply */
72 #define IPC_STG_REPLY_SHIFT	0
73 #define IPC_STG_REPLY_MASK	(0x1f << IPC_STG_REPLY_SHIFT)
74 
75 /* Debug Log Message - Generic */
76 #define IPC_LOG_OP_SHIFT	20
77 #define IPC_LOG_OP_MASK		(0xf << IPC_LOG_OP_SHIFT)
78 #define IPC_LOG_OP_TYPE(x)	(x << IPC_LOG_OP_SHIFT)
79 #define IPC_LOG_ID_SHIFT	16
80 #define IPC_LOG_ID_MASK		(0xf << IPC_LOG_ID_SHIFT)
81 #define IPC_LOG_ID(x)		(x << IPC_LOG_ID_SHIFT)
82 
83 /* Module Message */
84 #define IPC_MODULE_OPERATION_SHIFT	20
85 #define IPC_MODULE_OPERATION_MASK	(0xf << IPC_MODULE_OPERATION_SHIFT)
86 #define IPC_MODULE_OPERATION(x)	(x << IPC_MODULE_OPERATION_SHIFT)
87 
88 #define IPC_MODULE_ID_SHIFT	16
89 #define IPC_MODULE_ID_MASK	(0xf << IPC_MODULE_ID_SHIFT)
90 #define IPC_MODULE_ID(x)	(x << IPC_MODULE_ID_SHIFT)
91 
92 /* IPC message timeout (msecs) */
93 #define IPC_TIMEOUT_MSECS	300
94 #define IPC_BOOT_MSECS		200
95 #define IPC_MSG_WAIT		0
96 #define IPC_MSG_NOWAIT		1
97 
98 /* Firmware Ready Message */
99 #define IPC_FW_READY		(0x1 << 29)
100 #define IPC_STATUS_MASK		(0x3 << 30)
101 
102 #define IPC_EMPTY_LIST_SIZE	8
103 #define IPC_MAX_STREAMS		4
104 
105 /* Mailbox */
106 #define IPC_MAX_MAILBOX_BYTES	256
107 
108 #define INVALID_STREAM_HW_ID	0xffffffff
109 
110 /* Global Message - Types and Replies */
111 enum ipc_glb_type {
112 	IPC_GLB_GET_FW_VERSION = 0,		/* Retrieves firmware version */
113 	IPC_GLB_PERFORMANCE_MONITOR = 1,	/* Performance monitoring actions */
114 	IPC_GLB_ALLOCATE_STREAM = 3,		/* Request to allocate new stream */
115 	IPC_GLB_FREE_STREAM = 4,		/* Request to free stream */
116 	IPC_GLB_GET_FW_CAPABILITIES = 5,	/* Retrieves firmware capabilities */
117 	IPC_GLB_STREAM_MESSAGE = 6,		/* Message directed to stream or its stages */
118 	/* Request to store firmware context during D0->D3 transition */
119 	IPC_GLB_REQUEST_DUMP = 7,
120 	/* Request to restore firmware context during D3->D0 transition */
121 	IPC_GLB_RESTORE_CONTEXT = 8,
122 	IPC_GLB_GET_DEVICE_FORMATS = 9,		/* Set device format */
123 	IPC_GLB_SET_DEVICE_FORMATS = 10,	/* Get device format */
124 	IPC_GLB_SHORT_REPLY = 11,
125 	IPC_GLB_ENTER_DX_STATE = 12,
126 	IPC_GLB_GET_MIXER_STREAM_INFO = 13,	/* Request mixer stream params */
127 	IPC_GLB_DEBUG_LOG_MESSAGE = 14,		/* Message to or from the debug logger. */
128 	IPC_GLB_MODULE_OPERATION = 15,		/* Message to loadable fw module */
129 	IPC_GLB_REQUEST_TRANSFER = 16, 		/* < Request Transfer for host */
130 	IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17,	/* Maximum message number */
131 };
132 
133 enum ipc_glb_reply {
134 	IPC_GLB_REPLY_SUCCESS = 0,		/* The operation was successful. */
135 	IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1,	/* Invalid parameter was passed. */
136 	IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2,	/* Uknown message type was resceived. */
137 	IPC_GLB_REPLY_OUT_OF_RESOURCES = 3,	/* No resources to satisfy the request. */
138 	IPC_GLB_REPLY_BUSY = 4,			/* The system or resource is busy. */
139 	IPC_GLB_REPLY_PENDING = 5,		/* The action was scheduled for processing.  */
140 	IPC_GLB_REPLY_FAILURE = 6,		/* Critical error happened. */
141 	IPC_GLB_REPLY_INVALID_REQUEST = 7,	/* Request can not be completed. */
142 	IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8,	/* Processing stage was uninitialized. */
143 	IPC_GLB_REPLY_NOT_FOUND = 9,		/* Required resource can not be found. */
144 	IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10,	/* Source was not started. */
145 };
146 
147 enum ipc_module_operation {
148 	IPC_MODULE_NOTIFICATION = 0,
149 	IPC_MODULE_ENABLE = 1,
150 	IPC_MODULE_DISABLE = 2,
151 	IPC_MODULE_GET_PARAMETER = 3,
152 	IPC_MODULE_SET_PARAMETER = 4,
153 	IPC_MODULE_GET_INFO = 5,
154 	IPC_MODULE_MAX_MESSAGE
155 };
156 
157 /* Stream Message - Types */
158 enum ipc_str_operation {
159 	IPC_STR_RESET = 0,
160 	IPC_STR_PAUSE = 1,
161 	IPC_STR_RESUME = 2,
162 	IPC_STR_STAGE_MESSAGE = 3,
163 	IPC_STR_NOTIFICATION = 4,
164 	IPC_STR_MAX_MESSAGE
165 };
166 
167 /* Stream Stage Message Types */
168 enum ipc_stg_operation {
169 	IPC_STG_GET_VOLUME = 0,
170 	IPC_STG_SET_VOLUME,
171 	IPC_STG_SET_WRITE_POSITION,
172 	IPC_STG_SET_FX_ENABLE,
173 	IPC_STG_SET_FX_DISABLE,
174 	IPC_STG_SET_FX_GET_PARAM,
175 	IPC_STG_SET_FX_SET_PARAM,
176 	IPC_STG_SET_FX_GET_INFO,
177 	IPC_STG_MUTE_LOOPBACK,
178 	IPC_STG_MAX_MESSAGE
179 };
180 
181 /* Stream Stage Message Types For Notification*/
182 enum ipc_stg_operation_notify {
183 	IPC_POSITION_CHANGED = 0,
184 	IPC_STG_GLITCH,
185 	IPC_STG_MAX_NOTIFY
186 };
187 
188 enum ipc_glitch_type {
189 	IPC_GLITCH_UNDERRUN = 1,
190 	IPC_GLITCH_DECODER_ERROR,
191 	IPC_GLITCH_DOUBLED_WRITE_POS,
192 	IPC_GLITCH_MAX
193 };
194 
195 /* Debug Control */
196 enum ipc_debug_operation {
197 	IPC_DEBUG_ENABLE_LOG = 0,
198 	IPC_DEBUG_DISABLE_LOG = 1,
199 	IPC_DEBUG_REQUEST_LOG_DUMP = 2,
200 	IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
201 	IPC_DEBUG_MAX_DEBUG_LOG
202 };
203 
204 /* Firmware Ready */
205 struct sst_hsw_ipc_fw_ready {
206 	u32 inbox_offset;
207 	u32 outbox_offset;
208 	u32 inbox_size;
209 	u32 outbox_size;
210 	u32 fw_info_size;
211 	u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
212 } __attribute__((packed));
213 
214 struct sst_hsw_stream;
215 struct sst_hsw;
216 
217 /* Stream infomation */
218 struct sst_hsw_stream {
219 	/* configuration */
220 	struct sst_hsw_ipc_stream_alloc_req request;
221 	struct sst_hsw_ipc_stream_alloc_reply reply;
222 	struct sst_hsw_ipc_stream_free_req free_req;
223 
224 	/* Mixer info */
225 	u32 mute_volume[SST_HSW_NO_CHANNELS];
226 	u32 mute[SST_HSW_NO_CHANNELS];
227 
228 	/* runtime info */
229 	struct sst_hsw *hsw;
230 	int host_id;
231 	bool commited;
232 	bool running;
233 
234 	/* Notification work */
235 	struct work_struct notify_work;
236 	u32 header;
237 
238 	/* Position info from DSP */
239 	struct sst_hsw_ipc_stream_set_position wpos;
240 	struct sst_hsw_ipc_stream_get_position rpos;
241 	struct sst_hsw_ipc_stream_glitch_position glitch;
242 
243 	/* Volume info */
244 	struct sst_hsw_ipc_volume_req vol_req;
245 
246 	/* driver callback */
247 	u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
248 	void *pdata;
249 
250 	/* record the fw read position when playback */
251 	snd_pcm_uframes_t old_position;
252 	bool play_silence;
253 	struct list_head node;
254 };
255 
256 /* FW log ring information */
257 struct sst_hsw_log_stream {
258 	dma_addr_t dma_addr;
259 	unsigned char *dma_area;
260 	unsigned char *ring_descr;
261 	int pages;
262 	int size;
263 
264 	/* Notification work */
265 	struct work_struct notify_work;
266 	wait_queue_head_t readers_wait_q;
267 	struct mutex rw_mutex;
268 
269 	u32 last_pos;
270 	u32 curr_pos;
271 	u32 reader_pos;
272 
273 	/* fw log config */
274 	u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
275 
276 	struct sst_hsw *hsw;
277 };
278 
279 /* SST Haswell IPC data */
280 struct sst_hsw {
281 	struct device *dev;
282 	struct sst_dsp *dsp;
283 	struct platform_device *pdev_pcm;
284 
285 	/* FW config */
286 	struct sst_hsw_ipc_fw_ready fw_ready;
287 	struct sst_hsw_ipc_fw_version version;
288 	bool fw_done;
289 	struct sst_fw *sst_fw;
290 
291 	/* stream */
292 	struct list_head stream_list;
293 
294 	/* global mixer */
295 	struct sst_hsw_ipc_stream_info_reply mixer_info;
296 	enum sst_hsw_volume_curve curve_type;
297 	u32 curve_duration;
298 	u32 mute[SST_HSW_NO_CHANNELS];
299 	u32 mute_volume[SST_HSW_NO_CHANNELS];
300 
301 	/* DX */
302 	struct sst_hsw_ipc_dx_reply dx;
303 	void *dx_context;
304 	dma_addr_t dx_context_paddr;
305 	enum sst_hsw_device_id dx_dev;
306 	enum sst_hsw_device_mclk dx_mclk;
307 	enum sst_hsw_device_mode dx_mode;
308 	u32 dx_clock_divider;
309 
310 	/* boot */
311 	wait_queue_head_t boot_wait;
312 	bool boot_complete;
313 	bool shutdown;
314 
315 	/* IPC messaging */
316 	struct sst_generic_ipc ipc;
317 
318 	/* FW log stream */
319 	struct sst_hsw_log_stream log_stream;
320 
321 	/* flags bit field to track module state when resume from RTD3,
322 	 * each bit represent state (enabled/disabled) of single module */
323 	u32 enabled_modules_rtd3;
324 
325 	/* buffer to store parameter lines */
326 	u32 param_idx_w;	/* write index */
327 	u32 param_idx_r;	/* read index */
328 	u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
329 };
330 
331 #define CREATE_TRACE_POINTS
332 #include <trace/events/hswadsp.h>
333 
msg_get_global_type(u32 msg)334 static inline u32 msg_get_global_type(u32 msg)
335 {
336 	return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
337 }
338 
msg_get_global_reply(u32 msg)339 static inline u32 msg_get_global_reply(u32 msg)
340 {
341 	return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
342 }
343 
msg_get_stream_type(u32 msg)344 static inline u32 msg_get_stream_type(u32 msg)
345 {
346 	return (msg & IPC_STR_TYPE_MASK) >>  IPC_STR_TYPE_SHIFT;
347 }
348 
msg_get_stage_type(u32 msg)349 static inline u32 msg_get_stage_type(u32 msg)
350 {
351 	return (msg & IPC_STG_TYPE_MASK) >>  IPC_STG_TYPE_SHIFT;
352 }
353 
msg_get_stream_id(u32 msg)354 static inline u32 msg_get_stream_id(u32 msg)
355 {
356 	return (msg & IPC_STR_ID_MASK) >>  IPC_STR_ID_SHIFT;
357 }
358 
msg_get_notify_reason(u32 msg)359 static inline u32 msg_get_notify_reason(u32 msg)
360 {
361 	return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
362 }
363 
msg_get_module_operation(u32 msg)364 static inline u32 msg_get_module_operation(u32 msg)
365 {
366 	return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
367 }
368 
msg_get_module_id(u32 msg)369 static inline u32 msg_get_module_id(u32 msg)
370 {
371 	return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
372 }
373 
create_channel_map(enum sst_hsw_channel_config config)374 u32 create_channel_map(enum sst_hsw_channel_config config)
375 {
376 	switch (config) {
377 	case SST_HSW_CHANNEL_CONFIG_MONO:
378 		return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
379 	case SST_HSW_CHANNEL_CONFIG_STEREO:
380 		return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
381 			| (SST_HSW_CHANNEL_RIGHT << 4));
382 	case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
383 		return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
384 			| (SST_HSW_CHANNEL_RIGHT << 4)
385 			| (SST_HSW_CHANNEL_LFE << 8 ));
386 	case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
387 		return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
388 			| (SST_HSW_CHANNEL_CENTER << 4)
389 			| (SST_HSW_CHANNEL_RIGHT << 8));
390 	case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
391 		return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
392 			| (SST_HSW_CHANNEL_CENTER << 4)
393 			| (SST_HSW_CHANNEL_RIGHT << 8)
394 			| (SST_HSW_CHANNEL_LFE << 12));
395 	case SST_HSW_CHANNEL_CONFIG_QUATRO:
396 		return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
397 			| (SST_HSW_CHANNEL_RIGHT << 4)
398 			| (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
399 			| (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
400 	case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
401 		return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
402 			| (SST_HSW_CHANNEL_CENTER << 4)
403 			| (SST_HSW_CHANNEL_RIGHT << 8)
404 			| (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
405 	case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
406 		return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
407 			| (SST_HSW_CHANNEL_CENTER << 4)
408 			| (SST_HSW_CHANNEL_RIGHT << 8)
409 			| (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
410 			| (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
411 	case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
412 		return (0xFF000000 | SST_HSW_CHANNEL_CENTER
413 			| (SST_HSW_CHANNEL_LEFT << 4)
414 			| (SST_HSW_CHANNEL_RIGHT << 8)
415 			| (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
416 			| (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
417 			| (SST_HSW_CHANNEL_LFE << 20));
418 	case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
419 		return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
420 			| (SST_HSW_CHANNEL_LEFT << 4));
421 	default:
422 		return 0xFFFFFFFF;
423 	}
424 }
425 
get_stream_by_id(struct sst_hsw * hsw,int stream_id)426 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
427 	int stream_id)
428 {
429 	struct sst_hsw_stream *stream;
430 
431 	list_for_each_entry(stream, &hsw->stream_list, node) {
432 		if (stream->reply.stream_hw_id == stream_id)
433 			return stream;
434 	}
435 
436 	return NULL;
437 }
438 
hsw_fw_ready(struct sst_hsw * hsw,u32 header)439 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
440 {
441 	struct sst_hsw_ipc_fw_ready fw_ready;
442 	u32 offset;
443 	u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
444 	char *tmp[5], *pinfo;
445 	int i = 0;
446 
447 	offset = (header & 0x1FFFFFFF) << 3;
448 
449 	dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
450 		header, offset);
451 
452 	/* copy data from the DSP FW ready offset */
453 	sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
454 
455 	sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
456 		fw_ready.inbox_size, fw_ready.outbox_offset,
457 		fw_ready.outbox_size);
458 
459 	hsw->boot_complete = true;
460 	wake_up(&hsw->boot_wait);
461 
462 	dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
463 		fw_ready.inbox_offset, fw_ready.inbox_size);
464 	dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
465 		fw_ready.outbox_offset, fw_ready.outbox_size);
466 	if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
467 		fw_ready.fw_info[fw_ready.fw_info_size] = 0;
468 		dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
469 
470 		/* log the FW version info got from the mailbox here. */
471 		memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
472 		pinfo = &fw_info[0];
473 		for (i = 0; i < ARRAY_SIZE(tmp); i++)
474 			tmp[i] = strsep(&pinfo, " ");
475 		dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
476 			"version: %s.%s, build %s, source commit id: %s\n",
477 			tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
478 	}
479 }
480 
hsw_notification_work(struct work_struct * work)481 static void hsw_notification_work(struct work_struct *work)
482 {
483 	struct sst_hsw_stream *stream = container_of(work,
484 			struct sst_hsw_stream, notify_work);
485 	struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
486 	struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
487 	struct sst_hsw *hsw = stream->hsw;
488 	u32 reason;
489 
490 	reason = msg_get_notify_reason(stream->header);
491 
492 	switch (reason) {
493 	case IPC_STG_GLITCH:
494 		trace_ipc_notification("DSP stream under/overrun",
495 			stream->reply.stream_hw_id);
496 		sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
497 
498 		dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
499 			glitch->glitch_type, glitch->present_pos,
500 			glitch->write_pos);
501 		break;
502 
503 	case IPC_POSITION_CHANGED:
504 		trace_ipc_notification("DSP stream position changed for",
505 			stream->reply.stream_hw_id);
506 		sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
507 
508 		if (stream->notify_position)
509 			stream->notify_position(stream, stream->pdata);
510 
511 		break;
512 	default:
513 		dev_err(hsw->dev, "error: unknown notification 0x%x\n",
514 			stream->header);
515 		break;
516 	}
517 
518 	/* tell DSP that notification has been handled */
519 	sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
520 		SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
521 
522 	/* unmask busy interrupt */
523 	sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
524 }
525 
hsw_stream_update(struct sst_hsw * hsw,struct ipc_message * msg)526 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
527 {
528 	struct sst_hsw_stream *stream;
529 	u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
530 	u32 stream_id = msg_get_stream_id(header);
531 	u32 stream_msg = msg_get_stream_type(header);
532 
533 	stream = get_stream_by_id(hsw, stream_id);
534 	if (stream == NULL)
535 		return;
536 
537 	switch (stream_msg) {
538 	case IPC_STR_STAGE_MESSAGE:
539 	case IPC_STR_NOTIFICATION:
540 		break;
541 	case IPC_STR_RESET:
542 		trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
543 		break;
544 	case IPC_STR_PAUSE:
545 		stream->running = false;
546 		trace_ipc_notification("stream paused",
547 			stream->reply.stream_hw_id);
548 		break;
549 	case IPC_STR_RESUME:
550 		stream->running = true;
551 		trace_ipc_notification("stream running",
552 			stream->reply.stream_hw_id);
553 		break;
554 	}
555 }
556 
hsw_process_reply(struct sst_hsw * hsw,u32 header)557 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
558 {
559 	struct ipc_message *msg;
560 	u32 reply = msg_get_global_reply(header);
561 
562 	trace_ipc_reply("processing -->", header);
563 
564 	msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
565 	if (msg == NULL) {
566 		trace_ipc_error("error: can't find message header", header);
567 		return -EIO;
568 	}
569 
570 	/* first process the header */
571 	switch (reply) {
572 	case IPC_GLB_REPLY_PENDING:
573 		trace_ipc_pending_reply("received", header);
574 		msg->pending = true;
575 		hsw->ipc.pending = true;
576 		return 1;
577 	case IPC_GLB_REPLY_SUCCESS:
578 		if (msg->pending) {
579 			trace_ipc_pending_reply("completed", header);
580 			sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
581 				msg->rx_size);
582 			hsw->ipc.pending = false;
583 		} else {
584 			/* copy data from the DSP */
585 			sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
586 				msg->rx_size);
587 		}
588 		break;
589 	/* these will be rare - but useful for debug */
590 	case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
591 		trace_ipc_error("error: unknown message type", header);
592 		msg->errno = -EBADMSG;
593 		break;
594 	case IPC_GLB_REPLY_OUT_OF_RESOURCES:
595 		trace_ipc_error("error: out of resources", header);
596 		msg->errno = -ENOMEM;
597 		break;
598 	case IPC_GLB_REPLY_BUSY:
599 		trace_ipc_error("error: reply busy", header);
600 		msg->errno = -EBUSY;
601 		break;
602 	case IPC_GLB_REPLY_FAILURE:
603 		trace_ipc_error("error: reply failure", header);
604 		msg->errno = -EINVAL;
605 		break;
606 	case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
607 		trace_ipc_error("error: stage uninitialized", header);
608 		msg->errno = -EINVAL;
609 		break;
610 	case IPC_GLB_REPLY_NOT_FOUND:
611 		trace_ipc_error("error: reply not found", header);
612 		msg->errno = -EINVAL;
613 		break;
614 	case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
615 		trace_ipc_error("error: source not started", header);
616 		msg->errno = -EINVAL;
617 		break;
618 	case IPC_GLB_REPLY_INVALID_REQUEST:
619 		trace_ipc_error("error: invalid request", header);
620 		msg->errno = -EINVAL;
621 		break;
622 	case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
623 		trace_ipc_error("error: invalid parameter", header);
624 		msg->errno = -EINVAL;
625 		break;
626 	default:
627 		trace_ipc_error("error: unknown reply", header);
628 		msg->errno = -EINVAL;
629 		break;
630 	}
631 
632 	/* update any stream states */
633 	if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
634 		hsw_stream_update(hsw, msg);
635 
636 	/* wake up and return the error if we have waiters on this message ? */
637 	list_del(&msg->list);
638 	sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
639 
640 	return 1;
641 }
642 
hsw_module_message(struct sst_hsw * hsw,u32 header)643 static int hsw_module_message(struct sst_hsw *hsw, u32 header)
644 {
645 	u32 operation, module_id;
646 	int handled = 0;
647 
648 	operation = msg_get_module_operation(header);
649 	module_id = msg_get_module_id(header);
650 	dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
651 			header);
652 	dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
653 			operation, module_id);
654 
655 	switch (operation) {
656 	case IPC_MODULE_NOTIFICATION:
657 		dev_dbg(hsw->dev, "module notification received");
658 		handled = 1;
659 		break;
660 	default:
661 		handled = hsw_process_reply(hsw, header);
662 		break;
663 	}
664 
665 	return handled;
666 }
667 
hsw_stream_message(struct sst_hsw * hsw,u32 header)668 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
669 {
670 	u32 stream_msg, stream_id, stage_type;
671 	struct sst_hsw_stream *stream;
672 	int handled = 0;
673 
674 	stream_msg = msg_get_stream_type(header);
675 	stream_id = msg_get_stream_id(header);
676 	stage_type = msg_get_stage_type(header);
677 
678 	stream = get_stream_by_id(hsw, stream_id);
679 	if (stream == NULL)
680 		return handled;
681 
682 	stream->header = header;
683 
684 	switch (stream_msg) {
685 	case IPC_STR_STAGE_MESSAGE:
686 		dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
687 			header);
688 		break;
689 	case IPC_STR_NOTIFICATION:
690 		schedule_work(&stream->notify_work);
691 		break;
692 	default:
693 		/* handle pending message complete request */
694 		handled = hsw_process_reply(hsw, header);
695 		break;
696 	}
697 
698 	return handled;
699 }
700 
hsw_log_message(struct sst_hsw * hsw,u32 header)701 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
702 {
703 	u32 operation = (header & IPC_LOG_OP_MASK) >>  IPC_LOG_OP_SHIFT;
704 	struct sst_hsw_log_stream *stream = &hsw->log_stream;
705 	int ret = 1;
706 
707 	if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
708 		dev_err(hsw->dev,
709 			"error: log msg not implemented 0x%8.8x\n", header);
710 		return 0;
711 	}
712 
713 	mutex_lock(&stream->rw_mutex);
714 	stream->last_pos = stream->curr_pos;
715 	sst_dsp_inbox_read(
716 		hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
717 	mutex_unlock(&stream->rw_mutex);
718 
719 	schedule_work(&stream->notify_work);
720 
721 	return ret;
722 }
723 
hsw_process_notification(struct sst_hsw * hsw)724 static int hsw_process_notification(struct sst_hsw *hsw)
725 {
726 	struct sst_dsp *sst = hsw->dsp;
727 	u32 type, header;
728 	int handled = 1;
729 
730 	header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
731 	type = msg_get_global_type(header);
732 
733 	trace_ipc_request("processing -->", header);
734 
735 	/* FW Ready is a special case */
736 	if (!hsw->boot_complete && header & IPC_FW_READY) {
737 		hsw_fw_ready(hsw, header);
738 		return handled;
739 	}
740 
741 	switch (type) {
742 	case IPC_GLB_GET_FW_VERSION:
743 	case IPC_GLB_ALLOCATE_STREAM:
744 	case IPC_GLB_FREE_STREAM:
745 	case IPC_GLB_GET_FW_CAPABILITIES:
746 	case IPC_GLB_REQUEST_DUMP:
747 	case IPC_GLB_GET_DEVICE_FORMATS:
748 	case IPC_GLB_SET_DEVICE_FORMATS:
749 	case IPC_GLB_ENTER_DX_STATE:
750 	case IPC_GLB_GET_MIXER_STREAM_INFO:
751 	case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
752 	case IPC_GLB_RESTORE_CONTEXT:
753 	case IPC_GLB_SHORT_REPLY:
754 		dev_err(hsw->dev, "error: message type %d header 0x%x\n",
755 			type, header);
756 		break;
757 	case IPC_GLB_STREAM_MESSAGE:
758 		handled = hsw_stream_message(hsw, header);
759 		break;
760 	case IPC_GLB_DEBUG_LOG_MESSAGE:
761 		handled = hsw_log_message(hsw, header);
762 		break;
763 	case IPC_GLB_MODULE_OPERATION:
764 		handled = hsw_module_message(hsw, header);
765 		break;
766 	default:
767 		dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
768 			type, header);
769 		break;
770 	}
771 
772 	return handled;
773 }
774 
hsw_irq_thread(int irq,void * context)775 static irqreturn_t hsw_irq_thread(int irq, void *context)
776 {
777 	struct sst_dsp *sst = (struct sst_dsp *) context;
778 	struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
779 	struct sst_generic_ipc *ipc = &hsw->ipc;
780 	u32 ipcx, ipcd;
781 	int handled;
782 	unsigned long flags;
783 
784 	spin_lock_irqsave(&sst->spinlock, flags);
785 
786 	ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
787 	ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
788 
789 	/* reply message from DSP */
790 	if (ipcx & SST_IPCX_DONE) {
791 
792 		/* Handle Immediate reply from DSP Core */
793 		handled = hsw_process_reply(hsw, ipcx);
794 
795 		if (handled > 0) {
796 			/* clear DONE bit - tell DSP we have completed */
797 			sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
798 				SST_IPCX_DONE, 0);
799 
800 			/* unmask Done interrupt */
801 			sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
802 				SST_IMRX_DONE, 0);
803 		}
804 	}
805 
806 	/* new message from DSP */
807 	if (ipcd & SST_IPCD_BUSY) {
808 
809 		/* Handle Notification and Delayed reply from DSP Core */
810 		handled = hsw_process_notification(hsw);
811 
812 		/* clear BUSY bit and set DONE bit - accept new messages */
813 		if (handled > 0) {
814 			sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
815 				SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
816 
817 			/* unmask busy interrupt */
818 			sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
819 				SST_IMRX_BUSY, 0);
820 		}
821 	}
822 
823 	spin_unlock_irqrestore(&sst->spinlock, flags);
824 
825 	/* continue to send any remaining messages... */
826 	queue_kthread_work(&ipc->kworker, &ipc->kwork);
827 
828 	return IRQ_HANDLED;
829 }
830 
sst_hsw_fw_get_version(struct sst_hsw * hsw,struct sst_hsw_ipc_fw_version * version)831 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
832 	struct sst_hsw_ipc_fw_version *version)
833 {
834 	int ret;
835 
836 	ret = sst_ipc_tx_message_wait(&hsw->ipc,
837 		IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
838 		NULL, 0, version, sizeof(*version));
839 	if (ret < 0)
840 		dev_err(hsw->dev, "error: get version failed\n");
841 
842 	return ret;
843 }
844 
845 /* Mixer Controls */
sst_hsw_stream_get_volume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 stage_id,u32 channel,u32 * volume)846 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
847 	u32 stage_id, u32 channel, u32 *volume)
848 {
849 	if (channel > 1)
850 		return -EINVAL;
851 
852 	sst_dsp_read(hsw->dsp, volume,
853 		stream->reply.volume_register_address[channel],
854 		sizeof(*volume));
855 
856 	return 0;
857 }
858 
859 /* stream volume */
sst_hsw_stream_set_volume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 stage_id,u32 channel,u32 volume)860 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
861 	struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
862 {
863 	struct sst_hsw_ipc_volume_req *req;
864 	u32 header;
865 	int ret;
866 
867 	trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
868 
869 	if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
870 		return -EINVAL;
871 
872 	header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
873 		IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
874 	header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
875 	header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
876 	header |= (stage_id << IPC_STG_ID_SHIFT);
877 
878 	req = &stream->vol_req;
879 	req->target_volume = volume;
880 
881 	/* set both at same time ? */
882 	if (channel == SST_HSW_CHANNELS_ALL) {
883 		if (hsw->mute[0] && hsw->mute[1]) {
884 			hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
885 			return 0;
886 		} else if (hsw->mute[0])
887 			req->channel = 1;
888 		else if (hsw->mute[1])
889 			req->channel = 0;
890 		else
891 			req->channel = SST_HSW_CHANNELS_ALL;
892 	} else {
893 		/* set only 1 channel */
894 		if (hsw->mute[channel]) {
895 			hsw->mute_volume[channel] = volume;
896 			return 0;
897 		}
898 		req->channel = channel;
899 	}
900 
901 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
902 		sizeof(*req), NULL, 0);
903 	if (ret < 0) {
904 		dev_err(hsw->dev, "error: set stream volume failed\n");
905 		return ret;
906 	}
907 
908 	return 0;
909 }
910 
sst_hsw_mixer_get_volume(struct sst_hsw * hsw,u32 stage_id,u32 channel,u32 * volume)911 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
912 	u32 *volume)
913 {
914 	if (channel > 1)
915 		return -EINVAL;
916 
917 	sst_dsp_read(hsw->dsp, volume,
918 		hsw->mixer_info.volume_register_address[channel],
919 		sizeof(*volume));
920 
921 	return 0;
922 }
923 
924 /* global mixer volume */
sst_hsw_mixer_set_volume(struct sst_hsw * hsw,u32 stage_id,u32 channel,u32 volume)925 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
926 	u32 volume)
927 {
928 	struct sst_hsw_ipc_volume_req req;
929 	u32 header;
930 	int ret;
931 
932 	trace_ipc_request("set mixer volume", volume);
933 
934 	if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
935 		return -EINVAL;
936 
937 	/* set both at same time ? */
938 	if (channel == SST_HSW_CHANNELS_ALL) {
939 		if (hsw->mute[0] && hsw->mute[1]) {
940 			hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
941 			return 0;
942 		} else if (hsw->mute[0])
943 			req.channel = 1;
944 		else if (hsw->mute[1])
945 			req.channel = 0;
946 		else
947 			req.channel = SST_HSW_CHANNELS_ALL;
948 	} else {
949 		/* set only 1 channel */
950 		if (hsw->mute[channel]) {
951 			hsw->mute_volume[channel] = volume;
952 			return 0;
953 		}
954 		req.channel = channel;
955 	}
956 
957 	header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
958 		IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
959 	header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
960 	header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
961 	header |= (stage_id << IPC_STG_ID_SHIFT);
962 
963 	req.curve_duration = hsw->curve_duration;
964 	req.curve_type = hsw->curve_type;
965 	req.target_volume = volume;
966 
967 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
968 		sizeof(req), NULL, 0);
969 	if (ret < 0) {
970 		dev_err(hsw->dev, "error: set mixer volume failed\n");
971 		return ret;
972 	}
973 
974 	return 0;
975 }
976 
977 /* Stream API */
sst_hsw_stream_new(struct sst_hsw * hsw,int id,u32 (* notify_position)(struct sst_hsw_stream * stream,void * data),void * data)978 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
979 	u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
980 	void *data)
981 {
982 	struct sst_hsw_stream *stream;
983 	struct sst_dsp *sst = hsw->dsp;
984 	unsigned long flags;
985 
986 	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
987 	if (stream == NULL)
988 		return NULL;
989 
990 	spin_lock_irqsave(&sst->spinlock, flags);
991 	stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
992 	list_add(&stream->node, &hsw->stream_list);
993 	stream->notify_position = notify_position;
994 	stream->pdata = data;
995 	stream->hsw = hsw;
996 	stream->host_id = id;
997 
998 	/* work to process notification messages */
999 	INIT_WORK(&stream->notify_work, hsw_notification_work);
1000 	spin_unlock_irqrestore(&sst->spinlock, flags);
1001 
1002 	return stream;
1003 }
1004 
sst_hsw_stream_free(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1005 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1006 {
1007 	u32 header;
1008 	int ret = 0;
1009 	struct sst_dsp *sst = hsw->dsp;
1010 	unsigned long flags;
1011 
1012 	if (!stream) {
1013 		dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1014 		return 0;
1015 	}
1016 
1017 	/* dont free DSP streams that are not commited */
1018 	if (!stream->commited)
1019 		goto out;
1020 
1021 	trace_ipc_request("stream free", stream->host_id);
1022 
1023 	stream->free_req.stream_id = stream->reply.stream_hw_id;
1024 	header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1025 
1026 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
1027 		sizeof(stream->free_req), NULL, 0);
1028 	if (ret < 0) {
1029 		dev_err(hsw->dev, "error: free stream %d failed\n",
1030 			stream->free_req.stream_id);
1031 		return -EAGAIN;
1032 	}
1033 
1034 	trace_hsw_stream_free_req(stream, &stream->free_req);
1035 
1036 out:
1037 	cancel_work_sync(&stream->notify_work);
1038 	spin_lock_irqsave(&sst->spinlock, flags);
1039 	list_del(&stream->node);
1040 	kfree(stream);
1041 	spin_unlock_irqrestore(&sst->spinlock, flags);
1042 
1043 	return ret;
1044 }
1045 
sst_hsw_stream_set_bits(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_bitdepth bits)1046 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1047 	struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1048 {
1049 	if (stream->commited) {
1050 		dev_err(hsw->dev, "error: stream committed for set bits\n");
1051 		return -EINVAL;
1052 	}
1053 
1054 	stream->request.format.bitdepth = bits;
1055 	return 0;
1056 }
1057 
sst_hsw_stream_set_channels(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int channels)1058 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1059 	struct sst_hsw_stream *stream, int channels)
1060 {
1061 	if (stream->commited) {
1062 		dev_err(hsw->dev, "error: stream committed for set channels\n");
1063 		return -EINVAL;
1064 	}
1065 
1066 	stream->request.format.ch_num = channels;
1067 	return 0;
1068 }
1069 
sst_hsw_stream_set_rate(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int rate)1070 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1071 	struct sst_hsw_stream *stream, int rate)
1072 {
1073 	if (stream->commited) {
1074 		dev_err(hsw->dev, "error: stream committed for set rate\n");
1075 		return -EINVAL;
1076 	}
1077 
1078 	stream->request.format.frequency = rate;
1079 	return 0;
1080 }
1081 
sst_hsw_stream_set_map_config(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 map,enum sst_hsw_channel_config config)1082 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1083 	struct sst_hsw_stream *stream, u32 map,
1084 	enum sst_hsw_channel_config config)
1085 {
1086 	if (stream->commited) {
1087 		dev_err(hsw->dev, "error: stream committed for set map\n");
1088 		return -EINVAL;
1089 	}
1090 
1091 	stream->request.format.map = map;
1092 	stream->request.format.config = config;
1093 	return 0;
1094 }
1095 
sst_hsw_stream_set_style(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_interleaving style)1096 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1097 	struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1098 {
1099 	if (stream->commited) {
1100 		dev_err(hsw->dev, "error: stream committed for set style\n");
1101 		return -EINVAL;
1102 	}
1103 
1104 	stream->request.format.style = style;
1105 	return 0;
1106 }
1107 
sst_hsw_stream_set_valid(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 bits)1108 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1109 	struct sst_hsw_stream *stream, u32 bits)
1110 {
1111 	if (stream->commited) {
1112 		dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1113 		return -EINVAL;
1114 	}
1115 
1116 	stream->request.format.valid_bit = bits;
1117 	return 0;
1118 }
1119 
1120 /* Stream Configuration */
sst_hsw_stream_format(struct sst_hsw * hsw,struct sst_hsw_stream * stream,enum sst_hsw_stream_path_id path_id,enum sst_hsw_stream_type stream_type,enum sst_hsw_stream_format format_id)1121 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1122 	enum sst_hsw_stream_path_id path_id,
1123 	enum sst_hsw_stream_type stream_type,
1124 	enum sst_hsw_stream_format format_id)
1125 {
1126 	if (stream->commited) {
1127 		dev_err(hsw->dev, "error: stream committed for set format\n");
1128 		return -EINVAL;
1129 	}
1130 
1131 	stream->request.path_id = path_id;
1132 	stream->request.stream_type = stream_type;
1133 	stream->request.format_id = format_id;
1134 
1135 	trace_hsw_stream_alloc_request(stream, &stream->request);
1136 
1137 	return 0;
1138 }
1139 
sst_hsw_stream_buffer(struct sst_hsw * hsw,struct sst_hsw_stream * stream,u32 ring_pt_address,u32 num_pages,u32 ring_size,u32 ring_offset,u32 ring_first_pfn)1140 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1141 	u32 ring_pt_address, u32 num_pages,
1142 	u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1143 {
1144 	if (stream->commited) {
1145 		dev_err(hsw->dev, "error: stream committed for buffer\n");
1146 		return -EINVAL;
1147 	}
1148 
1149 	stream->request.ringinfo.ring_pt_address = ring_pt_address;
1150 	stream->request.ringinfo.num_pages = num_pages;
1151 	stream->request.ringinfo.ring_size = ring_size;
1152 	stream->request.ringinfo.ring_offset = ring_offset;
1153 	stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1154 
1155 	trace_hsw_stream_buffer(stream);
1156 
1157 	return 0;
1158 }
1159 
sst_hsw_stream_set_module_info(struct sst_hsw * hsw,struct sst_hsw_stream * stream,struct sst_module_runtime * runtime)1160 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1161 	struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1162 {
1163 	struct sst_hsw_module_map *map = &stream->request.map;
1164 	struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1165 	struct sst_module *module = runtime->module;
1166 
1167 	if (stream->commited) {
1168 		dev_err(hsw->dev, "error: stream committed for set module\n");
1169 		return -EINVAL;
1170 	}
1171 
1172 	/* only support initial module atm */
1173 	map->module_entries_count = 1;
1174 	map->module_entries[0].module_id = module->id;
1175 	map->module_entries[0].entry_point = module->entry;
1176 
1177 	stream->request.persistent_mem.offset =
1178 		sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1179 	stream->request.persistent_mem.size = module->persistent_size;
1180 
1181 	stream->request.scratch_mem.offset =
1182 		sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1183 	stream->request.scratch_mem.size = dsp->scratch_size;
1184 
1185 	dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1186 		runtime->id);
1187 	dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1188 		stream->request.persistent_mem.offset,
1189 		stream->request.persistent_mem.size);
1190 	dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1191 		stream->request.scratch_mem.offset,
1192 		stream->request.scratch_mem.size);
1193 
1194 	return 0;
1195 }
1196 
sst_hsw_stream_commit(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1197 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1198 {
1199 	struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1200 	struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1201 	u32 header;
1202 	int ret;
1203 
1204 	if (!stream) {
1205 		dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1206 		return 0;
1207 	}
1208 
1209 	if (stream->commited) {
1210 		dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1211 		return 0;
1212 	}
1213 
1214 	trace_ipc_request("stream alloc", stream->host_id);
1215 
1216 	header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1217 
1218 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1219 		sizeof(*str_req), reply, sizeof(*reply));
1220 	if (ret < 0) {
1221 		dev_err(hsw->dev, "error: stream commit failed\n");
1222 		return ret;
1223 	}
1224 
1225 	stream->commited = 1;
1226 	trace_hsw_stream_alloc_reply(stream);
1227 
1228 	return 0;
1229 }
1230 
sst_hsw_stream_get_old_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1231 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1232 	struct sst_hsw_stream *stream)
1233 {
1234 	return stream->old_position;
1235 }
1236 
sst_hsw_stream_set_old_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream,snd_pcm_uframes_t val)1237 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1238 	struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1239 {
1240 	stream->old_position = val;
1241 }
1242 
sst_hsw_stream_get_silence_start(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1243 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1244 	struct sst_hsw_stream *stream)
1245 {
1246 	return stream->play_silence;
1247 }
1248 
sst_hsw_stream_set_silence_start(struct sst_hsw * hsw,struct sst_hsw_stream * stream,bool val)1249 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1250 	struct sst_hsw_stream *stream, bool val)
1251 {
1252 	stream->play_silence = val;
1253 }
1254 
1255 /* Stream Information - these calls could be inline but we want the IPC
1256  ABI to be opaque to client PCM drivers to cope with any future ABI changes */
sst_hsw_mixer_get_info(struct sst_hsw * hsw)1257 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1258 {
1259 	struct sst_hsw_ipc_stream_info_reply *reply;
1260 	u32 header;
1261 	int ret;
1262 
1263 	reply = &hsw->mixer_info;
1264 	header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1265 
1266 	trace_ipc_request("get global mixer info", 0);
1267 
1268 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1269 		reply, sizeof(*reply));
1270 	if (ret < 0) {
1271 		dev_err(hsw->dev, "error: get stream info failed\n");
1272 		return ret;
1273 	}
1274 
1275 	trace_hsw_mixer_info_reply(reply);
1276 
1277 	return 0;
1278 }
1279 
1280 /* Send stream command */
sst_hsw_stream_operations(struct sst_hsw * hsw,int type,int stream_id,int wait)1281 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1282 	int stream_id, int wait)
1283 {
1284 	u32 header;
1285 
1286 	header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1287 	header |= (stream_id << IPC_STR_ID_SHIFT);
1288 
1289 	if (wait)
1290 		return sst_ipc_tx_message_wait(&hsw->ipc, header,
1291 			NULL, 0, NULL, 0);
1292 	else
1293 		return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
1294 }
1295 
1296 /* Stream ALSA trigger operations */
sst_hsw_stream_pause(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int wait)1297 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1298 	int wait)
1299 {
1300 	int ret;
1301 
1302 	if (!stream) {
1303 		dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1304 		return 0;
1305 	}
1306 
1307 	trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1308 
1309 	ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1310 		stream->reply.stream_hw_id, wait);
1311 	if (ret < 0)
1312 		dev_err(hsw->dev, "error: failed to pause stream %d\n",
1313 			stream->reply.stream_hw_id);
1314 
1315 	return ret;
1316 }
1317 
sst_hsw_stream_resume(struct sst_hsw * hsw,struct sst_hsw_stream * stream,int wait)1318 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1319 	int wait)
1320 {
1321 	int ret;
1322 
1323 	if (!stream) {
1324 		dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1325 		return 0;
1326 	}
1327 
1328 	trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1329 
1330 	ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1331 		stream->reply.stream_hw_id, wait);
1332 	if (ret < 0)
1333 		dev_err(hsw->dev, "error: failed to resume stream %d\n",
1334 			stream->reply.stream_hw_id);
1335 
1336 	return ret;
1337 }
1338 
sst_hsw_stream_reset(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1339 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1340 {
1341 	int ret, tries = 10;
1342 
1343 	if (!stream) {
1344 		dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1345 		return 0;
1346 	}
1347 
1348 	/* dont reset streams that are not commited */
1349 	if (!stream->commited)
1350 		return 0;
1351 
1352 	/* wait for pause to complete before we reset the stream */
1353 	while (stream->running && tries--)
1354 		msleep(1);
1355 	if (!tries) {
1356 		dev_err(hsw->dev, "error: reset stream %d still running\n",
1357 			stream->reply.stream_hw_id);
1358 		return -EINVAL;
1359 	}
1360 
1361 	trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1362 
1363 	ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1364 		stream->reply.stream_hw_id, 1);
1365 	if (ret < 0)
1366 		dev_err(hsw->dev, "error: failed to reset stream %d\n",
1367 			stream->reply.stream_hw_id);
1368 	return ret;
1369 }
1370 
1371 /* Stream pointer positions */
sst_hsw_get_dsp_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1372 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1373 	struct sst_hsw_stream *stream)
1374 {
1375 	u32 rpos;
1376 
1377 	sst_dsp_read(hsw->dsp, &rpos,
1378 		stream->reply.read_position_register_address, sizeof(rpos));
1379 
1380 	return rpos;
1381 }
1382 
1383 /* Stream presentation (monotonic) positions */
sst_hsw_get_dsp_presentation_position(struct sst_hsw * hsw,struct sst_hsw_stream * stream)1384 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1385 	struct sst_hsw_stream *stream)
1386 {
1387 	u64 ppos;
1388 
1389 	sst_dsp_read(hsw->dsp, &ppos,
1390 		stream->reply.presentation_position_register_address,
1391 		sizeof(ppos));
1392 
1393 	return ppos;
1394 }
1395 
1396 /* physical BE config */
sst_hsw_device_set_config(struct sst_hsw * hsw,enum sst_hsw_device_id dev,enum sst_hsw_device_mclk mclk,enum sst_hsw_device_mode mode,u32 clock_divider)1397 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1398 	enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1399 	enum sst_hsw_device_mode mode, u32 clock_divider)
1400 {
1401 	struct sst_hsw_ipc_device_config_req config;
1402 	u32 header;
1403 	int ret;
1404 
1405 	trace_ipc_request("set device config", dev);
1406 
1407 	hsw->dx_dev = config.ssp_interface = dev;
1408 	hsw->dx_mclk = config.clock_frequency = mclk;
1409 	hsw->dx_mode = config.mode = mode;
1410 	hsw->dx_clock_divider = config.clock_divider = clock_divider;
1411 	if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1412 		config.channels = 4;
1413 	else
1414 		config.channels = 2;
1415 
1416 	trace_hsw_device_config_req(&config);
1417 
1418 	header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1419 
1420 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1421 		sizeof(config), NULL, 0);
1422 	if (ret < 0)
1423 		dev_err(hsw->dev, "error: set device formats failed\n");
1424 
1425 	return ret;
1426 }
1427 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1428 
1429 /* DX Config */
sst_hsw_dx_set_state(struct sst_hsw * hsw,enum sst_hsw_dx_state state,struct sst_hsw_ipc_dx_reply * dx)1430 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1431 	enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1432 {
1433 	u32 header, state_;
1434 	int ret, item;
1435 
1436 	header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1437 	state_ = state;
1438 
1439 	trace_ipc_request("PM enter Dx state", state);
1440 
1441 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1442 		sizeof(state_), dx, sizeof(*dx));
1443 	if (ret < 0) {
1444 		dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1445 		return ret;
1446 	}
1447 
1448 	for (item = 0; item < dx->entries_no; item++) {
1449 		dev_dbg(hsw->dev,
1450 			"Item[%d] offset[%x] - size[%x] - source[%x]\n",
1451 			item, dx->mem_info[item].offset,
1452 			dx->mem_info[item].size,
1453 			dx->mem_info[item].source);
1454 	}
1455 	dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1456 		dx->entries_no, state);
1457 
1458 	return ret;
1459 }
1460 
sst_hsw_runtime_module_create(struct sst_hsw * hsw,int mod_id,int offset)1461 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1462 	int mod_id, int offset)
1463 {
1464 	struct sst_dsp *dsp = hsw->dsp;
1465 	struct sst_module *module;
1466 	struct sst_module_runtime *runtime;
1467 	int err;
1468 
1469 	module = sst_module_get_from_id(dsp, mod_id);
1470 	if (module == NULL) {
1471 		dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1472 			mod_id);
1473 		return NULL;
1474 	}
1475 
1476 	runtime = sst_module_runtime_new(module, mod_id, NULL);
1477 	if (runtime == NULL) {
1478 		dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1479 			mod_id);
1480 		return NULL;
1481 	}
1482 
1483 	err = sst_module_runtime_alloc_blocks(runtime, offset);
1484 	if (err < 0) {
1485 		dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1486 			mod_id);
1487 		sst_module_runtime_free(runtime);
1488 		return NULL;
1489 	}
1490 
1491 	dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1492 		mod_id);
1493 	return runtime;
1494 }
1495 
sst_hsw_runtime_module_free(struct sst_module_runtime * runtime)1496 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1497 {
1498 	sst_module_runtime_free_blocks(runtime);
1499 	sst_module_runtime_free(runtime);
1500 }
1501 
1502 #ifdef CONFIG_PM
sst_hsw_dx_state_dump(struct sst_hsw * hsw)1503 static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1504 {
1505 	struct sst_dsp *sst = hsw->dsp;
1506 	u32 item, offset, size;
1507 	int ret = 0;
1508 
1509 	trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1510 
1511 	if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1512 		dev_err(hsw->dev,
1513 			"error: number of FW context regions greater than %d\n",
1514 			SST_HSW_MAX_DX_REGIONS);
1515 		memset(&hsw->dx, 0, sizeof(hsw->dx));
1516 		return -EINVAL;
1517 	}
1518 
1519 	ret = sst_dsp_dma_get_channel(sst, 0);
1520 	if (ret < 0) {
1521 		dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1522 		return ret;
1523 	}
1524 
1525 	/* set on-demond mode on engine 0 channel 3 */
1526 	sst_dsp_shim_update_bits(sst, SST_HMDC,
1527 			SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1528 			SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1529 
1530 	for (item = 0; item < hsw->dx.entries_no; item++) {
1531 		if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1532 			&& hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1533 			&& hsw->dx.mem_info[item].offset <
1534 			DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1535 
1536 			offset = hsw->dx.mem_info[item].offset
1537 					- DSP_DRAM_ADDR_OFFSET;
1538 			size = (hsw->dx.mem_info[item].size + 3) & (~3);
1539 
1540 			ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1541 				sst->addr.lpe_base + offset, size);
1542 			if (ret < 0) {
1543 				dev_err(hsw->dev,
1544 					"error: FW context dump failed\n");
1545 				memset(&hsw->dx, 0, sizeof(hsw->dx));
1546 				goto out;
1547 			}
1548 		}
1549 	}
1550 
1551 out:
1552 	sst_dsp_dma_put_channel(sst);
1553 	return ret;
1554 }
1555 
sst_hsw_dx_state_restore(struct sst_hsw * hsw)1556 static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1557 {
1558 	struct sst_dsp *sst = hsw->dsp;
1559 	u32 item, offset, size;
1560 	int ret;
1561 
1562 	for (item = 0; item < hsw->dx.entries_no; item++) {
1563 		if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1564 			&& hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1565 			&& hsw->dx.mem_info[item].offset <
1566 			DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1567 
1568 			offset = hsw->dx.mem_info[item].offset
1569 					- DSP_DRAM_ADDR_OFFSET;
1570 			size = (hsw->dx.mem_info[item].size + 3) & (~3);
1571 
1572 			ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1573 				hsw->dx_context_paddr + offset, size);
1574 			if (ret < 0) {
1575 				dev_err(hsw->dev,
1576 					"error: FW context restore failed\n");
1577 				return ret;
1578 			}
1579 		}
1580 	}
1581 
1582 	return 0;
1583 }
1584 
sst_hsw_dsp_load(struct sst_hsw * hsw)1585 int sst_hsw_dsp_load(struct sst_hsw *hsw)
1586 {
1587 	struct sst_dsp *dsp = hsw->dsp;
1588 	struct sst_fw *sst_fw, *t;
1589 	int ret;
1590 
1591 	dev_dbg(hsw->dev, "loading audio DSP....");
1592 
1593 	ret = sst_dsp_wake(dsp);
1594 	if (ret < 0) {
1595 		dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1596 		return -ENODEV;
1597 	}
1598 
1599 	ret = sst_dsp_dma_get_channel(dsp, 0);
1600 	if (ret < 0) {
1601 		dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1602 		return ret;
1603 	}
1604 
1605 	list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1606 		ret = sst_fw_reload(sst_fw);
1607 		if (ret < 0) {
1608 			dev_err(hsw->dev, "error: SST FW reload failed\n");
1609 			sst_dsp_dma_put_channel(dsp);
1610 			return -ENOMEM;
1611 		}
1612 	}
1613 	ret = sst_block_alloc_scratch(hsw->dsp);
1614 	if (ret < 0)
1615 		return -EINVAL;
1616 
1617 	sst_dsp_dma_put_channel(dsp);
1618 	return 0;
1619 }
1620 
sst_hsw_dsp_restore(struct sst_hsw * hsw)1621 static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1622 {
1623 	struct sst_dsp *dsp = hsw->dsp;
1624 	int ret;
1625 
1626 	dev_dbg(hsw->dev, "restoring audio DSP....");
1627 
1628 	ret = sst_dsp_dma_get_channel(dsp, 0);
1629 	if (ret < 0) {
1630 		dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1631 		return ret;
1632 	}
1633 
1634 	ret = sst_hsw_dx_state_restore(hsw);
1635 	if (ret < 0) {
1636 		dev_err(hsw->dev, "error: SST FW context restore failed\n");
1637 		sst_dsp_dma_put_channel(dsp);
1638 		return -ENOMEM;
1639 	}
1640 	sst_dsp_dma_put_channel(dsp);
1641 
1642 	/* wait for DSP boot completion */
1643 	sst_dsp_boot(dsp);
1644 
1645 	return ret;
1646 }
1647 
sst_hsw_dsp_runtime_suspend(struct sst_hsw * hsw)1648 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1649 {
1650 	int ret;
1651 
1652 	dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1653 
1654 	ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1655 	if (ret < 0)
1656 		return ret;
1657 
1658 	sst_dsp_stall(hsw->dsp);
1659 
1660 	ret = sst_hsw_dx_state_dump(hsw);
1661 	if (ret < 0)
1662 		return ret;
1663 
1664 	sst_ipc_drop_all(&hsw->ipc);
1665 
1666 	return 0;
1667 }
1668 
sst_hsw_dsp_runtime_sleep(struct sst_hsw * hsw)1669 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1670 {
1671 	struct sst_fw *sst_fw, *t;
1672 	struct sst_dsp *dsp = hsw->dsp;
1673 
1674 	list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1675 		sst_fw_unload(sst_fw);
1676 	}
1677 	sst_block_free_scratch(dsp);
1678 
1679 	hsw->boot_complete = false;
1680 
1681 	sst_dsp_sleep(dsp);
1682 
1683 	return 0;
1684 }
1685 
sst_hsw_dsp_runtime_resume(struct sst_hsw * hsw)1686 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1687 {
1688 	struct device *dev = hsw->dev;
1689 	int ret;
1690 
1691 	dev_dbg(dev, "audio dsp runtime resume\n");
1692 
1693 	if (hsw->boot_complete)
1694 		return 1; /* tell caller no action is required */
1695 
1696 	ret = sst_hsw_dsp_restore(hsw);
1697 	if (ret < 0)
1698 		dev_err(dev, "error: audio DSP boot failure\n");
1699 
1700 	sst_hsw_init_module_state(hsw);
1701 
1702 	ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1703 		msecs_to_jiffies(IPC_BOOT_MSECS));
1704 	if (ret == 0) {
1705 		dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1706 			sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1707 			sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1708 		return -EIO;
1709 	}
1710 
1711 	/* Set ADSP SSP port settings - sadly the FW does not store SSP port
1712 	   settings as part of the PM context. */
1713 	ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1714 					hsw->dx_mode, hsw->dx_clock_divider);
1715 	if (ret < 0)
1716 		dev_err(dev, "error: SSP re-initialization failed\n");
1717 
1718 	return ret;
1719 }
1720 #endif
1721 
sst_hsw_get_dsp(struct sst_hsw * hsw)1722 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1723 {
1724 	return hsw->dsp;
1725 }
1726 
sst_hsw_init_module_state(struct sst_hsw * hsw)1727 void sst_hsw_init_module_state(struct sst_hsw *hsw)
1728 {
1729 	struct sst_module *module;
1730 	enum sst_hsw_module_id id;
1731 
1732 	/* the base fw contains several modules */
1733 	for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1734 		module = sst_module_get_from_id(hsw->dsp, id);
1735 		if (module) {
1736 			/* module waves is active only after being enabled */
1737 			if (id == SST_HSW_MODULE_WAVES)
1738 				module->state = SST_MODULE_STATE_INITIALIZED;
1739 			else
1740 				module->state = SST_MODULE_STATE_ACTIVE;
1741 		}
1742 	}
1743 }
1744 
sst_hsw_is_module_loaded(struct sst_hsw * hsw,u32 module_id)1745 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1746 {
1747 	struct sst_module *module;
1748 
1749 	module = sst_module_get_from_id(hsw->dsp, module_id);
1750 	if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1751 		return false;
1752 	else
1753 		return true;
1754 }
1755 
sst_hsw_is_module_active(struct sst_hsw * hsw,u32 module_id)1756 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1757 {
1758 	struct sst_module *module;
1759 
1760 	module = sst_module_get_from_id(hsw->dsp, module_id);
1761 	if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1762 		return true;
1763 	else
1764 		return false;
1765 }
1766 
sst_hsw_set_module_enabled_rtd3(struct sst_hsw * hsw,u32 module_id)1767 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1768 {
1769 	hsw->enabled_modules_rtd3 |= (1 << module_id);
1770 }
1771 
sst_hsw_set_module_disabled_rtd3(struct sst_hsw * hsw,u32 module_id)1772 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1773 {
1774 	hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1775 }
1776 
sst_hsw_is_module_enabled_rtd3(struct sst_hsw * hsw,u32 module_id)1777 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1778 {
1779 	return hsw->enabled_modules_rtd3 & (1 << module_id);
1780 }
1781 
sst_hsw_reset_param_buf(struct sst_hsw * hsw)1782 void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1783 {
1784 	hsw->param_idx_w = 0;
1785 	hsw->param_idx_r = 0;
1786 	memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1787 }
1788 
sst_hsw_store_param_line(struct sst_hsw * hsw,u8 * buf)1789 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1790 {
1791 	/* save line to the first available position of param buffer */
1792 	if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1793 		dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1794 		return -EPERM;
1795 	}
1796 	memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1797 	hsw->param_idx_w++;
1798 	return 0;
1799 }
1800 
sst_hsw_load_param_line(struct sst_hsw * hsw,u8 * buf)1801 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1802 {
1803 	u8 id = 0;
1804 
1805 	/* read the first matching line from param buffer */
1806 	while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1807 		id = hsw->param_buf[hsw->param_idx_r][0];
1808 		hsw->param_idx_r++;
1809 		if (buf[0] == id) {
1810 			memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1811 				WAVES_PARAM_COUNT);
1812 			break;
1813 		}
1814 	}
1815 	if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1816 		dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1817 		hsw->param_idx_r = 0;
1818 		return 0;
1819 	}
1820 	return 0;
1821 }
1822 
sst_hsw_launch_param_buf(struct sst_hsw * hsw)1823 int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1824 {
1825 	int ret, idx;
1826 
1827 	if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1828 		dev_dbg(hsw->dev, "module waves is not active\n");
1829 		return 0;
1830 	}
1831 
1832 	/* put all param lines to DSP through ipc */
1833 	for (idx = 0; idx < hsw->param_idx_w; idx++) {
1834 		ret = sst_hsw_module_set_param(hsw,
1835 			SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1836 			WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1837 		if (ret < 0)
1838 			return ret;
1839 	}
1840 	return 0;
1841 }
1842 
sst_hsw_module_load(struct sst_hsw * hsw,u32 module_id,u32 instance_id,char * name)1843 int sst_hsw_module_load(struct sst_hsw *hsw,
1844 	u32 module_id, u32 instance_id, char *name)
1845 {
1846 	int ret = 0;
1847 	const struct firmware *fw = NULL;
1848 	struct sst_fw *hsw_sst_fw;
1849 	struct sst_module *module;
1850 	struct device *dev = hsw->dev;
1851 	struct sst_dsp *dsp = hsw->dsp;
1852 
1853 	dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1854 
1855 	module = sst_module_get_from_id(dsp, module_id);
1856 	if (module == NULL) {
1857 		/* loading for the first time */
1858 		if (module_id == SST_HSW_MODULE_BASE_FW) {
1859 			/* for base module: use fw requested in acpi probe */
1860 			fw = dsp->pdata->fw;
1861 			if (!fw) {
1862 				dev_err(dev, "request Base fw failed\n");
1863 				return -ENODEV;
1864 			}
1865 		} else {
1866 			/* try and load any other optional modules if they are
1867 			 * available. Use dev_info instead of dev_err in case
1868 			 * request firmware failed */
1869 			ret = request_firmware(&fw, name, dev);
1870 			if (ret) {
1871 				dev_info(dev, "fw image %s not available(%d)\n",
1872 						name, ret);
1873 				return ret;
1874 			}
1875 		}
1876 		hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1877 		if (hsw_sst_fw  == NULL) {
1878 			dev_err(dev, "error: failed to load firmware\n");
1879 			ret = -ENOMEM;
1880 			goto out;
1881 		}
1882 		module = sst_module_get_from_id(dsp, module_id);
1883 		if (module == NULL) {
1884 			dev_err(dev, "error: no module %d in firmware %s\n",
1885 					module_id, name);
1886 		}
1887 	} else
1888 		dev_info(dev, "module %d (%s) already loaded\n",
1889 				module_id, name);
1890 out:
1891 	/* release fw, but base fw should be released by acpi driver */
1892 	if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1893 		release_firmware(fw);
1894 
1895 	return ret;
1896 }
1897 
sst_hsw_module_enable(struct sst_hsw * hsw,u32 module_id,u32 instance_id)1898 int sst_hsw_module_enable(struct sst_hsw *hsw,
1899 	u32 module_id, u32 instance_id)
1900 {
1901 	int ret;
1902 	u32 header = 0;
1903 	struct sst_hsw_ipc_module_config config;
1904 	struct sst_module *module;
1905 	struct sst_module_runtime *runtime;
1906 	struct device *dev = hsw->dev;
1907 	struct sst_dsp *dsp = hsw->dsp;
1908 
1909 	if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1910 		dev_dbg(dev, "module %d not loaded\n", module_id);
1911 		return 0;
1912 	}
1913 
1914 	if (sst_hsw_is_module_active(hsw, module_id)) {
1915 		dev_info(dev, "module %d already enabled\n", module_id);
1916 		return 0;
1917 	}
1918 
1919 	module = sst_module_get_from_id(dsp, module_id);
1920 	if (module == NULL) {
1921 		dev_err(dev, "module %d not valid\n", module_id);
1922 		return -ENXIO;
1923 	}
1924 
1925 	runtime = sst_module_runtime_get_from_id(module, module_id);
1926 	if (runtime == NULL) {
1927 		dev_err(dev, "runtime %d not valid", module_id);
1928 		return -ENXIO;
1929 	}
1930 
1931 	header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1932 			IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1933 			IPC_MODULE_ID(module_id);
1934 	dev_dbg(dev, "module enable header: %x\n", header);
1935 
1936 	config.map.module_entries_count = 1;
1937 	config.map.module_entries[0].module_id = module->id;
1938 	config.map.module_entries[0].entry_point = module->entry;
1939 
1940 	config.persistent_mem.offset =
1941 		sst_dsp_get_offset(dsp,
1942 			runtime->persistent_offset, SST_MEM_DRAM);
1943 	config.persistent_mem.size = module->persistent_size;
1944 
1945 	config.scratch_mem.offset =
1946 		sst_dsp_get_offset(dsp,
1947 			dsp->scratch_offset, SST_MEM_DRAM);
1948 	config.scratch_mem.size = module->scratch_size;
1949 	dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1950 		config.map.module_entries[0].module_id,
1951 		config.persistent_mem.size,
1952 		config.persistent_mem.offset,
1953 		config.scratch_mem.size, config.scratch_mem.offset,
1954 		config.map.module_entries[0].entry_point);
1955 
1956 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
1957 			&config, sizeof(config), NULL, 0);
1958 	if (ret < 0)
1959 		dev_err(dev, "ipc: module enable failed - %d\n", ret);
1960 	else
1961 		module->state = SST_MODULE_STATE_ACTIVE;
1962 
1963 	return ret;
1964 }
1965 
sst_hsw_module_disable(struct sst_hsw * hsw,u32 module_id,u32 instance_id)1966 int sst_hsw_module_disable(struct sst_hsw *hsw,
1967 	u32 module_id, u32 instance_id)
1968 {
1969 	int ret;
1970 	u32 header;
1971 	struct sst_module *module;
1972 	struct device *dev = hsw->dev;
1973 	struct sst_dsp *dsp = hsw->dsp;
1974 
1975 	if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1976 		dev_dbg(dev, "module %d not loaded\n", module_id);
1977 		return 0;
1978 	}
1979 
1980 	if (!sst_hsw_is_module_active(hsw, module_id)) {
1981 		dev_info(dev, "module %d already disabled\n", module_id);
1982 		return 0;
1983 	}
1984 
1985 	module = sst_module_get_from_id(dsp, module_id);
1986 	if (module == NULL) {
1987 		dev_err(dev, "module %d not valid\n", module_id);
1988 		return -ENXIO;
1989 	}
1990 
1991 	header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1992 			IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1993 			IPC_MODULE_ID(module_id);
1994 
1995 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header,  NULL, 0, NULL, 0);
1996 	if (ret < 0)
1997 		dev_err(dev, "module disable failed - %d\n", ret);
1998 	else
1999 		module->state = SST_MODULE_STATE_INITIALIZED;
2000 
2001 	return ret;
2002 }
2003 
sst_hsw_module_set_param(struct sst_hsw * hsw,u32 module_id,u32 instance_id,u32 parameter_id,u32 param_size,char * param)2004 int sst_hsw_module_set_param(struct sst_hsw *hsw,
2005 	u32 module_id, u32 instance_id, u32 parameter_id,
2006 	u32 param_size, char *param)
2007 {
2008 	int ret;
2009 	unsigned char *data = NULL;
2010 	u32 header = 0;
2011 	u32 payload_size = 0, transfer_parameter_size = 0;
2012 	dma_addr_t dma_addr = 0;
2013 	struct sst_hsw_transfer_parameter *parameter;
2014 	struct device *dev = hsw->dev;
2015 
2016 	header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2017 			IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2018 			IPC_MODULE_ID(module_id);
2019 	dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2020 
2021 	payload_size = param_size +
2022 		sizeof(struct sst_hsw_transfer_parameter) -
2023 		sizeof(struct sst_hsw_transfer_list);
2024 	dev_dbg(dev, "parameter size : %d\n", param_size);
2025 	dev_dbg(dev, "payload size   : %d\n", payload_size);
2026 
2027 	if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2028 		/* short parameter, mailbox can contain data */
2029 		dev_dbg(dev, "transfer parameter size : %d\n",
2030 			transfer_parameter_size);
2031 
2032 		transfer_parameter_size = ALIGN(payload_size, 4);
2033 		dev_dbg(dev, "transfer parameter aligned size : %d\n",
2034 			transfer_parameter_size);
2035 
2036 		parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2037 		if (parameter == NULL)
2038 			return -ENOMEM;
2039 
2040 		memcpy(parameter->data, param, param_size);
2041 	} else {
2042 		dev_warn(dev, "transfer parameter size too large!");
2043 		return 0;
2044 	}
2045 
2046 	parameter->parameter_id = parameter_id;
2047 	parameter->data_size = param_size;
2048 
2049 	ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
2050 		parameter, transfer_parameter_size , NULL, 0);
2051 	if (ret < 0)
2052 		dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2053 
2054 	kfree(parameter);
2055 
2056 	if (data)
2057 		dma_free_coherent(hsw->dsp->dma_dev,
2058 			param_size, (void *)data, dma_addr);
2059 
2060 	return ret;
2061 }
2062 
2063 static struct sst_dsp_device hsw_dev = {
2064 	.thread = hsw_irq_thread,
2065 	.ops = &haswell_ops,
2066 };
2067 
hsw_tx_msg(struct sst_generic_ipc * ipc,struct ipc_message * msg)2068 static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2069 {
2070 	/* send the message */
2071 	sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2072 	sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2073 }
2074 
hsw_shim_dbg(struct sst_generic_ipc * ipc,const char * text)2075 static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2076 {
2077 	struct sst_dsp *sst = ipc->dsp;
2078 	u32 isr, ipcd, imrx, ipcx;
2079 
2080 	ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2081 	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2082 	ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2083 	imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2084 
2085 	dev_err(ipc->dev,
2086 		"ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2087 		text, ipcx, isr, ipcd, imrx);
2088 }
2089 
hsw_tx_data_copy(struct ipc_message * msg,char * tx_data,size_t tx_size)2090 static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2091 	size_t tx_size)
2092 {
2093 	memcpy(msg->tx_data, tx_data, tx_size);
2094 }
2095 
hsw_reply_msg_match(u64 header,u64 * mask)2096 static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2097 {
2098 	/* clear reply bits & status bits */
2099 	header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2100 	*mask = (u64)-1;
2101 
2102 	return header;
2103 }
2104 
hsw_is_dsp_busy(struct sst_dsp * dsp)2105 static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2106 {
2107 	u64 ipcx;
2108 
2109 	ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2110 	return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2111 }
2112 
sst_hsw_dsp_init(struct device * dev,struct sst_pdata * pdata)2113 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2114 {
2115 	struct sst_hsw_ipc_fw_version version;
2116 	struct sst_hsw *hsw;
2117 	struct sst_generic_ipc *ipc;
2118 	int ret;
2119 
2120 	dev_dbg(dev, "initialising Audio DSP IPC\n");
2121 
2122 	hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2123 	if (hsw == NULL)
2124 		return -ENOMEM;
2125 
2126 	hsw->dev = dev;
2127 
2128 	ipc = &hsw->ipc;
2129 	ipc->dev = dev;
2130 	ipc->ops.tx_msg = hsw_tx_msg;
2131 	ipc->ops.shim_dbg = hsw_shim_dbg;
2132 	ipc->ops.tx_data_copy = hsw_tx_data_copy;
2133 	ipc->ops.reply_msg_match = hsw_reply_msg_match;
2134 	ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
2135 
2136 	ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2137 	ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2138 
2139 	ret = sst_ipc_init(ipc);
2140 	if (ret != 0)
2141 		goto ipc_init_err;
2142 
2143 	INIT_LIST_HEAD(&hsw->stream_list);
2144 	init_waitqueue_head(&hsw->boot_wait);
2145 	hsw_dev.thread_context = hsw;
2146 
2147 	/* init SST shim */
2148 	hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2149 	if (hsw->dsp == NULL) {
2150 		ret = -ENODEV;
2151 		goto dsp_new_err;
2152 	}
2153 
2154 	ipc->dsp = hsw->dsp;
2155 
2156 	/* allocate DMA buffer for context storage */
2157 	hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2158 		SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2159 	if (hsw->dx_context == NULL) {
2160 		ret = -ENOMEM;
2161 		goto dma_err;
2162 	}
2163 
2164 	/* keep the DSP in reset state for base FW loading */
2165 	sst_dsp_reset(hsw->dsp);
2166 
2167 	/* load base module and other modules in base firmware image */
2168 	ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2169 	if (ret < 0)
2170 		goto fw_err;
2171 
2172 	/* try to load module waves */
2173 	sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2174 
2175 	/* allocate scratch mem regions */
2176 	ret = sst_block_alloc_scratch(hsw->dsp);
2177 	if (ret < 0)
2178 		goto boot_err;
2179 
2180 	/* init param buffer */
2181 	sst_hsw_reset_param_buf(hsw);
2182 
2183 	/* wait for DSP boot completion */
2184 	sst_dsp_boot(hsw->dsp);
2185 	ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2186 		msecs_to_jiffies(IPC_BOOT_MSECS));
2187 	if (ret == 0) {
2188 		ret = -EIO;
2189 		dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2190 			sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2191 			sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2192 		goto boot_err;
2193 	}
2194 
2195 	/* init module state after boot */
2196 	sst_hsw_init_module_state(hsw);
2197 
2198 	/* get the FW version */
2199 	sst_hsw_fw_get_version(hsw, &version);
2200 
2201 	/* get the globalmixer */
2202 	ret = sst_hsw_mixer_get_info(hsw);
2203 	if (ret < 0) {
2204 		dev_err(hsw->dev, "error: failed to get stream info\n");
2205 		goto boot_err;
2206 	}
2207 
2208 	pdata->dsp = hsw;
2209 	return 0;
2210 
2211 boot_err:
2212 	sst_dsp_reset(hsw->dsp);
2213 	sst_fw_free_all(hsw->dsp);
2214 fw_err:
2215 	dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2216 			hsw->dx_context, hsw->dx_context_paddr);
2217 dma_err:
2218 	sst_dsp_free(hsw->dsp);
2219 dsp_new_err:
2220 	sst_ipc_fini(ipc);
2221 ipc_init_err:
2222 	return ret;
2223 }
2224 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2225 
sst_hsw_dsp_free(struct device * dev,struct sst_pdata * pdata)2226 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2227 {
2228 	struct sst_hsw *hsw = pdata->dsp;
2229 
2230 	sst_dsp_reset(hsw->dsp);
2231 	sst_fw_free_all(hsw->dsp);
2232 	dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2233 			hsw->dx_context, hsw->dx_context_paddr);
2234 	sst_dsp_free(hsw->dsp);
2235 	sst_ipc_fini(&hsw->ipc);
2236 }
2237 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
2238