1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
20
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
25
26 /* Define max times to check status register before we give up. */
27
28 /*
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
31 */
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
33
34 /*
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
36 * for larger flash
37 */
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
39
40 #define SPI_NOR_MAX_ID_LEN 6
41
42 struct flash_info {
43 char *name;
44
45 /*
46 * This array stores the ID bytes.
47 * The first three bytes are the JEDIC ID.
48 * JEDEC ID zero means "no ID" (mostly older chips).
49 */
50 u8 id[SPI_NOR_MAX_ID_LEN];
51 u8 id_len;
52
53 /* The size listed here is what works with SPINOR_OP_SE, which isn't
54 * necessarily called a "sector" by the vendor.
55 */
56 unsigned sector_size;
57 u16 n_sectors;
58
59 u16 page_size;
60 u16 addr_width;
61
62 u16 flags;
63 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
64 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
65 #define SST_WRITE 0x04 /* use SST byte programming */
66 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
67 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
68 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
69 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
70 #define USE_FSR 0x80 /* use flag status register */
71 };
72
73 #define JEDEC_MFR(info) ((info)->id[0])
74
75 static const struct flash_info *spi_nor_match_id(const char *name);
76
77 /*
78 * Read the status register, returning its value in the location
79 * Return the status register value.
80 * Returns negative if error occurred.
81 */
read_sr(struct spi_nor * nor)82 static int read_sr(struct spi_nor *nor)
83 {
84 int ret;
85 u8 val;
86
87 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
88 if (ret < 0) {
89 pr_err("error %d reading SR\n", (int) ret);
90 return ret;
91 }
92
93 return val;
94 }
95
96 /*
97 * Read the flag status register, returning its value in the location
98 * Return the status register value.
99 * Returns negative if error occurred.
100 */
read_fsr(struct spi_nor * nor)101 static int read_fsr(struct spi_nor *nor)
102 {
103 int ret;
104 u8 val;
105
106 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
107 if (ret < 0) {
108 pr_err("error %d reading FSR\n", ret);
109 return ret;
110 }
111
112 return val;
113 }
114
115 /*
116 * Read configuration register, returning its value in the
117 * location. Return the configuration register value.
118 * Returns negative if error occured.
119 */
read_cr(struct spi_nor * nor)120 static int read_cr(struct spi_nor *nor)
121 {
122 int ret;
123 u8 val;
124
125 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
126 if (ret < 0) {
127 dev_err(nor->dev, "error %d reading CR\n", ret);
128 return ret;
129 }
130
131 return val;
132 }
133
134 /*
135 * Dummy Cycle calculation for different type of read.
136 * It can be used to support more commands with
137 * different dummy cycle requirements.
138 */
spi_nor_read_dummy_cycles(struct spi_nor * nor)139 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
140 {
141 switch (nor->flash_read) {
142 case SPI_NOR_FAST:
143 case SPI_NOR_DUAL:
144 case SPI_NOR_QUAD:
145 return 8;
146 case SPI_NOR_NORMAL:
147 return 0;
148 }
149 return 0;
150 }
151
152 /*
153 * Write status register 1 byte
154 * Returns negative if error occurred.
155 */
write_sr(struct spi_nor * nor,u8 val)156 static inline int write_sr(struct spi_nor *nor, u8 val)
157 {
158 nor->cmd_buf[0] = val;
159 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
160 }
161
162 /*
163 * Set write enable latch with Write Enable command.
164 * Returns negative if error occurred.
165 */
write_enable(struct spi_nor * nor)166 static inline int write_enable(struct spi_nor *nor)
167 {
168 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
169 }
170
171 /*
172 * Send write disble instruction to the chip.
173 */
write_disable(struct spi_nor * nor)174 static inline int write_disable(struct spi_nor *nor)
175 {
176 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
177 }
178
mtd_to_spi_nor(struct mtd_info * mtd)179 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
180 {
181 return mtd->priv;
182 }
183
184 /* Enable/disable 4-byte addressing mode. */
set_4byte(struct spi_nor * nor,const struct flash_info * info,int enable)185 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
186 int enable)
187 {
188 int status;
189 bool need_wren = false;
190 u8 cmd;
191
192 switch (JEDEC_MFR(info)) {
193 case SNOR_MFR_MICRON:
194 /* Some Micron need WREN command; all will accept it */
195 need_wren = true;
196 case SNOR_MFR_MACRONIX:
197 case SNOR_MFR_WINBOND:
198 if (need_wren)
199 write_enable(nor);
200
201 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
202 status = nor->write_reg(nor, cmd, NULL, 0);
203 if (need_wren)
204 write_disable(nor);
205
206 return status;
207 default:
208 /* Spansion style */
209 nor->cmd_buf[0] = enable << 7;
210 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
211 }
212 }
spi_nor_sr_ready(struct spi_nor * nor)213 static inline int spi_nor_sr_ready(struct spi_nor *nor)
214 {
215 int sr = read_sr(nor);
216 if (sr < 0)
217 return sr;
218 else
219 return !(sr & SR_WIP);
220 }
221
spi_nor_fsr_ready(struct spi_nor * nor)222 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
223 {
224 int fsr = read_fsr(nor);
225 if (fsr < 0)
226 return fsr;
227 else
228 return fsr & FSR_READY;
229 }
230
spi_nor_ready(struct spi_nor * nor)231 static int spi_nor_ready(struct spi_nor *nor)
232 {
233 int sr, fsr;
234 sr = spi_nor_sr_ready(nor);
235 if (sr < 0)
236 return sr;
237 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
238 if (fsr < 0)
239 return fsr;
240 return sr && fsr;
241 }
242
243 /*
244 * Service routine to read status register until ready, or timeout occurs.
245 * Returns non-zero if error.
246 */
spi_nor_wait_till_ready_with_timeout(struct spi_nor * nor,unsigned long timeout_jiffies)247 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
248 unsigned long timeout_jiffies)
249 {
250 unsigned long deadline;
251 int timeout = 0, ret;
252
253 deadline = jiffies + timeout_jiffies;
254
255 while (!timeout) {
256 if (time_after_eq(jiffies, deadline))
257 timeout = 1;
258
259 ret = spi_nor_ready(nor);
260 if (ret < 0)
261 return ret;
262 if (ret)
263 return 0;
264
265 cond_resched();
266 }
267
268 dev_err(nor->dev, "flash operation timed out\n");
269
270 return -ETIMEDOUT;
271 }
272
spi_nor_wait_till_ready(struct spi_nor * nor)273 static int spi_nor_wait_till_ready(struct spi_nor *nor)
274 {
275 return spi_nor_wait_till_ready_with_timeout(nor,
276 DEFAULT_READY_WAIT_JIFFIES);
277 }
278
279 /*
280 * Erase the whole flash memory
281 *
282 * Returns 0 if successful, non-zero otherwise.
283 */
erase_chip(struct spi_nor * nor)284 static int erase_chip(struct spi_nor *nor)
285 {
286 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
287
288 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
289 }
290
spi_nor_lock_and_prep(struct spi_nor * nor,enum spi_nor_ops ops)291 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
292 {
293 int ret = 0;
294
295 mutex_lock(&nor->lock);
296
297 if (nor->prepare) {
298 ret = nor->prepare(nor, ops);
299 if (ret) {
300 dev_err(nor->dev, "failed in the preparation.\n");
301 mutex_unlock(&nor->lock);
302 return ret;
303 }
304 }
305 return ret;
306 }
307
spi_nor_unlock_and_unprep(struct spi_nor * nor,enum spi_nor_ops ops)308 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
309 {
310 if (nor->unprepare)
311 nor->unprepare(nor, ops);
312 mutex_unlock(&nor->lock);
313 }
314
315 /*
316 * Erase an address range on the nor chip. The address range may extend
317 * one or more erase sectors. Return an error is there is a problem erasing.
318 */
spi_nor_erase(struct mtd_info * mtd,struct erase_info * instr)319 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
320 {
321 struct spi_nor *nor = mtd_to_spi_nor(mtd);
322 u32 addr, len;
323 uint32_t rem;
324 int ret;
325
326 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
327 (long long)instr->len);
328
329 div_u64_rem(instr->len, mtd->erasesize, &rem);
330 if (rem)
331 return -EINVAL;
332
333 addr = instr->addr;
334 len = instr->len;
335
336 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
337 if (ret)
338 return ret;
339
340 /* whole-chip erase? */
341 if (len == mtd->size) {
342 unsigned long timeout;
343
344 write_enable(nor);
345
346 if (erase_chip(nor)) {
347 ret = -EIO;
348 goto erase_err;
349 }
350
351 /*
352 * Scale the timeout linearly with the size of the flash, with
353 * a minimum calibrated to an old 2MB flash. We could try to
354 * pull these from CFI/SFDP, but these values should be good
355 * enough for now.
356 */
357 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
358 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
359 (unsigned long)(mtd->size / SZ_2M));
360 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
361 if (ret)
362 goto erase_err;
363
364 /* REVISIT in some cases we could speed up erasing large regions
365 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
366 * to use "small sector erase", but that's not always optimal.
367 */
368
369 /* "sector"-at-a-time erase */
370 } else {
371 while (len) {
372 write_enable(nor);
373
374 if (nor->erase(nor, addr)) {
375 ret = -EIO;
376 goto erase_err;
377 }
378
379 addr += mtd->erasesize;
380 len -= mtd->erasesize;
381
382 ret = spi_nor_wait_till_ready(nor);
383 if (ret)
384 goto erase_err;
385 }
386 }
387
388 write_disable(nor);
389
390 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
391
392 instr->state = MTD_ERASE_DONE;
393 mtd_erase_callback(instr);
394
395 return ret;
396
397 erase_err:
398 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
399 instr->state = MTD_ERASE_FAILED;
400 return ret;
401 }
402
stm_get_locked_range(struct spi_nor * nor,u8 sr,loff_t * ofs,uint64_t * len)403 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
404 uint64_t *len)
405 {
406 struct mtd_info *mtd = &nor->mtd;
407 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
408 int shift = ffs(mask) - 1;
409 int pow;
410
411 if (!(sr & mask)) {
412 /* No protection */
413 *ofs = 0;
414 *len = 0;
415 } else {
416 pow = ((sr & mask) ^ mask) >> shift;
417 *len = mtd->size >> pow;
418 *ofs = mtd->size - *len;
419 }
420 }
421
422 /*
423 * Return 1 if the entire region is locked, 0 otherwise
424 */
stm_is_locked_sr(struct spi_nor * nor,loff_t ofs,uint64_t len,u8 sr)425 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
426 u8 sr)
427 {
428 loff_t lock_offs;
429 uint64_t lock_len;
430
431 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
432
433 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
434 }
435
436 /*
437 * Lock a region of the flash. Compatible with ST Micro and similar flash.
438 * Supports only the block protection bits BP{0,1,2} in the status register
439 * (SR). Does not support these features found in newer SR bitfields:
440 * - TB: top/bottom protect - only handle TB=0 (top protect)
441 * - SEC: sector/block protect - only handle SEC=0 (block protect)
442 * - CMP: complement protect - only support CMP=0 (range is not complemented)
443 *
444 * Sample table portion for 8MB flash (Winbond w25q64fw):
445 *
446 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
447 * --------------------------------------------------------------------------
448 * X | X | 0 | 0 | 0 | NONE | NONE
449 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
450 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
451 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
452 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
453 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
454 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
455 * X | X | 1 | 1 | 1 | 8 MB | ALL
456 *
457 * Returns negative on errors, 0 on success.
458 */
stm_lock(struct spi_nor * nor,loff_t ofs,uint64_t len)459 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
460 {
461 struct mtd_info *mtd = &nor->mtd;
462 u8 status_old, status_new;
463 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
464 u8 shift = ffs(mask) - 1, pow, val;
465
466 status_old = read_sr(nor);
467
468 /* SPI NOR always locks to the end */
469 if (ofs + len != mtd->size) {
470 /* Does combined region extend to end? */
471 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
472 status_old))
473 return -EINVAL;
474 len = mtd->size - ofs;
475 }
476
477 /*
478 * Need smallest pow such that:
479 *
480 * 1 / (2^pow) <= (len / size)
481 *
482 * so (assuming power-of-2 size) we do:
483 *
484 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
485 */
486 pow = ilog2(mtd->size) - ilog2(len);
487 val = mask - (pow << shift);
488 if (val & ~mask)
489 return -EINVAL;
490 /* Don't "lock" with no region! */
491 if (!(val & mask))
492 return -EINVAL;
493
494 status_new = (status_old & ~mask) | val;
495
496 /* Only modify protection if it will not unlock other areas */
497 if ((status_new & mask) <= (status_old & mask))
498 return -EINVAL;
499
500 write_enable(nor);
501 return write_sr(nor, status_new);
502 }
503
504 /*
505 * Unlock a region of the flash. See stm_lock() for more info
506 *
507 * Returns negative on errors, 0 on success.
508 */
stm_unlock(struct spi_nor * nor,loff_t ofs,uint64_t len)509 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
510 {
511 struct mtd_info *mtd = &nor->mtd;
512 uint8_t status_old, status_new;
513 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
514 u8 shift = ffs(mask) - 1, pow, val;
515
516 status_old = read_sr(nor);
517
518 /* Cannot unlock; would unlock larger region than requested */
519 if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
520 status_old))
521 return -EINVAL;
522
523 /*
524 * Need largest pow such that:
525 *
526 * 1 / (2^pow) >= (len / size)
527 *
528 * so (assuming power-of-2 size) we do:
529 *
530 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
531 */
532 pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
533 if (ofs + len == mtd->size) {
534 val = 0; /* fully unlocked */
535 } else {
536 val = mask - (pow << shift);
537 /* Some power-of-two sizes are not supported */
538 if (val & ~mask)
539 return -EINVAL;
540 }
541
542 status_new = (status_old & ~mask) | val;
543
544 /* Only modify protection if it will not lock other areas */
545 if ((status_new & mask) >= (status_old & mask))
546 return -EINVAL;
547
548 write_enable(nor);
549 return write_sr(nor, status_new);
550 }
551
552 /*
553 * Check if a region of the flash is (completely) locked. See stm_lock() for
554 * more info.
555 *
556 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
557 * negative on errors.
558 */
stm_is_locked(struct spi_nor * nor,loff_t ofs,uint64_t len)559 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
560 {
561 int status;
562
563 status = read_sr(nor);
564 if (status < 0)
565 return status;
566
567 return stm_is_locked_sr(nor, ofs, len, status);
568 }
569
spi_nor_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)570 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
571 {
572 struct spi_nor *nor = mtd_to_spi_nor(mtd);
573 int ret;
574
575 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
576 if (ret)
577 return ret;
578
579 ret = nor->flash_lock(nor, ofs, len);
580
581 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
582 return ret;
583 }
584
spi_nor_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)585 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
586 {
587 struct spi_nor *nor = mtd_to_spi_nor(mtd);
588 int ret;
589
590 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
591 if (ret)
592 return ret;
593
594 ret = nor->flash_unlock(nor, ofs, len);
595
596 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
597 return ret;
598 }
599
spi_nor_is_locked(struct mtd_info * mtd,loff_t ofs,uint64_t len)600 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
601 {
602 struct spi_nor *nor = mtd_to_spi_nor(mtd);
603 int ret;
604
605 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
606 if (ret)
607 return ret;
608
609 ret = nor->flash_is_locked(nor, ofs, len);
610
611 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
612 return ret;
613 }
614
615 /* Used when the "_ext_id" is two bytes at most */
616 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
617 .id = { \
618 ((_jedec_id) >> 16) & 0xff, \
619 ((_jedec_id) >> 8) & 0xff, \
620 (_jedec_id) & 0xff, \
621 ((_ext_id) >> 8) & 0xff, \
622 (_ext_id) & 0xff, \
623 }, \
624 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
625 .sector_size = (_sector_size), \
626 .n_sectors = (_n_sectors), \
627 .page_size = 256, \
628 .flags = (_flags),
629
630 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
631 .id = { \
632 ((_jedec_id) >> 16) & 0xff, \
633 ((_jedec_id) >> 8) & 0xff, \
634 (_jedec_id) & 0xff, \
635 ((_ext_id) >> 16) & 0xff, \
636 ((_ext_id) >> 8) & 0xff, \
637 (_ext_id) & 0xff, \
638 }, \
639 .id_len = 6, \
640 .sector_size = (_sector_size), \
641 .n_sectors = (_n_sectors), \
642 .page_size = 256, \
643 .flags = (_flags),
644
645 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
646 .sector_size = (_sector_size), \
647 .n_sectors = (_n_sectors), \
648 .page_size = (_page_size), \
649 .addr_width = (_addr_width), \
650 .flags = (_flags),
651
652 /* NOTE: double check command sets and memory organization when you add
653 * more nor chips. This current list focusses on newer chips, which
654 * have been converging on command sets which including JEDEC ID.
655 *
656 * All newly added entries should describe *hardware* and should use SECT_4K
657 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
658 * scenarios excluding small sectors there is config option that can be
659 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
660 * For historical (and compatibility) reasons (before we got above config) some
661 * old entries may be missing 4K flag.
662 */
663 static const struct flash_info spi_nor_ids[] = {
664 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
665 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
666 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
667
668 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
669 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
670 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
671
672 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
673 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
674 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
675 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
676
677 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
678
679 /* EON -- en25xxx */
680 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
681 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
682 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
683 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
684 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
685 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
686 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
687 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
688
689 /* ESMT */
690 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
691
692 /* Everspin */
693 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
694 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
695
696 /* Fujitsu */
697 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
698
699 /* GigaDevice */
700 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
701 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
702 { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
703
704 /* Intel/Numonyx -- xxxs33b */
705 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
706 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
707 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
708
709 /* ISSI */
710 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
711
712 /* Macronix */
713 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
714 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
715 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
716 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
717 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
718 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
719 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
720 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
721 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
722 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
723 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
724 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
725 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
726 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
727 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
728
729 /* Micron */
730 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
731 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
732 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
733 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
734 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
735 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
736 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
737 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
738 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
739 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
740
741 /* PMC */
742 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
743 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
744 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
745
746 /* Spansion -- single (large) sector size only, at least
747 * for the chips listed here (without boot sectors).
748 */
749 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
750 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
751 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
752 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
753 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
754 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
755 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
756 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
757 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
758 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
759 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
760 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
761 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
762 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
763 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
764 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
765 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
766 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
767 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
768 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
769 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
770 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
771 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
772
773 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
774 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
775 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
776 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
777 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
778 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
779 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
780 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
781 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
782 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
783 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
784 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
785 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
786
787 /* ST Microelectronics -- newer production may have feature updates */
788 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
789 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
790 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
791 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
792 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
793 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
794 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
795 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
796 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
797
798 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
799 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
800 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
801 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
802 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
803 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
804 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
805 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
806 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
807
808 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
809 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
810 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
811
812 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
813 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
814 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
815
816 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
817 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
818 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
819 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
820 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
821 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
822
823 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
824 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
825 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
826 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
827 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
828 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
829 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
830 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
831 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
832 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
833 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
834 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
835 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
836 { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
837 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
838 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
839 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
840 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
841
842 /* Catalyst / On Semiconductor -- non-JEDEC */
843 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
844 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
845 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
846 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
847 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
848 { },
849 };
850
spi_nor_read_id(struct spi_nor * nor)851 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
852 {
853 int tmp;
854 u8 id[SPI_NOR_MAX_ID_LEN];
855 const struct flash_info *info;
856
857 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
858 if (tmp < 0) {
859 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
860 return ERR_PTR(tmp);
861 }
862
863 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
864 info = &spi_nor_ids[tmp];
865 if (info->id_len) {
866 if (!memcmp(info->id, id, info->id_len))
867 return &spi_nor_ids[tmp];
868 }
869 }
870 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
871 id[0], id[1], id[2]);
872 return ERR_PTR(-ENODEV);
873 }
874
spi_nor_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)875 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
876 size_t *retlen, u_char *buf)
877 {
878 struct spi_nor *nor = mtd_to_spi_nor(mtd);
879 int ret;
880
881 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
882
883 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
884 if (ret)
885 return ret;
886
887 ret = nor->read(nor, from, len, retlen, buf);
888
889 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
890 return ret;
891 }
892
sst_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)893 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
894 size_t *retlen, const u_char *buf)
895 {
896 struct spi_nor *nor = mtd_to_spi_nor(mtd);
897 size_t actual;
898 int ret;
899
900 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
901
902 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
903 if (ret)
904 return ret;
905
906 write_enable(nor);
907
908 nor->sst_write_second = false;
909
910 actual = to % 2;
911 /* Start write from odd address. */
912 if (actual) {
913 nor->program_opcode = SPINOR_OP_BP;
914
915 /* write one byte. */
916 nor->write(nor, to, 1, retlen, buf);
917 ret = spi_nor_wait_till_ready(nor);
918 if (ret)
919 goto time_out;
920 }
921 to += actual;
922
923 /* Write out most of the data here. */
924 for (; actual < len - 1; actual += 2) {
925 nor->program_opcode = SPINOR_OP_AAI_WP;
926
927 /* write two bytes. */
928 nor->write(nor, to, 2, retlen, buf + actual);
929 ret = spi_nor_wait_till_ready(nor);
930 if (ret)
931 goto time_out;
932 to += 2;
933 nor->sst_write_second = true;
934 }
935 nor->sst_write_second = false;
936
937 write_disable(nor);
938 ret = spi_nor_wait_till_ready(nor);
939 if (ret)
940 goto time_out;
941
942 /* Write out trailing byte if it exists. */
943 if (actual != len) {
944 write_enable(nor);
945
946 nor->program_opcode = SPINOR_OP_BP;
947 nor->write(nor, to, 1, retlen, buf + actual);
948
949 ret = spi_nor_wait_till_ready(nor);
950 if (ret)
951 goto time_out;
952 write_disable(nor);
953 }
954 time_out:
955 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
956 return ret;
957 }
958
959 /*
960 * Write an address range to the nor chip. Data must be written in
961 * FLASH_PAGESIZE chunks. The address range may be any size provided
962 * it is within the physical boundaries.
963 */
spi_nor_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)964 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
965 size_t *retlen, const u_char *buf)
966 {
967 struct spi_nor *nor = mtd_to_spi_nor(mtd);
968 u32 page_offset, page_size, i;
969 int ret;
970
971 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
972
973 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
974 if (ret)
975 return ret;
976
977 write_enable(nor);
978
979 page_offset = to & (nor->page_size - 1);
980
981 /* do all the bytes fit onto one page? */
982 if (page_offset + len <= nor->page_size) {
983 nor->write(nor, to, len, retlen, buf);
984 } else {
985 /* the size of data remaining on the first page */
986 page_size = nor->page_size - page_offset;
987 nor->write(nor, to, page_size, retlen, buf);
988
989 /* write everything in nor->page_size chunks */
990 for (i = page_size; i < len; i += page_size) {
991 page_size = len - i;
992 if (page_size > nor->page_size)
993 page_size = nor->page_size;
994
995 ret = spi_nor_wait_till_ready(nor);
996 if (ret)
997 goto write_err;
998
999 write_enable(nor);
1000
1001 nor->write(nor, to + i, page_size, retlen, buf + i);
1002 }
1003 }
1004
1005 ret = spi_nor_wait_till_ready(nor);
1006 write_err:
1007 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1008 return ret;
1009 }
1010
macronix_quad_enable(struct spi_nor * nor)1011 static int macronix_quad_enable(struct spi_nor *nor)
1012 {
1013 int ret, val;
1014
1015 val = read_sr(nor);
1016 write_enable(nor);
1017
1018 write_sr(nor, val | SR_QUAD_EN_MX);
1019
1020 if (spi_nor_wait_till_ready(nor))
1021 return 1;
1022
1023 ret = read_sr(nor);
1024 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1025 dev_err(nor->dev, "Macronix Quad bit not set\n");
1026 return -EINVAL;
1027 }
1028
1029 return 0;
1030 }
1031
1032 /*
1033 * Write status Register and configuration register with 2 bytes
1034 * The first byte will be written to the status register, while the
1035 * second byte will be written to the configuration register.
1036 * Return negative if error occured.
1037 */
write_sr_cr(struct spi_nor * nor,u16 val)1038 static int write_sr_cr(struct spi_nor *nor, u16 val)
1039 {
1040 nor->cmd_buf[0] = val & 0xff;
1041 nor->cmd_buf[1] = (val >> 8);
1042
1043 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1044 }
1045
spansion_quad_enable(struct spi_nor * nor)1046 static int spansion_quad_enable(struct spi_nor *nor)
1047 {
1048 int ret;
1049 int quad_en = CR_QUAD_EN_SPAN << 8;
1050
1051 write_enable(nor);
1052
1053 ret = write_sr_cr(nor, quad_en);
1054 if (ret < 0) {
1055 dev_err(nor->dev,
1056 "error while writing configuration register\n");
1057 return -EINVAL;
1058 }
1059
1060 /* read back and check it */
1061 ret = read_cr(nor);
1062 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1063 dev_err(nor->dev, "Spansion Quad bit not set\n");
1064 return -EINVAL;
1065 }
1066
1067 return 0;
1068 }
1069
set_quad_mode(struct spi_nor * nor,const struct flash_info * info)1070 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1071 {
1072 int status;
1073
1074 switch (JEDEC_MFR(info)) {
1075 case SNOR_MFR_MACRONIX:
1076 status = macronix_quad_enable(nor);
1077 if (status) {
1078 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1079 return -EINVAL;
1080 }
1081 return status;
1082 case SNOR_MFR_MICRON:
1083 return 0;
1084 default:
1085 status = spansion_quad_enable(nor);
1086 if (status) {
1087 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1088 return -EINVAL;
1089 }
1090 return status;
1091 }
1092 }
1093
spi_nor_check(struct spi_nor * nor)1094 static int spi_nor_check(struct spi_nor *nor)
1095 {
1096 if (!nor->dev || !nor->read || !nor->write ||
1097 !nor->read_reg || !nor->write_reg || !nor->erase) {
1098 pr_err("spi-nor: please fill all the necessary fields!\n");
1099 return -EINVAL;
1100 }
1101
1102 return 0;
1103 }
1104
spi_nor_scan(struct spi_nor * nor,const char * name,enum read_mode mode)1105 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1106 {
1107 const struct flash_info *info = NULL;
1108 struct device *dev = nor->dev;
1109 struct mtd_info *mtd = &nor->mtd;
1110 struct device_node *np = nor->flash_node;
1111 int ret;
1112 int i;
1113
1114 ret = spi_nor_check(nor);
1115 if (ret)
1116 return ret;
1117
1118 if (name)
1119 info = spi_nor_match_id(name);
1120 /* Try to auto-detect if chip name wasn't specified or not found */
1121 if (!info)
1122 info = spi_nor_read_id(nor);
1123 if (IS_ERR_OR_NULL(info))
1124 return -ENOENT;
1125
1126 /*
1127 * If caller has specified name of flash model that can normally be
1128 * detected using JEDEC, let's verify it.
1129 */
1130 if (name && info->id_len) {
1131 const struct flash_info *jinfo;
1132
1133 jinfo = spi_nor_read_id(nor);
1134 if (IS_ERR(jinfo)) {
1135 return PTR_ERR(jinfo);
1136 } else if (jinfo != info) {
1137 /*
1138 * JEDEC knows better, so overwrite platform ID. We
1139 * can't trust partitions any longer, but we'll let
1140 * mtd apply them anyway, since some partitions may be
1141 * marked read-only, and we don't want to lose that
1142 * information, even if it's not 100% accurate.
1143 */
1144 dev_warn(dev, "found %s, expected %s\n",
1145 jinfo->name, info->name);
1146 info = jinfo;
1147 }
1148 }
1149
1150 mutex_init(&nor->lock);
1151
1152 /*
1153 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1154 * with the software protection bits set
1155 */
1156
1157 if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1158 JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1159 JEDEC_MFR(info) == SNOR_MFR_SST) {
1160 write_enable(nor);
1161 write_sr(nor, 0);
1162 }
1163
1164 if (!mtd->name)
1165 mtd->name = dev_name(dev);
1166 mtd->priv = nor;
1167 mtd->type = MTD_NORFLASH;
1168 mtd->writesize = 1;
1169 mtd->flags = MTD_CAP_NORFLASH;
1170 mtd->size = info->sector_size * info->n_sectors;
1171 mtd->_erase = spi_nor_erase;
1172 mtd->_read = spi_nor_read;
1173
1174 /* NOR protection support for STmicro/Micron chips and similar */
1175 if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
1176 nor->flash_lock = stm_lock;
1177 nor->flash_unlock = stm_unlock;
1178 nor->flash_is_locked = stm_is_locked;
1179 }
1180
1181 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1182 mtd->_lock = spi_nor_lock;
1183 mtd->_unlock = spi_nor_unlock;
1184 mtd->_is_locked = spi_nor_is_locked;
1185 }
1186
1187 /* sst nor chips use AAI word program */
1188 if (info->flags & SST_WRITE)
1189 mtd->_write = sst_write;
1190 else
1191 mtd->_write = spi_nor_write;
1192
1193 if (info->flags & USE_FSR)
1194 nor->flags |= SNOR_F_USE_FSR;
1195
1196 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1197 /* prefer "small sector" erase if possible */
1198 if (info->flags & SECT_4K) {
1199 nor->erase_opcode = SPINOR_OP_BE_4K;
1200 mtd->erasesize = 4096;
1201 } else if (info->flags & SECT_4K_PMC) {
1202 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1203 mtd->erasesize = 4096;
1204 } else
1205 #endif
1206 {
1207 nor->erase_opcode = SPINOR_OP_SE;
1208 mtd->erasesize = info->sector_size;
1209 }
1210
1211 if (info->flags & SPI_NOR_NO_ERASE)
1212 mtd->flags |= MTD_NO_ERASE;
1213
1214 mtd->dev.parent = dev;
1215 nor->page_size = info->page_size;
1216 mtd->writebufsize = nor->page_size;
1217
1218 if (np) {
1219 /* If we were instantiated by DT, use it */
1220 if (of_property_read_bool(np, "m25p,fast-read"))
1221 nor->flash_read = SPI_NOR_FAST;
1222 else
1223 nor->flash_read = SPI_NOR_NORMAL;
1224 } else {
1225 /* If we weren't instantiated by DT, default to fast-read */
1226 nor->flash_read = SPI_NOR_FAST;
1227 }
1228
1229 /* Some devices cannot do fast-read, no matter what DT tells us */
1230 if (info->flags & SPI_NOR_NO_FR)
1231 nor->flash_read = SPI_NOR_NORMAL;
1232
1233 /* Quad/Dual-read mode takes precedence over fast/normal */
1234 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1235 ret = set_quad_mode(nor, info);
1236 if (ret) {
1237 dev_err(dev, "quad mode not supported\n");
1238 return ret;
1239 }
1240 nor->flash_read = SPI_NOR_QUAD;
1241 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1242 nor->flash_read = SPI_NOR_DUAL;
1243 }
1244
1245 /* Default commands */
1246 switch (nor->flash_read) {
1247 case SPI_NOR_QUAD:
1248 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1249 break;
1250 case SPI_NOR_DUAL:
1251 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1252 break;
1253 case SPI_NOR_FAST:
1254 nor->read_opcode = SPINOR_OP_READ_FAST;
1255 break;
1256 case SPI_NOR_NORMAL:
1257 nor->read_opcode = SPINOR_OP_READ;
1258 break;
1259 default:
1260 dev_err(dev, "No Read opcode defined\n");
1261 return -EINVAL;
1262 }
1263
1264 nor->program_opcode = SPINOR_OP_PP;
1265
1266 if (info->addr_width)
1267 nor->addr_width = info->addr_width;
1268 else if (mtd->size > 0x1000000) {
1269 /* enable 4-byte addressing if the device exceeds 16MiB */
1270 nor->addr_width = 4;
1271 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1272 /* Dedicated 4-byte command set */
1273 switch (nor->flash_read) {
1274 case SPI_NOR_QUAD:
1275 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1276 break;
1277 case SPI_NOR_DUAL:
1278 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1279 break;
1280 case SPI_NOR_FAST:
1281 nor->read_opcode = SPINOR_OP_READ4_FAST;
1282 break;
1283 case SPI_NOR_NORMAL:
1284 nor->read_opcode = SPINOR_OP_READ4;
1285 break;
1286 }
1287 nor->program_opcode = SPINOR_OP_PP_4B;
1288 /* No small sector erase for 4-byte command set */
1289 nor->erase_opcode = SPINOR_OP_SE_4B;
1290 mtd->erasesize = info->sector_size;
1291 } else
1292 set_4byte(nor, info, 1);
1293 } else {
1294 nor->addr_width = 3;
1295 }
1296
1297 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1298
1299 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1300 (long long)mtd->size >> 10);
1301
1302 dev_dbg(dev,
1303 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1304 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1305 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1306 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1307
1308 if (mtd->numeraseregions)
1309 for (i = 0; i < mtd->numeraseregions; i++)
1310 dev_dbg(dev,
1311 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1312 ".erasesize = 0x%.8x (%uKiB), "
1313 ".numblocks = %d }\n",
1314 i, (long long)mtd->eraseregions[i].offset,
1315 mtd->eraseregions[i].erasesize,
1316 mtd->eraseregions[i].erasesize / 1024,
1317 mtd->eraseregions[i].numblocks);
1318 return 0;
1319 }
1320 EXPORT_SYMBOL_GPL(spi_nor_scan);
1321
spi_nor_match_id(const char * name)1322 static const struct flash_info *spi_nor_match_id(const char *name)
1323 {
1324 const struct flash_info *id = spi_nor_ids;
1325
1326 while (id->name) {
1327 if (!strcmp(name, id->name))
1328 return id;
1329 id++;
1330 }
1331 return NULL;
1332 }
1333
1334 MODULE_LICENSE("GPL");
1335 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1336 MODULE_AUTHOR("Mike Lavender");
1337 MODULE_DESCRIPTION("framework for SPI NOR");
1338