1 /* 2 * SH-X3 prototype CPU pinmux 3 * 4 * Copyright (C) 2010 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <cpu/shx3.h> 13 14 #include "sh_pfc.h" 15 16 enum { 17 PINMUX_RESERVED = 0, 18 19 PINMUX_DATA_BEGIN, 20 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 21 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 22 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 23 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, 24 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 25 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 26 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 27 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, 28 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 29 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, 30 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 31 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, 32 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 33 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, 34 35 PH5_DATA, PH4_DATA, 36 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, 37 PINMUX_DATA_END, 38 39 PINMUX_INPUT_BEGIN, 40 PA7_IN, PA6_IN, PA5_IN, PA4_IN, 41 PA3_IN, PA2_IN, PA1_IN, PA0_IN, 42 PB7_IN, PB6_IN, PB5_IN, PB4_IN, 43 PB3_IN, PB2_IN, PB1_IN, PB0_IN, 44 PC7_IN, PC6_IN, PC5_IN, PC4_IN, 45 PC3_IN, PC2_IN, PC1_IN, PC0_IN, 46 PD7_IN, PD6_IN, PD5_IN, PD4_IN, 47 PD3_IN, PD2_IN, PD1_IN, PD0_IN, 48 PE7_IN, PE6_IN, PE5_IN, PE4_IN, 49 PE3_IN, PE2_IN, PE1_IN, PE0_IN, 50 PF7_IN, PF6_IN, PF5_IN, PF4_IN, 51 PF3_IN, PF2_IN, PF1_IN, PF0_IN, 52 PG7_IN, PG6_IN, PG5_IN, PG4_IN, 53 PG3_IN, PG2_IN, PG1_IN, PG0_IN, 54 55 PH5_IN, PH4_IN, 56 PH3_IN, PH2_IN, PH1_IN, PH0_IN, 57 PINMUX_INPUT_END, 58 59 PINMUX_OUTPUT_BEGIN, 60 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, 61 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, 62 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, 63 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, 64 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, 65 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, 66 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, 67 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, 68 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, 69 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, 70 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, 71 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, 72 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, 73 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, 74 75 PH5_OUT, PH4_OUT, 76 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, 77 PINMUX_OUTPUT_END, 78 79 PINMUX_FUNCTION_BEGIN, 80 PA7_FN, PA6_FN, PA5_FN, PA4_FN, 81 PA3_FN, PA2_FN, PA1_FN, PA0_FN, 82 PB7_FN, PB6_FN, PB5_FN, PB4_FN, 83 PB3_FN, PB2_FN, PB1_FN, PB0_FN, 84 PC7_FN, PC6_FN, PC5_FN, PC4_FN, 85 PC3_FN, PC2_FN, PC1_FN, PC0_FN, 86 PD7_FN, PD6_FN, PD5_FN, PD4_FN, 87 PD3_FN, PD2_FN, PD1_FN, PD0_FN, 88 PE7_FN, PE6_FN, PE5_FN, PE4_FN, 89 PE3_FN, PE2_FN, PE1_FN, PE0_FN, 90 PF7_FN, PF6_FN, PF5_FN, PF4_FN, 91 PF3_FN, PF2_FN, PF1_FN, PF0_FN, 92 PG7_FN, PG6_FN, PG5_FN, PG4_FN, 93 PG3_FN, PG2_FN, PG1_FN, PG0_FN, 94 95 PH5_FN, PH4_FN, 96 PH3_FN, PH2_FN, PH1_FN, PH0_FN, 97 PINMUX_FUNCTION_END, 98 99 PINMUX_MARK_BEGIN, 100 101 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK, 102 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK, 103 D19_MARK, D18_MARK, D17_MARK, D16_MARK, 104 105 BACK_MARK, BREQ_MARK, 106 WE3_MARK, WE2_MARK, 107 CS6_MARK, CS5_MARK, CS4_MARK, 108 CLKOUTENB_MARK, 109 110 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK, 111 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK, 112 113 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, 114 115 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK, 116 117 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK, 118 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK, 119 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK, 120 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK, 121 122 CE2B_MARK, CE2A_MARK, IOIS16_MARK, 123 STATUS1_MARK, STATUS0_MARK, 124 125 IRQOUT_MARK, 126 127 PINMUX_MARK_END, 128 }; 129 130 static const u16 pinmux_data[] = { 131 /* PA GPIO */ 132 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), 133 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), 134 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), 135 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), 136 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), 137 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), 138 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), 139 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), 140 141 /* PB GPIO */ 142 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), 143 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), 144 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), 145 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), 146 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), 147 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), 148 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), 149 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), 150 151 /* PC GPIO */ 152 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), 153 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), 154 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), 155 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), 156 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), 157 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), 158 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), 159 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), 160 161 /* PD GPIO */ 162 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), 163 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), 164 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), 165 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), 166 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), 167 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), 168 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), 169 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), 170 171 /* PE GPIO */ 172 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), 173 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), 174 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT), 175 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT), 176 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT), 177 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT), 178 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT), 179 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT), 180 181 /* PF GPIO */ 182 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), 183 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), 184 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), 185 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), 186 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), 187 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), 188 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), 189 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), 190 191 /* PG GPIO */ 192 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), 193 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), 194 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), 195 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT), 196 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT), 197 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT), 198 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT), 199 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT), 200 201 /* PH GPIO */ 202 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), 203 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), 204 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), 205 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), 206 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), 207 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), 208 209 /* PA FN */ 210 PINMUX_DATA(D31_MARK, PA7_FN), 211 PINMUX_DATA(D30_MARK, PA6_FN), 212 PINMUX_DATA(D29_MARK, PA5_FN), 213 PINMUX_DATA(D28_MARK, PA4_FN), 214 PINMUX_DATA(D27_MARK, PA3_FN), 215 PINMUX_DATA(D26_MARK, PA2_FN), 216 PINMUX_DATA(D25_MARK, PA1_FN), 217 PINMUX_DATA(D24_MARK, PA0_FN), 218 219 /* PB FN */ 220 PINMUX_DATA(D23_MARK, PB7_FN), 221 PINMUX_DATA(D22_MARK, PB6_FN), 222 PINMUX_DATA(D21_MARK, PB5_FN), 223 PINMUX_DATA(D20_MARK, PB4_FN), 224 PINMUX_DATA(D19_MARK, PB3_FN), 225 PINMUX_DATA(D18_MARK, PB2_FN), 226 PINMUX_DATA(D17_MARK, PB1_FN), 227 PINMUX_DATA(D16_MARK, PB0_FN), 228 229 /* PC FN */ 230 PINMUX_DATA(BACK_MARK, PC7_FN), 231 PINMUX_DATA(BREQ_MARK, PC6_FN), 232 PINMUX_DATA(WE3_MARK, PC5_FN), 233 PINMUX_DATA(WE2_MARK, PC4_FN), 234 PINMUX_DATA(CS6_MARK, PC3_FN), 235 PINMUX_DATA(CS5_MARK, PC2_FN), 236 PINMUX_DATA(CS4_MARK, PC1_FN), 237 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN), 238 239 /* PD FN */ 240 PINMUX_DATA(DACK3_MARK, PD7_FN), 241 PINMUX_DATA(DACK2_MARK, PD6_FN), 242 PINMUX_DATA(DACK1_MARK, PD5_FN), 243 PINMUX_DATA(DACK0_MARK, PD4_FN), 244 PINMUX_DATA(DREQ3_MARK, PD3_FN), 245 PINMUX_DATA(DREQ2_MARK, PD2_FN), 246 PINMUX_DATA(DREQ1_MARK, PD1_FN), 247 PINMUX_DATA(DREQ0_MARK, PD0_FN), 248 249 /* PE FN */ 250 PINMUX_DATA(IRQ3_MARK, PE7_FN), 251 PINMUX_DATA(IRQ2_MARK, PE6_FN), 252 PINMUX_DATA(IRQ1_MARK, PE5_FN), 253 PINMUX_DATA(IRQ0_MARK, PE4_FN), 254 PINMUX_DATA(DRAK3_MARK, PE3_FN), 255 PINMUX_DATA(DRAK2_MARK, PE2_FN), 256 PINMUX_DATA(DRAK1_MARK, PE1_FN), 257 PINMUX_DATA(DRAK0_MARK, PE0_FN), 258 259 /* PF FN */ 260 PINMUX_DATA(SCK3_MARK, PF7_FN), 261 PINMUX_DATA(SCK2_MARK, PF6_FN), 262 PINMUX_DATA(SCK1_MARK, PF5_FN), 263 PINMUX_DATA(SCK0_MARK, PF4_FN), 264 PINMUX_DATA(IRL3_MARK, PF3_FN), 265 PINMUX_DATA(IRL2_MARK, PF2_FN), 266 PINMUX_DATA(IRL1_MARK, PF1_FN), 267 PINMUX_DATA(IRL0_MARK, PF0_FN), 268 269 /* PG FN */ 270 PINMUX_DATA(TXD3_MARK, PG7_FN), 271 PINMUX_DATA(TXD2_MARK, PG6_FN), 272 PINMUX_DATA(TXD1_MARK, PG5_FN), 273 PINMUX_DATA(TXD0_MARK, PG4_FN), 274 PINMUX_DATA(RXD3_MARK, PG3_FN), 275 PINMUX_DATA(RXD2_MARK, PG2_FN), 276 PINMUX_DATA(RXD1_MARK, PG1_FN), 277 PINMUX_DATA(RXD0_MARK, PG0_FN), 278 279 /* PH FN */ 280 PINMUX_DATA(CE2B_MARK, PH5_FN), 281 PINMUX_DATA(CE2A_MARK, PH4_FN), 282 PINMUX_DATA(IOIS16_MARK, PH3_FN), 283 PINMUX_DATA(STATUS1_MARK, PH2_FN), 284 PINMUX_DATA(STATUS0_MARK, PH1_FN), 285 PINMUX_DATA(IRQOUT_MARK, PH0_FN), 286 }; 287 288 static const struct sh_pfc_pin pinmux_pins[] = { 289 /* PA */ 290 PINMUX_GPIO(PA7), 291 PINMUX_GPIO(PA6), 292 PINMUX_GPIO(PA5), 293 PINMUX_GPIO(PA4), 294 PINMUX_GPIO(PA3), 295 PINMUX_GPIO(PA2), 296 PINMUX_GPIO(PA1), 297 PINMUX_GPIO(PA0), 298 299 /* PB */ 300 PINMUX_GPIO(PB7), 301 PINMUX_GPIO(PB6), 302 PINMUX_GPIO(PB5), 303 PINMUX_GPIO(PB4), 304 PINMUX_GPIO(PB3), 305 PINMUX_GPIO(PB2), 306 PINMUX_GPIO(PB1), 307 PINMUX_GPIO(PB0), 308 309 /* PC */ 310 PINMUX_GPIO(PC7), 311 PINMUX_GPIO(PC6), 312 PINMUX_GPIO(PC5), 313 PINMUX_GPIO(PC4), 314 PINMUX_GPIO(PC3), 315 PINMUX_GPIO(PC2), 316 PINMUX_GPIO(PC1), 317 PINMUX_GPIO(PC0), 318 319 /* PD */ 320 PINMUX_GPIO(PD7), 321 PINMUX_GPIO(PD6), 322 PINMUX_GPIO(PD5), 323 PINMUX_GPIO(PD4), 324 PINMUX_GPIO(PD3), 325 PINMUX_GPIO(PD2), 326 PINMUX_GPIO(PD1), 327 PINMUX_GPIO(PD0), 328 329 /* PE */ 330 PINMUX_GPIO(PE7), 331 PINMUX_GPIO(PE6), 332 PINMUX_GPIO(PE5), 333 PINMUX_GPIO(PE4), 334 PINMUX_GPIO(PE3), 335 PINMUX_GPIO(PE2), 336 PINMUX_GPIO(PE1), 337 PINMUX_GPIO(PE0), 338 339 /* PF */ 340 PINMUX_GPIO(PF7), 341 PINMUX_GPIO(PF6), 342 PINMUX_GPIO(PF5), 343 PINMUX_GPIO(PF4), 344 PINMUX_GPIO(PF3), 345 PINMUX_GPIO(PF2), 346 PINMUX_GPIO(PF1), 347 PINMUX_GPIO(PF0), 348 349 /* PG */ 350 PINMUX_GPIO(PG7), 351 PINMUX_GPIO(PG6), 352 PINMUX_GPIO(PG5), 353 PINMUX_GPIO(PG4), 354 PINMUX_GPIO(PG3), 355 PINMUX_GPIO(PG2), 356 PINMUX_GPIO(PG1), 357 PINMUX_GPIO(PG0), 358 359 /* PH */ 360 PINMUX_GPIO(PH5), 361 PINMUX_GPIO(PH4), 362 PINMUX_GPIO(PH3), 363 PINMUX_GPIO(PH2), 364 PINMUX_GPIO(PH1), 365 PINMUX_GPIO(PH0), 366 }; 367 368 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 369 370 static const struct pinmux_func pinmux_func_gpios[] = { 371 /* FN */ 372 GPIO_FN(D31), 373 GPIO_FN(D30), 374 GPIO_FN(D29), 375 GPIO_FN(D28), 376 GPIO_FN(D27), 377 GPIO_FN(D26), 378 GPIO_FN(D25), 379 GPIO_FN(D24), 380 GPIO_FN(D23), 381 GPIO_FN(D22), 382 GPIO_FN(D21), 383 GPIO_FN(D20), 384 GPIO_FN(D19), 385 GPIO_FN(D18), 386 GPIO_FN(D17), 387 GPIO_FN(D16), 388 GPIO_FN(BACK), 389 GPIO_FN(BREQ), 390 GPIO_FN(WE3), 391 GPIO_FN(WE2), 392 GPIO_FN(CS6), 393 GPIO_FN(CS5), 394 GPIO_FN(CS4), 395 GPIO_FN(CLKOUTENB), 396 GPIO_FN(DACK3), 397 GPIO_FN(DACK2), 398 GPIO_FN(DACK1), 399 GPIO_FN(DACK0), 400 GPIO_FN(DREQ3), 401 GPIO_FN(DREQ2), 402 GPIO_FN(DREQ1), 403 GPIO_FN(DREQ0), 404 GPIO_FN(IRQ3), 405 GPIO_FN(IRQ2), 406 GPIO_FN(IRQ1), 407 GPIO_FN(IRQ0), 408 GPIO_FN(DRAK3), 409 GPIO_FN(DRAK2), 410 GPIO_FN(DRAK1), 411 GPIO_FN(DRAK0), 412 GPIO_FN(SCK3), 413 GPIO_FN(SCK2), 414 GPIO_FN(SCK1), 415 GPIO_FN(SCK0), 416 GPIO_FN(IRL3), 417 GPIO_FN(IRL2), 418 GPIO_FN(IRL1), 419 GPIO_FN(IRL0), 420 GPIO_FN(TXD3), 421 GPIO_FN(TXD2), 422 GPIO_FN(TXD1), 423 GPIO_FN(TXD0), 424 GPIO_FN(RXD3), 425 GPIO_FN(RXD2), 426 GPIO_FN(RXD1), 427 GPIO_FN(RXD0), 428 GPIO_FN(CE2B), 429 GPIO_FN(CE2A), 430 GPIO_FN(IOIS16), 431 GPIO_FN(STATUS1), 432 GPIO_FN(STATUS0), 433 GPIO_FN(IRQOUT), 434 }; 435 436 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 437 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { 438 PA7_FN, PA7_OUT, PA7_IN, 0, 439 PA6_FN, PA6_OUT, PA6_IN, 0, 440 PA5_FN, PA5_OUT, PA5_IN, 0, 441 PA4_FN, PA4_OUT, PA4_IN, 0, 442 PA3_FN, PA3_OUT, PA3_IN, 0, 443 PA2_FN, PA2_OUT, PA2_IN, 0, 444 PA1_FN, PA1_OUT, PA1_IN, 0, 445 PA0_FN, PA0_OUT, PA0_IN, 0, 446 PB7_FN, PB7_OUT, PB7_IN, 0, 447 PB6_FN, PB6_OUT, PB6_IN, 0, 448 PB5_FN, PB5_OUT, PB5_IN, 0, 449 PB4_FN, PB4_OUT, PB4_IN, 0, 450 PB3_FN, PB3_OUT, PB3_IN, 0, 451 PB2_FN, PB2_OUT, PB2_IN, 0, 452 PB1_FN, PB1_OUT, PB1_IN, 0, 453 PB0_FN, PB0_OUT, PB0_IN, 0, }, 454 }, 455 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) { 456 PC7_FN, PC7_OUT, PC7_IN, 0, 457 PC6_FN, PC6_OUT, PC6_IN, 0, 458 PC5_FN, PC5_OUT, PC5_IN, 0, 459 PC4_FN, PC4_OUT, PC4_IN, 0, 460 PC3_FN, PC3_OUT, PC3_IN, 0, 461 PC2_FN, PC2_OUT, PC2_IN, 0, 462 PC1_FN, PC1_OUT, PC1_IN, 0, 463 PC0_FN, PC0_OUT, PC0_IN, 0, 464 PD7_FN, PD7_OUT, PD7_IN, 0, 465 PD6_FN, PD6_OUT, PD6_IN, 0, 466 PD5_FN, PD5_OUT, PD5_IN, 0, 467 PD4_FN, PD4_OUT, PD4_IN, 0, 468 PD3_FN, PD3_OUT, PD3_IN, 0, 469 PD2_FN, PD2_OUT, PD2_IN, 0, 470 PD1_FN, PD1_OUT, PD1_IN, 0, 471 PD0_FN, PD0_OUT, PD0_IN, 0, }, 472 }, 473 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) { 474 PE7_FN, PE7_OUT, PE7_IN, 0, 475 PE6_FN, PE6_OUT, PE6_IN, 0, 476 PE5_FN, PE5_OUT, PE5_IN, 0, 477 PE4_FN, PE4_OUT, PE4_IN, 0, 478 PE3_FN, PE3_OUT, PE3_IN, 0, 479 PE2_FN, PE2_OUT, PE2_IN, 0, 480 PE1_FN, PE1_OUT, PE1_IN, 0, 481 PE0_FN, PE0_OUT, PE0_IN, 0, 482 PF7_FN, PF7_OUT, PF7_IN, 0, 483 PF6_FN, PF6_OUT, PF6_IN, 0, 484 PF5_FN, PF5_OUT, PF5_IN, 0, 485 PF4_FN, PF4_OUT, PF4_IN, 0, 486 PF3_FN, PF3_OUT, PF3_IN, 0, 487 PF2_FN, PF2_OUT, PF2_IN, 0, 488 PF1_FN, PF1_OUT, PF1_IN, 0, 489 PF0_FN, PF0_OUT, PF0_IN, 0, }, 490 }, 491 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) { 492 PG7_FN, PG7_OUT, PG7_IN, 0, 493 PG6_FN, PG6_OUT, PG6_IN, 0, 494 PG5_FN, PG5_OUT, PG5_IN, 0, 495 PG4_FN, PG4_OUT, PG4_IN, 0, 496 PG3_FN, PG3_OUT, PG3_IN, 0, 497 PG2_FN, PG2_OUT, PG2_IN, 0, 498 PG1_FN, PG1_OUT, PG1_IN, 0, 499 PG0_FN, PG0_OUT, PG0_IN, 0, 500 0, 0, 0, 0, 501 0, 0, 0, 0, 502 PH5_FN, PH5_OUT, PH5_IN, 0, 503 PH4_FN, PH4_OUT, PH4_IN, 0, 504 PH3_FN, PH3_OUT, PH3_IN, 0, 505 PH2_FN, PH2_OUT, PH2_IN, 0, 506 PH1_FN, PH1_OUT, PH1_IN, 0, 507 PH0_FN, PH0_OUT, PH0_IN, 0, }, 508 }, 509 { }, 510 }; 511 512 static const struct pinmux_data_reg pinmux_data_regs[] = { 513 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 514 0, 0, 0, 0, 0, 0, 0, 0, 515 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 516 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 517 0, 0, 0, 0, 0, 0, 0, 0, 518 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 519 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, }, 520 }, 521 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) { 522 0, 0, 0, 0, 0, 0, 0, 0, 523 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 524 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 525 0, 0, 0, 0, 0, 0, 0, 0, 526 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 527 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, }, 528 }, 529 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) { 530 0, 0, 0, 0, 0, 0, 0, 0, 531 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 532 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, 533 0, 0, 0, 0, 0, 0, 0, 0, 534 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 535 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, }, 536 }, 537 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) { 538 0, 0, 0, 0, 0, 0, 0, 0, 539 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 540 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, 541 0, 0, 0, 0, 0, 0, 0, 0, 542 0, 0, PH5_DATA, PH4_DATA, 543 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, }, 544 }, 545 { }, 546 }; 547 548 const struct sh_pfc_soc_info shx3_pinmux_info = { 549 .name = "shx3_pfc", 550 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 551 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 552 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 553 .pins = pinmux_pins, 554 .nr_pins = ARRAY_SIZE(pinmux_pins), 555 .func_gpios = pinmux_func_gpios, 556 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 557 .pinmux_data = pinmux_data, 558 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 559 .cfg_regs = pinmux_config_regs, 560 .data_regs = pinmux_data_regs, 561 }; 562