1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_TYPE_H_ 30 #define _IXGBE_TYPE_H_ 31 32 #include <linux/types.h> 33 #include <linux/mdio.h> 34 #include <linux/netdevice.h> 35 36 /* Device IDs */ 37 #define IXGBE_DEV_ID_82598 0x10B6 38 #define IXGBE_DEV_ID_82598_BX 0x1508 39 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 40 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 41 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 42 #define IXGBE_DEV_ID_82598AT 0x10C8 43 #define IXGBE_DEV_ID_82598AT2 0x150B 44 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD 45 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 46 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 47 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 48 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 49 #define IXGBE_DEV_ID_82599_KX4 0x10F7 50 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 51 #define IXGBE_DEV_ID_82599_KR 0x1517 52 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C 53 #define IXGBE_DEV_ID_82599_CX4 0x10F9 54 #define IXGBE_DEV_ID_82599_SFP 0x10FB 55 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a 56 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 57 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 58 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 59 #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 60 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 61 #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 62 #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 63 #define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976 64 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 65 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 66 #define IXGBE_DEV_ID_82599EN_SFP 0x1557 67 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 68 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 69 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 70 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 71 #define IXGBE_DEV_ID_82599_LS 0x154F 72 #define IXGBE_DEV_ID_X540T 0x1528 73 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 74 #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 75 #define IXGBE_DEV_ID_X540T1 0x1560 76 77 #define IXGBE_DEV_ID_X550T 0x1563 78 #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA 79 #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB 80 #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC 81 #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD 82 #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE 83 #define IXGBE_DEV_ID_X550_VF_HV 0x1564 84 #define IXGBE_DEV_ID_X550_VF 0x1565 85 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 86 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 87 88 /* VF Device IDs */ 89 #define IXGBE_DEV_ID_82599_VF 0x10ED 90 #define IXGBE_DEV_ID_X540_VF 0x1515 91 #define IXGBE_DEV_ID_X550_VF 0x1565 92 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 93 94 /* General Registers */ 95 #define IXGBE_CTRL 0x00000 96 #define IXGBE_STATUS 0x00008 97 #define IXGBE_CTRL_EXT 0x00018 98 #define IXGBE_ESDP 0x00020 99 #define IXGBE_EODSDP 0x00028 100 #define IXGBE_I2CCTL_BY_MAC(_hw)((((_hw)->mac.type >= ixgbe_mac_X550) ? \ 101 0x15F5C : 0x00028)) 102 #define IXGBE_LEDCTL 0x00200 103 #define IXGBE_FRTIMER 0x00048 104 #define IXGBE_TCPTIMER 0x0004C 105 #define IXGBE_CORESPARE 0x00600 106 #define IXGBE_EXVET 0x05078 107 108 /* NVM Registers */ 109 #define IXGBE_EEC 0x10010 110 #define IXGBE_EERD 0x10014 111 #define IXGBE_EEWR 0x10018 112 #define IXGBE_FLA 0x1001C 113 #define IXGBE_EEMNGCTL 0x10110 114 #define IXGBE_EEMNGDATA 0x10114 115 #define IXGBE_FLMNGCTL 0x10118 116 #define IXGBE_FLMNGDATA 0x1011C 117 #define IXGBE_FLMNGCNT 0x10120 118 #define IXGBE_FLOP 0x1013C 119 #define IXGBE_GRC 0x10200 120 121 /* General Receive Control */ 122 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 123 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 124 125 #define IXGBE_VPDDIAG0 0x10204 126 #define IXGBE_VPDDIAG1 0x10208 127 128 /* I2CCTL Bit Masks */ 129 #define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \ 130 0x00004000 : 0x00000001) 131 #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \ 132 0x00000200 : 0x00000002) 133 #define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \ 134 0x00001000 : 0x00000004) 135 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \ 136 0x00000400 : 0x00000008) 137 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 138 139 #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 140 #define IXGBE_EMC_INTERNAL_DATA 0x00 141 #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 142 #define IXGBE_EMC_DIODE1_DATA 0x01 143 #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 144 #define IXGBE_EMC_DIODE2_DATA 0x23 145 #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A 146 147 #define IXGBE_MAX_SENSORS 3 148 149 struct ixgbe_thermal_diode_data { 150 u8 location; 151 u8 temp; 152 u8 caution_thresh; 153 u8 max_op_thresh; 154 }; 155 156 struct ixgbe_thermal_sensor_data { 157 struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS]; 158 }; 159 160 /* Interrupt Registers */ 161 #define IXGBE_EICR 0x00800 162 #define IXGBE_EICS 0x00808 163 #define IXGBE_EIMS 0x00880 164 #define IXGBE_EIMC 0x00888 165 #define IXGBE_EIAC 0x00810 166 #define IXGBE_EIAM 0x00890 167 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 168 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 169 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 170 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 171 /* 172 * 82598 EITR is 16 bits but set the limits based on the max 173 * supported by all ixgbe hardware. 82599 EITR is only 12 bits, 174 * with the lower 3 always zero. 175 */ 176 #define IXGBE_MAX_INT_RATE 488281 177 #define IXGBE_MIN_INT_RATE 956 178 #define IXGBE_MAX_EITR 0x00000FF8 179 #define IXGBE_MIN_EITR 8 180 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 181 (0x012300 + (((_i) - 24) * 4))) 182 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 183 #define IXGBE_EITR_LLI_MOD 0x00008000 184 #define IXGBE_EITR_CNT_WDIS 0x80000000 185 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 186 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 187 #define IXGBE_EITRSEL 0x00894 188 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 189 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 190 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 191 #define IXGBE_GPIE 0x00898 192 193 /* Flow Control Registers */ 194 #define IXGBE_FCADBUL 0x03210 195 #define IXGBE_FCADBUH 0x03214 196 #define IXGBE_FCAMACL 0x04328 197 #define IXGBE_FCAMACH 0x0432C 198 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 199 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 200 #define IXGBE_PFCTOP 0x03008 201 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 202 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 203 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 204 #define IXGBE_FCRTV 0x032A0 205 #define IXGBE_FCCFG 0x03D00 206 #define IXGBE_TFCS 0x0CE00 207 208 /* Receive DMA Registers */ 209 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 210 (0x0D000 + (((_i) - 64) * 0x40))) 211 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 212 (0x0D004 + (((_i) - 64) * 0x40))) 213 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 214 (0x0D008 + (((_i) - 64) * 0x40))) 215 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 216 (0x0D010 + (((_i) - 64) * 0x40))) 217 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 218 (0x0D018 + (((_i) - 64) * 0x40))) 219 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 220 (0x0D028 + (((_i) - 64) * 0x40))) 221 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 222 (0x0D02C + (((_i) - 64) * 0x40))) 223 #define IXGBE_RSCDBU 0x03028 224 #define IXGBE_RDDCC 0x02F20 225 #define IXGBE_RXMEMWRAP 0x03190 226 #define IXGBE_STARCTRL 0x03024 227 /* 228 * Split and Replication Receive Control Registers 229 * 00-15 : 0x02100 + n*4 230 * 16-64 : 0x01014 + n*0x40 231 * 64-127: 0x0D014 + (n-64)*0x40 232 */ 233 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 234 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 235 (0x0D014 + (((_i) - 64) * 0x40)))) 236 /* 237 * Rx DCA Control Register: 238 * 00-15 : 0x02200 + n*4 239 * 16-64 : 0x0100C + n*0x40 240 * 64-127: 0x0D00C + (n-64)*0x40 241 */ 242 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 243 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 244 (0x0D00C + (((_i) - 64) * 0x40)))) 245 #define IXGBE_RDRXCTL 0x02F00 246 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 247 /* 8 of these 0x03C00 - 0x03C1C */ 248 #define IXGBE_RXCTRL 0x03000 249 #define IXGBE_DROPEN 0x03D04 250 #define IXGBE_RXPBSIZE_SHIFT 10 251 252 /* Receive Registers */ 253 #define IXGBE_RXCSUM 0x05000 254 #define IXGBE_RFCTL 0x05008 255 #define IXGBE_DRECCCTL 0x02F08 256 #define IXGBE_DRECCCTL_DISABLE 0 257 /* Multicast Table Array - 128 entries */ 258 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 259 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 260 (0x0A200 + ((_i) * 8))) 261 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 262 (0x0A204 + ((_i) * 8))) 263 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 264 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 265 /* Packet split receive type */ 266 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 267 (0x0EA00 + ((_i) * 4))) 268 /* array of 4096 1-bit vlan filters */ 269 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 270 /*array of 4096 4-bit vlan vmdq indices */ 271 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 272 #define IXGBE_FCTRL 0x05080 273 #define IXGBE_VLNCTRL 0x05088 274 #define IXGBE_MCSTCTRL 0x05090 275 #define IXGBE_MRQC 0x05818 276 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 277 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 278 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 279 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 280 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 281 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 282 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 283 #define IXGBE_RQTC 0x0EC70 284 #define IXGBE_MTQC 0x08120 285 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 286 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 287 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 288 #define IXGBE_PFFLPL 0x050B0 289 #define IXGBE_PFFLPH 0x050B4 290 #define IXGBE_VT_CTL 0x051B0 291 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 292 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ 293 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 294 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 295 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 296 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 297 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 298 #define IXGBE_QDE 0x2F04 299 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 300 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 301 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 302 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 303 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 304 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 305 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 306 #define IXGBE_RXFECCERR0 0x051B8 307 #define IXGBE_LLITHRESH 0x0EC90 308 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 309 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 310 #define IXGBE_IMIRVP 0x05AC0 311 #define IXGBE_VMD_CTL 0x0581C 312 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 313 #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ 314 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 315 316 /* Registers for setting up RSS on X550 with SRIOV 317 * _p - pool number (0..63) 318 * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) 319 */ 320 #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) 321 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) 322 #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) 323 324 /* Flow Director registers */ 325 #define IXGBE_FDIRCTRL 0x0EE00 326 #define IXGBE_FDIRHKEY 0x0EE68 327 #define IXGBE_FDIRSKEY 0x0EE6C 328 #define IXGBE_FDIRDIP4M 0x0EE3C 329 #define IXGBE_FDIRSIP4M 0x0EE40 330 #define IXGBE_FDIRTCPM 0x0EE44 331 #define IXGBE_FDIRUDPM 0x0EE48 332 #define IXGBE_FDIRIP6M 0x0EE74 333 #define IXGBE_FDIRM 0x0EE70 334 335 /* Flow Director Stats registers */ 336 #define IXGBE_FDIRFREE 0x0EE38 337 #define IXGBE_FDIRLEN 0x0EE4C 338 #define IXGBE_FDIRUSTAT 0x0EE50 339 #define IXGBE_FDIRFSTAT 0x0EE54 340 #define IXGBE_FDIRMATCH 0x0EE58 341 #define IXGBE_FDIRMISS 0x0EE5C 342 343 /* Flow Director Programming registers */ 344 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 345 #define IXGBE_FDIRIPSA 0x0EE18 346 #define IXGBE_FDIRIPDA 0x0EE1C 347 #define IXGBE_FDIRPORT 0x0EE20 348 #define IXGBE_FDIRVLAN 0x0EE24 349 #define IXGBE_FDIRHASH 0x0EE28 350 #define IXGBE_FDIRCMD 0x0EE2C 351 352 /* Transmit DMA registers */ 353 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 354 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 355 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 356 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 357 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 358 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 359 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 360 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 361 #define IXGBE_DTXCTL 0x07E00 362 363 #define IXGBE_DMATXCTL 0x04A80 364 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 365 #define IXGBE_PFDTXGSWC 0x08220 366 #define IXGBE_DTXMXSZRQ 0x08100 367 #define IXGBE_DTXTCPFLGL 0x04A88 368 #define IXGBE_DTXTCPFLGH 0x04A8C 369 #define IXGBE_LBDRPEN 0x0CA00 370 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 371 372 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 373 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 374 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 375 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 376 377 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 378 379 /* Anti-spoofing defines */ 380 #define IXGBE_SPOOF_MACAS_MASK 0xFF 381 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 382 #define IXGBE_SPOOF_VLANAS_SHIFT 8 383 #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 384 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 385 #define IXGBE_PFVFSPOOF_REG_COUNT 8 386 387 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 388 /* Tx DCA Control register : 128 of these (0-127) */ 389 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 390 #define IXGBE_TIPG 0x0CB00 391 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 392 #define IXGBE_MNGTXMAP 0x0CD10 393 #define IXGBE_TIPG_FIBER_DEFAULT 3 394 #define IXGBE_TXPBSIZE_SHIFT 10 395 396 /* Wake up registers */ 397 #define IXGBE_WUC 0x05800 398 #define IXGBE_WUFC 0x05808 399 #define IXGBE_WUS 0x05810 400 #define IXGBE_IPAV 0x05838 401 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 402 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 403 404 #define IXGBE_WUPL 0x05900 405 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 406 #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ 407 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 408 #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host 409 * Filter Table */ 410 411 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 412 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 413 414 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 415 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 416 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 417 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 418 419 /* Definitions for power management and wakeup registers */ 420 /* Wake Up Control */ 421 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 422 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 423 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 424 425 /* Wake Up Filter Control */ 426 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 427 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 428 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 429 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 430 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 431 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 432 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 433 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 434 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 435 436 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 437 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 438 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 439 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 440 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 441 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 442 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 443 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 444 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ 445 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ 446 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 447 448 /* Wake Up Status */ 449 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 450 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG 451 #define IXGBE_WUS_EX IXGBE_WUFC_EX 452 #define IXGBE_WUS_MC IXGBE_WUFC_MC 453 #define IXGBE_WUS_BC IXGBE_WUFC_BC 454 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP 455 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 456 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 457 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG 458 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 459 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 460 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 461 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 462 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 463 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 464 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 465 466 /* Wake Up Packet Length */ 467 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF 468 469 /* DCB registers */ 470 #define MAX_TRAFFIC_CLASS 8 471 #define X540_TRAFFIC_CLASS 4 472 #define IXGBE_RMCS 0x03D00 473 #define IXGBE_DPMCS 0x07F40 474 #define IXGBE_PDPMCS 0x0CD00 475 #define IXGBE_RUPPBMR 0x050A0 476 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 477 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 478 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 479 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 480 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 481 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 482 483 484 /* Security Control Registers */ 485 #define IXGBE_SECTXCTRL 0x08800 486 #define IXGBE_SECTXSTAT 0x08804 487 #define IXGBE_SECTXBUFFAF 0x08808 488 #define IXGBE_SECTXMINIFG 0x08810 489 #define IXGBE_SECRXCTRL 0x08D00 490 #define IXGBE_SECRXSTAT 0x08D04 491 492 /* Security Bit Fields and Masks */ 493 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 494 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 495 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 496 497 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 498 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 499 500 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 501 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 502 503 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 504 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 505 506 /* LinkSec (MacSec) Registers */ 507 #define IXGBE_LSECTXCAP 0x08A00 508 #define IXGBE_LSECRXCAP 0x08F00 509 #define IXGBE_LSECTXCTRL 0x08A04 510 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 511 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 512 #define IXGBE_LSECTXSA 0x08A10 513 #define IXGBE_LSECTXPN0 0x08A14 514 #define IXGBE_LSECTXPN1 0x08A18 515 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 516 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 517 #define IXGBE_LSECRXCTRL 0x08F04 518 #define IXGBE_LSECRXSCL 0x08F08 519 #define IXGBE_LSECRXSCH 0x08F0C 520 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 521 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 522 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 523 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 524 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 525 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 526 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 527 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 528 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 529 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 530 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 531 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 532 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 533 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 534 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 535 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 536 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 537 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 538 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 539 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 540 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 541 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 542 543 /* LinkSec (MacSec) Bit Fields and Masks */ 544 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 545 #define IXGBE_LSECTXCAP_SUM_SHIFT 16 546 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 547 #define IXGBE_LSECRXCAP_SUM_SHIFT 16 548 549 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 550 #define IXGBE_LSECTXCTRL_DISABLE 0x0 551 #define IXGBE_LSECTXCTRL_AUTH 0x1 552 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 553 #define IXGBE_LSECTXCTRL_AISCI 0x00000020 554 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 555 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 556 557 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 558 #define IXGBE_LSECRXCTRL_EN_SHIFT 2 559 #define IXGBE_LSECRXCTRL_DISABLE 0x0 560 #define IXGBE_LSECRXCTRL_CHECK 0x1 561 #define IXGBE_LSECRXCTRL_STRICT 0x2 562 #define IXGBE_LSECRXCTRL_DROP 0x3 563 #define IXGBE_LSECRXCTRL_PLSH 0x00000040 564 #define IXGBE_LSECRXCTRL_RP 0x00000080 565 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 566 567 /* IpSec Registers */ 568 #define IXGBE_IPSTXIDX 0x08900 569 #define IXGBE_IPSTXSALT 0x08904 570 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 571 #define IXGBE_IPSRXIDX 0x08E00 572 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 573 #define IXGBE_IPSRXSPI 0x08E14 574 #define IXGBE_IPSRXIPIDX 0x08E18 575 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 576 #define IXGBE_IPSRXSALT 0x08E2C 577 #define IXGBE_IPSRXMOD 0x08E30 578 579 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 580 581 /* DCB registers */ 582 #define IXGBE_RTRPCS 0x02430 583 #define IXGBE_RTTDCS 0x04900 584 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 585 #define IXGBE_RTTPCS 0x0CD00 586 #define IXGBE_RTRUP2TC 0x03020 587 #define IXGBE_RTTUP2TC 0x0C800 588 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 589 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 590 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 591 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 592 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 593 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 594 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 595 #define IXGBE_RTTDQSEL 0x04904 596 #define IXGBE_RTTDT1C 0x04908 597 #define IXGBE_RTTDT1S 0x0490C 598 #define IXGBE_RTTQCNCR 0x08B00 599 #define IXGBE_RTTQCNTG 0x04A90 600 #define IXGBE_RTTBCNRD 0x0498C 601 #define IXGBE_RTTQCNRR 0x0498C 602 #define IXGBE_RTTDTECC 0x04990 603 #define IXGBE_RTTDTECC_NO_BCN 0x00000100 604 #define IXGBE_RTTBCNRC 0x04984 605 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 606 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 607 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 608 #define IXGBE_RTTBCNRC_RF_INT_MASK \ 609 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 610 #define IXGBE_RTTBCNRM 0x04980 611 #define IXGBE_RTTQCNRM 0x04980 612 613 /* FCoE Direct DMA Context */ 614 #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) 615 /* FCoE DMA Context Registers */ 616 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 617 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 618 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 619 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 620 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ 621 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 622 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 623 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 624 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 625 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 626 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 627 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 628 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 629 #define IXGBE_FCBUFF_OFFSET_SHIFT 16 630 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 631 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 632 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 633 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 634 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 635 636 /* FCoE SOF/EOF */ 637 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 638 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 639 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 640 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 641 /* FCoE Direct Filter Context */ 642 #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) 643 #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) 644 /* FCoE Filter Context Registers */ 645 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 646 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 647 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 648 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 649 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 650 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 651 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 652 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 653 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 654 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 655 /* FCoE Receive Control */ 656 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 657 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 658 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 659 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 660 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 661 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 662 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 663 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 664 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 665 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 666 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 667 /* FCoE Redirection */ 668 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 669 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 670 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 671 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 672 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 673 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 674 #define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ 675 /* Higher 7 bits for the queue index */ 676 #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 677 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 678 679 /* Stats registers */ 680 #define IXGBE_CRCERRS 0x04000 681 #define IXGBE_ILLERRC 0x04004 682 #define IXGBE_ERRBC 0x04008 683 #define IXGBE_MSPDC 0x04010 684 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 685 #define IXGBE_MLFC 0x04034 686 #define IXGBE_MRFC 0x04038 687 #define IXGBE_RLEC 0x04040 688 #define IXGBE_LXONTXC 0x03F60 689 #define IXGBE_LXONRXC 0x0CF60 690 #define IXGBE_LXOFFTXC 0x03F68 691 #define IXGBE_LXOFFRXC 0x0CF68 692 #define IXGBE_LXONRXCNT 0x041A4 693 #define IXGBE_LXOFFRXCNT 0x041A8 694 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 695 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 696 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 697 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 698 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 699 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 700 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 701 #define IXGBE_PRC64 0x0405C 702 #define IXGBE_PRC127 0x04060 703 #define IXGBE_PRC255 0x04064 704 #define IXGBE_PRC511 0x04068 705 #define IXGBE_PRC1023 0x0406C 706 #define IXGBE_PRC1522 0x04070 707 #define IXGBE_GPRC 0x04074 708 #define IXGBE_BPRC 0x04078 709 #define IXGBE_MPRC 0x0407C 710 #define IXGBE_GPTC 0x04080 711 #define IXGBE_GORCL 0x04088 712 #define IXGBE_GORCH 0x0408C 713 #define IXGBE_GOTCL 0x04090 714 #define IXGBE_GOTCH 0x04094 715 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 716 #define IXGBE_RUC 0x040A4 717 #define IXGBE_RFC 0x040A8 718 #define IXGBE_ROC 0x040AC 719 #define IXGBE_RJC 0x040B0 720 #define IXGBE_MNGPRC 0x040B4 721 #define IXGBE_MNGPDC 0x040B8 722 #define IXGBE_MNGPTC 0x0CF90 723 #define IXGBE_TORL 0x040C0 724 #define IXGBE_TORH 0x040C4 725 #define IXGBE_TPR 0x040D0 726 #define IXGBE_TPT 0x040D4 727 #define IXGBE_PTC64 0x040D8 728 #define IXGBE_PTC127 0x040DC 729 #define IXGBE_PTC255 0x040E0 730 #define IXGBE_PTC511 0x040E4 731 #define IXGBE_PTC1023 0x040E8 732 #define IXGBE_PTC1522 0x040EC 733 #define IXGBE_MPTC 0x040F0 734 #define IXGBE_BPTC 0x040F4 735 #define IXGBE_XEC 0x04120 736 #define IXGBE_SSVPC 0x08780 737 738 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 739 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 740 (0x08600 + ((_i) * 4))) 741 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 742 743 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 744 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 745 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 746 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 747 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 748 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 749 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 750 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 751 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 752 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ 753 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 754 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 755 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 756 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 757 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 758 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 759 #define IXGBE_O2BGPTC 0x041C4 760 #define IXGBE_O2BSPC 0x087B0 761 #define IXGBE_B2OSPC 0x041C0 762 #define IXGBE_B2OGPRC 0x02F90 763 #define IXGBE_PCRC8ECL 0x0E810 764 #define IXGBE_PCRC8ECH 0x0E811 765 #define IXGBE_PCRC8ECH_MASK 0x1F 766 #define IXGBE_LDPCECL 0x0E820 767 #define IXGBE_LDPCECH 0x0E821 768 769 /* MII clause 22/28 definitions */ 770 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 771 772 #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register */ 773 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ 774 775 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ 776 777 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ 778 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ 779 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ 780 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */ 781 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */ 782 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ 783 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ 784 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ 785 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ 786 787 /* Management */ 788 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 789 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 790 #define IXGBE_MANC 0x05820 791 #define IXGBE_MFVAL 0x05824 792 #define IXGBE_MANC2H 0x05860 793 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 794 #define IXGBE_MIPAF 0x058B0 795 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 796 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 797 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 798 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 799 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 800 #define IXGBE_LSWFW 0x15014 801 802 /* Management Bit Fields and Masks */ 803 #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 804 805 /* Firmware Semaphore Register */ 806 #define IXGBE_FWSM_MODE_MASK 0xE 807 #define IXGBE_FWSM_FW_MODE_PT 0x4 808 809 /* ARC Subsystem registers */ 810 #define IXGBE_HICR 0x15F00 811 #define IXGBE_FWSTS 0x15F0C 812 #define IXGBE_HSMC0R 0x15F04 813 #define IXGBE_HSMC1R 0x15F08 814 #define IXGBE_SWSR 0x15F10 815 #define IXGBE_HFDR 0x15FE8 816 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 817 818 #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 819 /* Driver sets this bit when done to put command in RAM */ 820 #define IXGBE_HICR_C 0x02 821 #define IXGBE_HICR_SV 0x04 /* Status Validity */ 822 #define IXGBE_HICR_FW_RESET_ENABLE 0x40 823 #define IXGBE_HICR_FW_RESET 0x80 824 825 /* PCI-E registers */ 826 #define IXGBE_GCR 0x11000 827 #define IXGBE_GTV 0x11004 828 #define IXGBE_FUNCTAG 0x11008 829 #define IXGBE_GLT 0x1100C 830 #define IXGBE_GSCL_1 0x11010 831 #define IXGBE_GSCL_2 0x11014 832 #define IXGBE_GSCL_3 0x11018 833 #define IXGBE_GSCL_4 0x1101C 834 #define IXGBE_GSCN_0 0x11020 835 #define IXGBE_GSCN_1 0x11024 836 #define IXGBE_GSCN_2 0x11028 837 #define IXGBE_GSCN_3 0x1102C 838 #define IXGBE_FACTPS 0x10150 839 #define IXGBE_PCIEANACTL 0x11040 840 #define IXGBE_SWSM 0x10140 841 #define IXGBE_FWSM 0x10148 842 #define IXGBE_GSSR 0x10160 843 #define IXGBE_MREVID 0x11064 844 #define IXGBE_DCA_ID 0x11070 845 #define IXGBE_DCA_CTRL 0x11074 846 #define IXGBE_SWFW_SYNC IXGBE_GSSR 847 848 /* PCIe registers 82599-specific */ 849 #define IXGBE_GCR_EXT 0x11050 850 #define IXGBE_GSCL_5_82599 0x11030 851 #define IXGBE_GSCL_6_82599 0x11034 852 #define IXGBE_GSCL_7_82599 0x11038 853 #define IXGBE_GSCL_8_82599 0x1103C 854 #define IXGBE_PHYADR_82599 0x11040 855 #define IXGBE_PHYDAT_82599 0x11044 856 #define IXGBE_PHYCTL_82599 0x11048 857 #define IXGBE_PBACLR_82599 0x11068 858 #define IXGBE_CIAA_82599 0x11088 859 #define IXGBE_CIAD_82599 0x1108C 860 #define IXGBE_CIAA_X550 0x11508 861 #define IXGBE_CIAD_X550 0x11510 862 #define IXGBE_CIAA_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \ 863 IXGBE_CIAA_X550 : IXGBE_CIAA_82599)) 864 #define IXGBE_CIAD_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \ 865 IXGBE_CIAD_X550 : IXGBE_CIAD_82599)) 866 #define IXGBE_PICAUSE 0x110B0 867 #define IXGBE_PIENA 0x110B8 868 #define IXGBE_CDQ_MBR_82599 0x110B4 869 #define IXGBE_PCIESPARE 0x110BC 870 #define IXGBE_MISC_REG_82599 0x110F0 871 #define IXGBE_ECC_CTRL_0_82599 0x11100 872 #define IXGBE_ECC_CTRL_1_82599 0x11104 873 #define IXGBE_ECC_STATUS_82599 0x110E0 874 #define IXGBE_BAR_CTRL_82599 0x110F4 875 876 /* PCI Express Control */ 877 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 878 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 879 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 880 #define IXGBE_GCR_CAP_VER2 0x00040000 881 882 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 883 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 884 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 885 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 886 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 887 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 888 IXGBE_GCR_EXT_VT_MODE_64) 889 890 /* Time Sync Registers */ 891 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 892 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 893 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 894 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 895 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 896 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 897 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 898 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 899 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 900 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 901 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 902 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 903 #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 904 #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 905 #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 906 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 907 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 908 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 909 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 910 #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 911 #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 912 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 913 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 914 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 915 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 916 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 917 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 918 919 /* Diagnostic Registers */ 920 #define IXGBE_RDSTATCTL 0x02C20 921 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 922 #define IXGBE_RDHMPN 0x02F08 923 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 924 #define IXGBE_RDPROBE 0x02F20 925 #define IXGBE_RDMAM 0x02F30 926 #define IXGBE_RDMAD 0x02F34 927 #define IXGBE_TDSTATCTL 0x07C20 928 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 929 #define IXGBE_TDHMPN 0x07F08 930 #define IXGBE_TDHMPN2 0x082FC 931 #define IXGBE_TXDESCIC 0x082CC 932 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 933 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 934 #define IXGBE_TDPROBE 0x07F20 935 #define IXGBE_TXBUFCTRL 0x0C600 936 #define IXGBE_TXBUFDATA0 0x0C610 937 #define IXGBE_TXBUFDATA1 0x0C614 938 #define IXGBE_TXBUFDATA2 0x0C618 939 #define IXGBE_TXBUFDATA3 0x0C61C 940 #define IXGBE_RXBUFCTRL 0x03600 941 #define IXGBE_RXBUFDATA0 0x03610 942 #define IXGBE_RXBUFDATA1 0x03614 943 #define IXGBE_RXBUFDATA2 0x03618 944 #define IXGBE_RXBUFDATA3 0x0361C 945 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 946 #define IXGBE_RFVAL 0x050A4 947 #define IXGBE_MDFTC1 0x042B8 948 #define IXGBE_MDFTC2 0x042C0 949 #define IXGBE_MDFTFIFO1 0x042C4 950 #define IXGBE_MDFTFIFO2 0x042C8 951 #define IXGBE_MDFTS 0x042CC 952 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 953 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 954 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 955 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 956 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 957 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 958 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 959 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 960 #define IXGBE_PCIEECCCTL 0x1106C 961 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 962 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 963 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 964 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 965 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 966 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 967 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 968 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 969 #define IXGBE_PCIEECCCTL0 0x11100 970 #define IXGBE_PCIEECCCTL1 0x11104 971 #define IXGBE_RXDBUECC 0x03F70 972 #define IXGBE_TXDBUECC 0x0CF70 973 #define IXGBE_RXDBUEST 0x03F74 974 #define IXGBE_TXDBUEST 0x0CF74 975 #define IXGBE_PBTXECC 0x0C300 976 #define IXGBE_PBRXECC 0x03300 977 #define IXGBE_GHECCR 0x110B0 978 979 /* MAC Registers */ 980 #define IXGBE_PCS1GCFIG 0x04200 981 #define IXGBE_PCS1GLCTL 0x04208 982 #define IXGBE_PCS1GLSTA 0x0420C 983 #define IXGBE_PCS1GDBG0 0x04210 984 #define IXGBE_PCS1GDBG1 0x04214 985 #define IXGBE_PCS1GANA 0x04218 986 #define IXGBE_PCS1GANLP 0x0421C 987 #define IXGBE_PCS1GANNP 0x04220 988 #define IXGBE_PCS1GANLPNP 0x04224 989 #define IXGBE_HLREG0 0x04240 990 #define IXGBE_HLREG1 0x04244 991 #define IXGBE_PAP 0x04248 992 #define IXGBE_MACA 0x0424C 993 #define IXGBE_APAE 0x04250 994 #define IXGBE_ARD 0x04254 995 #define IXGBE_AIS 0x04258 996 #define IXGBE_MSCA 0x0425C 997 #define IXGBE_MSRWD 0x04260 998 #define IXGBE_MLADD 0x04264 999 #define IXGBE_MHADD 0x04268 1000 #define IXGBE_MAXFRS 0x04268 1001 #define IXGBE_TREG 0x0426C 1002 #define IXGBE_PCSS1 0x04288 1003 #define IXGBE_PCSS2 0x0428C 1004 #define IXGBE_XPCSS 0x04290 1005 #define IXGBE_MFLCN 0x04294 1006 #define IXGBE_SERDESC 0x04298 1007 #define IXGBE_MACS 0x0429C 1008 #define IXGBE_AUTOC 0x042A0 1009 #define IXGBE_LINKS 0x042A4 1010 #define IXGBE_LINKS2 0x04324 1011 #define IXGBE_AUTOC2 0x042A8 1012 #define IXGBE_AUTOC3 0x042AC 1013 #define IXGBE_ANLP1 0x042B0 1014 #define IXGBE_ANLP2 0x042B4 1015 #define IXGBE_MACC 0x04330 1016 #define IXGBE_ATLASCTL 0x04800 1017 #define IXGBE_MMNGC 0x042D0 1018 #define IXGBE_ANLPNP1 0x042D4 1019 #define IXGBE_ANLPNP2 0x042D8 1020 #define IXGBE_KRPCSFC 0x042E0 1021 #define IXGBE_KRPCSS 0x042E4 1022 #define IXGBE_FECS1 0x042E8 1023 #define IXGBE_FECS2 0x042EC 1024 #define IXGBE_SMADARCTL 0x14F10 1025 #define IXGBE_MPVC 0x04318 1026 #define IXGBE_SGMIIC 0x04314 1027 1028 /* Statistics Registers */ 1029 #define IXGBE_RXNFGPC 0x041B0 1030 #define IXGBE_RXNFGBCL 0x041B4 1031 #define IXGBE_RXNFGBCH 0x041B8 1032 #define IXGBE_RXDGPC 0x02F50 1033 #define IXGBE_RXDGBCL 0x02F54 1034 #define IXGBE_RXDGBCH 0x02F58 1035 #define IXGBE_RXDDGPC 0x02F5C 1036 #define IXGBE_RXDDGBCL 0x02F60 1037 #define IXGBE_RXDDGBCH 0x02F64 1038 #define IXGBE_RXLPBKGPC 0x02F68 1039 #define IXGBE_RXLPBKGBCL 0x02F6C 1040 #define IXGBE_RXLPBKGBCH 0x02F70 1041 #define IXGBE_RXDLPBKGPC 0x02F74 1042 #define IXGBE_RXDLPBKGBCL 0x02F78 1043 #define IXGBE_RXDLPBKGBCH 0x02F7C 1044 #define IXGBE_TXDGPC 0x087A0 1045 #define IXGBE_TXDGBCL 0x087A4 1046 #define IXGBE_TXDGBCH 0x087A8 1047 1048 #define IXGBE_RXDSTATCTRL 0x02F40 1049 1050 /* Copper Pond 2 link timeout */ 1051 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1052 1053 /* Omer CORECTL */ 1054 #define IXGBE_CORECTL 0x014F00 1055 /* BARCTRL */ 1056 #define IXGBE_BARCTRL 0x110F4 1057 #define IXGBE_BARCTRL_FLSIZE 0x0700 1058 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1059 #define IXGBE_BARCTRL_CSRSIZE 0x2000 1060 1061 /* RSCCTL Bit Masks */ 1062 #define IXGBE_RSCCTL_RSCEN 0x01 1063 #define IXGBE_RSCCTL_MAXDESC_1 0x00 1064 #define IXGBE_RSCCTL_MAXDESC_4 0x04 1065 #define IXGBE_RSCCTL_MAXDESC_8 0x08 1066 #define IXGBE_RSCCTL_MAXDESC_16 0x0C 1067 1068 /* RSCDBU Bit Masks */ 1069 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1070 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1071 1072 /* RDRXCTL Bit Masks */ 1073 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 1074 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1075 #define IXGBE_RDRXCTL_MVMEN 0x00000020 1076 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1077 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1078 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1079 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ 1080 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ 1081 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ 1082 1083 /* RQTC Bit Masks and Shifts */ 1084 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1085 #define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1086 #define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1087 #define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1088 #define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1089 #define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1090 #define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1091 #define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1092 #define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1093 1094 /* PSRTYPE.RQPL Bit masks and shift */ 1095 #define IXGBE_PSRTYPE_RQPL_MASK 0x7 1096 #define IXGBE_PSRTYPE_RQPL_SHIFT 29 1097 1098 /* CTRL Bit Masks */ 1099 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 1100 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1101 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1102 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1103 1104 /* FACTPS */ 1105 #define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1106 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1107 1108 /* MHADD Bit Masks */ 1109 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1110 #define IXGBE_MHADD_MFS_SHIFT 16 1111 1112 /* Extended Device Control */ 1113 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1114 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1115 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1116 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1117 1118 /* Direct Cache Access (DCA) definitions */ 1119 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1120 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1121 1122 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1123 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1124 1125 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1126 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1127 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1128 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 1129 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 1130 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 1131 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 1132 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1133 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1134 1135 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1136 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1137 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1138 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1139 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1140 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1141 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1142 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1143 1144 /* MSCA Bit Masks */ 1145 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 1146 #define IXGBE_MSCA_NP_ADDR_SHIFT 0 1147 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 1148 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 1149 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1150 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1151 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1152 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1153 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1154 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 1155 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ 1156 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ 1157 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1158 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1159 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 1160 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 1161 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1162 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 1163 1164 /* MSRWD bit masks */ 1165 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1166 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1167 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1168 #define IXGBE_MSRWD_READ_DATA_SHIFT 16 1169 1170 /* Atlas registers */ 1171 #define IXGBE_ATLAS_PDN_LPBK 0x24 1172 #define IXGBE_ATLAS_PDN_10G 0xB 1173 #define IXGBE_ATLAS_PDN_1G 0xC 1174 #define IXGBE_ATLAS_PDN_AN 0xD 1175 1176 /* Atlas bit masks */ 1177 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1178 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1179 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1180 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1181 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1182 1183 /* Omer bit masks */ 1184 #define IXGBE_CORECTL_WRITE_CMD 0x00010000 1185 1186 /* MDIO definitions */ 1187 1188 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1189 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1190 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1191 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1192 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1193 #define IXGBE_TWINAX_DEV 1 1194 1195 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1196 1197 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 1198 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1199 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1200 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 1201 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1202 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1203 1204 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1205 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1206 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ 1207 #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1208 #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1209 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 1210 1211 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 1212 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ 1213 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ 1214 #define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ 1215 1216 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1217 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1218 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Stat Reg */ 1219 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Tx Dis Reg */ 1220 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Tx Dis */ 1221 1222 /* MII clause 22/28 definitions */ 1223 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1224 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1225 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1226 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1227 #define IXGBE_MII_AUTONEG_REG 0x0 1228 1229 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1230 #define IXGBE_MAX_PHY_ADDR 32 1231 1232 /* PHY IDs*/ 1233 #define TN1010_PHY_ID 0x00A19410 1234 #define TNX_FW_REV 0xB 1235 #define X540_PHY_ID 0x01540200 1236 #define QT2022_PHY_ID 0x0043A400 1237 #define ATH_PHY_ID 0x03429050 1238 #define AQ_FW_REV 0x20 1239 1240 /* PHY Types */ 1241 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1242 1243 /* Special PHY Init Routine */ 1244 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1245 #define IXGBE_PHY_INIT_END_NL 0xFFFF 1246 #define IXGBE_CONTROL_MASK_NL 0xF000 1247 #define IXGBE_DATA_MASK_NL 0x0FFF 1248 #define IXGBE_CONTROL_SHIFT_NL 12 1249 #define IXGBE_DELAY_NL 0 1250 #define IXGBE_DATA_NL 1 1251 #define IXGBE_CONTROL_NL 0x000F 1252 #define IXGBE_CONTROL_EOL_NL 0x0FFF 1253 #define IXGBE_CONTROL_SOL_NL 0x0000 1254 1255 /* General purpose Interrupt Enable */ 1256 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1257 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1258 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1259 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1260 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1261 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1262 #define IXGBE_GPIE_EIAME 0x40000000 1263 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1264 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1265 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1266 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1267 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1268 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1269 1270 /* Packet Buffer Initialization */ 1271 #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1272 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1273 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1274 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1275 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1276 #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1277 #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/ 1278 #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/ 1279 1280 #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1281 #define IXGBE_MAX_PB 8 1282 1283 /* Packet buffer allocation strategies */ 1284 enum { 1285 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1286 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1287 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1288 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1289 }; 1290 1291 /* Transmit Flow Control status */ 1292 #define IXGBE_TFCS_TXOFF 0x00000001 1293 #define IXGBE_TFCS_TXOFF0 0x00000100 1294 #define IXGBE_TFCS_TXOFF1 0x00000200 1295 #define IXGBE_TFCS_TXOFF2 0x00000400 1296 #define IXGBE_TFCS_TXOFF3 0x00000800 1297 #define IXGBE_TFCS_TXOFF4 0x00001000 1298 #define IXGBE_TFCS_TXOFF5 0x00002000 1299 #define IXGBE_TFCS_TXOFF6 0x00004000 1300 #define IXGBE_TFCS_TXOFF7 0x00008000 1301 1302 /* TCP Timer */ 1303 #define IXGBE_TCPTIMER_KS 0x00000100 1304 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1305 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1306 #define IXGBE_TCPTIMER_LOOP 0x00000800 1307 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1308 1309 /* HLREG0 Bit Masks */ 1310 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1311 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1312 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1313 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1314 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1315 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1316 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1317 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1318 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1319 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1320 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1321 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1322 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1323 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1324 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1325 1326 /* VMD_CTL bitmasks */ 1327 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1328 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1329 1330 /* VT_CTL bitmasks */ 1331 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1332 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1333 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1334 #define IXGBE_VT_CTL_POOL_SHIFT 7 1335 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1336 1337 /* VMOLR bitmasks */ 1338 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1339 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1340 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1341 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1342 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1343 1344 /* VFRE bitmask */ 1345 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1346 1347 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1348 1349 /* RDHMPN and TDHMPN bitmasks */ 1350 #define IXGBE_RDHMPN_RDICADDR 0x007FF800 1351 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1352 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1353 #define IXGBE_TDHMPN_TDICADDR 0x003FF800 1354 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1355 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1356 1357 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1358 #define IXGBE_RDMAM_DWORD_SHIFT 9 1359 #define IXGBE_RDMAM_DESC_COMP_FIFO 1 1360 #define IXGBE_RDMAM_DFC_CMD_FIFO 2 1361 #define IXGBE_RDMAM_TCN_STATUS_RAM 4 1362 #define IXGBE_RDMAM_WB_COLL_FIFO 5 1363 #define IXGBE_RDMAM_QSC_CNT_RAM 6 1364 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1365 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1366 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1367 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1368 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1369 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1370 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1371 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1372 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1373 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1374 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1375 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1376 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1377 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1378 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1379 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1380 1381 #define IXGBE_TXDESCIC_READY 0x80000000 1382 1383 /* Receive Checksum Control */ 1384 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1385 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1386 1387 /* FCRTL Bit Masks */ 1388 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1389 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1390 1391 /* PAP bit masks*/ 1392 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1393 1394 /* RMCS Bit Masks */ 1395 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 1396 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1397 #define IXGBE_RMCS_RAC 0x00000004 1398 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 1399 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1400 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1401 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1402 1403 /* FCCFG Bit Masks */ 1404 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1405 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1406 1407 /* Interrupt register bitmasks */ 1408 1409 /* Extended Interrupt Cause Read */ 1410 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1411 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1412 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1413 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1414 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1415 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1416 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1417 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1418 #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1419 #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1420 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1421 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1422 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1423 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1424 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1425 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1426 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1427 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1428 1429 /* Extended Interrupt Cause Set */ 1430 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1431 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1432 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1433 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1434 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1435 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1436 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1437 #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1438 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1439 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1440 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1441 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1442 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1443 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1444 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1445 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1446 1447 /* Extended Interrupt Mask Set */ 1448 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1449 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1450 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1451 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1452 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1453 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1454 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1455 #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */ 1456 #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1457 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1458 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1459 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1460 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1461 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1462 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1463 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1464 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1465 1466 /* Extended Interrupt Mask Clear */ 1467 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1468 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1469 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1470 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1471 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1472 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1473 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1474 #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1475 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1476 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1477 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1478 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1479 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1480 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1481 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1482 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1483 1484 #define IXGBE_EIMS_ENABLE_MASK ( \ 1485 IXGBE_EIMS_RTX_QUEUE | \ 1486 IXGBE_EIMS_LSC | \ 1487 IXGBE_EIMS_TCP_TIMER | \ 1488 IXGBE_EIMS_OTHER) 1489 1490 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1491 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1492 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1493 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1494 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1495 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1496 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1497 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1498 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1499 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1500 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1501 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1502 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1503 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1504 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1505 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1506 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1507 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1508 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ 1509 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1510 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1511 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1512 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1513 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1514 1515 #define IXGBE_MAX_FTQF_FILTERS 128 1516 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1517 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1518 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1519 #define IXGBE_FTQF_PROTOCOL_SCTP 2 1520 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1521 #define IXGBE_FTQF_PRIORITY_SHIFT 2 1522 #define IXGBE_FTQF_POOL_MASK 0x0000003F 1523 #define IXGBE_FTQF_POOL_SHIFT 8 1524 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1525 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1526 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1527 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1528 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1529 #define IXGBE_FTQF_DEST_PORT_MASK 0x17 1530 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1531 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1532 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1533 1534 /* Interrupt clear mask */ 1535 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1536 1537 /* Interrupt Vector Allocation Registers */ 1538 #define IXGBE_IVAR_REG_NUM 25 1539 #define IXGBE_IVAR_REG_NUM_82599 64 1540 #define IXGBE_IVAR_TXRX_ENTRY 96 1541 #define IXGBE_IVAR_RX_ENTRY 64 1542 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1543 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1544 #define IXGBE_IVAR_TX_ENTRY 32 1545 1546 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1547 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1548 1549 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1550 1551 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1552 1553 /* ETYPE Queue Filter/Select Bit Masks */ 1554 #define IXGBE_MAX_ETQF_FILTERS 8 1555 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1556 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1557 #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 1558 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1559 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1560 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1561 #define IXGBE_ETQF_POOL_SHIFT 20 1562 1563 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1564 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1565 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1566 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1567 1568 /* 1569 * ETQF filter list: one static filter per filter consumer. This is 1570 * to avoid filter collisions later. Add new filters 1571 * here!! 1572 * 1573 * Current filters: 1574 * EAPOL 802.1x (0x888e): Filter 0 1575 * FCoE (0x8906): Filter 2 1576 * 1588 (0x88f7): Filter 3 1577 * FIP (0x8914): Filter 4 1578 */ 1579 #define IXGBE_ETQF_FILTER_EAPOL 0 1580 #define IXGBE_ETQF_FILTER_FCOE 2 1581 #define IXGBE_ETQF_FILTER_1588 3 1582 #define IXGBE_ETQF_FILTER_FIP 4 1583 #define IXGBE_ETQF_FILTER_LLDP 5 1584 #define IXGBE_ETQF_FILTER_LACP 6 1585 1586 /* VLAN Control Bit Masks */ 1587 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1588 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1589 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1590 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1591 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1592 1593 /* VLAN pool filtering masks */ 1594 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1595 #define IXGBE_VLVF_ENTRIES 64 1596 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1597 1598 /* Per VF Port VLAN insertion rules */ 1599 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1600 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1601 1602 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1603 1604 /* STATUS Bit Masks */ 1605 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1606 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1607 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 1608 1609 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1610 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1611 1612 /* ESDP Bit Masks */ 1613 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1614 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1615 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1616 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1617 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1618 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1619 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1620 #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 1621 #define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 1622 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 1623 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1624 #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */ 1625 #define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 1626 1627 /* LEDCTL Bit Masks */ 1628 #define IXGBE_LED_IVRT_BASE 0x00000040 1629 #define IXGBE_LED_BLINK_BASE 0x00000080 1630 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1631 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1632 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i)) 1633 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1634 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1635 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1636 1637 /* LED modes */ 1638 #define IXGBE_LED_LINK_UP 0x0 1639 #define IXGBE_LED_LINK_10G 0x1 1640 #define IXGBE_LED_MAC 0x2 1641 #define IXGBE_LED_FILTER 0x3 1642 #define IXGBE_LED_LINK_ACTIVE 0x4 1643 #define IXGBE_LED_LINK_1G 0x5 1644 #define IXGBE_LED_ON 0xE 1645 #define IXGBE_LED_OFF 0xF 1646 1647 /* AUTOC Bit Masks */ 1648 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1649 #define IXGBE_AUTOC_KX4_SUPP 0x80000000 1650 #define IXGBE_AUTOC_KX_SUPP 0x40000000 1651 #define IXGBE_AUTOC_PAUSE 0x30000000 1652 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1653 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1654 #define IXGBE_AUTOC_RF 0x08000000 1655 #define IXGBE_AUTOC_PD_TMR 0x06000000 1656 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1657 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1658 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1659 #define IXGBE_AUTOC_FECA 0x00040000 1660 #define IXGBE_AUTOC_FECR 0x00020000 1661 #define IXGBE_AUTOC_KR_SUPP 0x00010000 1662 #define IXGBE_AUTOC_AN_RESTART 0x00001000 1663 #define IXGBE_AUTOC_FLU 0x00000001 1664 #define IXGBE_AUTOC_LMS_SHIFT 13 1665 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1666 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1667 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1668 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1669 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1670 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1671 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1672 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1673 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1674 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1675 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1676 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1677 1678 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1679 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1680 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1681 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1682 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1683 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1684 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1685 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1686 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1687 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1688 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1689 1690 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1691 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1692 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1693 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1694 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1695 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1696 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 1697 #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1698 1699 #define IXGBE_MACC_FLU 0x00000001 1700 #define IXGBE_MACC_FSV_10G 0x00030000 1701 #define IXGBE_MACC_FS 0x00040000 1702 #define IXGBE_MAC_RX2TX_LPBK 0x00000002 1703 1704 /* Veto Bit definition */ 1705 #define IXGBE_MMNGC_MNG_VETO 0x00000001 1706 1707 /* LINKS Bit Masks */ 1708 #define IXGBE_LINKS_KX_AN_COMP 0x80000000 1709 #define IXGBE_LINKS_UP 0x40000000 1710 #define IXGBE_LINKS_SPEED 0x20000000 1711 #define IXGBE_LINKS_MODE 0x18000000 1712 #define IXGBE_LINKS_RX_MODE 0x06000000 1713 #define IXGBE_LINKS_TX_MODE 0x01800000 1714 #define IXGBE_LINKS_XGXS_EN 0x00400000 1715 #define IXGBE_LINKS_SGMII_EN 0x02000000 1716 #define IXGBE_LINKS_PCS_1G_EN 0x00200000 1717 #define IXGBE_LINKS_1G_AN_EN 0x00100000 1718 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1719 #define IXGBE_LINKS_1G_SYNC 0x00040000 1720 #define IXGBE_LINKS_10G_ALIGN 0x00020000 1721 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1722 #define IXGBE_LINKS_TL_FAULT 0x00001000 1723 #define IXGBE_LINKS_SIGNAL 0x00000F00 1724 1725 #define IXGBE_LINKS_SPEED_NON_STD 0x08000000 1726 #define IXGBE_LINKS_SPEED_82599 0x30000000 1727 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1728 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1729 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 1730 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1731 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1732 1733 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1734 1735 /* PCS1GLSTA Bit Masks */ 1736 #define IXGBE_PCS1GLSTA_LINK_OK 1 1737 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1738 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1739 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1740 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1741 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1742 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1743 1744 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1745 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1746 1747 /* PCS1GLCTL Bit Masks */ 1748 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1749 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1750 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1751 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1752 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1753 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1754 1755 /* ANLP1 Bit Masks */ 1756 #define IXGBE_ANLP1_PAUSE 0x0C00 1757 #define IXGBE_ANLP1_SYM_PAUSE 0x0400 1758 #define IXGBE_ANLP1_ASM_PAUSE 0x0800 1759 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1760 1761 /* SW Semaphore Register bitmasks */ 1762 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1763 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1764 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1765 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1766 1767 /* SW_FW_SYNC/GSSR definitions */ 1768 #define IXGBE_GSSR_EEP_SM 0x0001 1769 #define IXGBE_GSSR_PHY0_SM 0x0002 1770 #define IXGBE_GSSR_PHY1_SM 0x0004 1771 #define IXGBE_GSSR_MAC_CSR_SM 0x0008 1772 #define IXGBE_GSSR_FLASH_SM 0x0010 1773 #define IXGBE_GSSR_SW_MNG_SM 0x0400 1774 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */ 1775 #define IXGBE_GSSR_I2C_MASK 0x1800 1776 1777 /* FW Status register bitmask */ 1778 #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1779 1780 /* EEC Register */ 1781 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1782 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1783 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1784 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1785 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1786 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1787 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1788 #define IXGBE_EEC_FWE_SHIFT 4 1789 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1790 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1791 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1792 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1793 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1794 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 1795 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1796 /* EEPROM Addressing bits based on type (0-small, 1-large) */ 1797 #define IXGBE_EEC_ADDR_SIZE 0x00000400 1798 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1799 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 1800 1801 #define IXGBE_EEC_SIZE_SHIFT 11 1802 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 1803 #define IXGBE_EEPROM_OPCODE_BITS 8 1804 1805 /* Part Number String Length */ 1806 #define IXGBE_PBANUM_LENGTH 11 1807 1808 /* Checksum and EEPROM pointers */ 1809 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA 1810 #define IXGBE_EEPROM_CHECKSUM 0x3F 1811 #define IXGBE_EEPROM_SUM 0xBABA 1812 #define IXGBE_PCIE_ANALOG_PTR 0x03 1813 #define IXGBE_ATLAS0_CONFIG_PTR 0x04 1814 #define IXGBE_PHY_PTR 0x04 1815 #define IXGBE_ATLAS1_CONFIG_PTR 0x05 1816 #define IXGBE_OPTION_ROM_PTR 0x05 1817 #define IXGBE_PCIE_GENERAL_PTR 0x06 1818 #define IXGBE_PCIE_CONFIG0_PTR 0x07 1819 #define IXGBE_PCIE_CONFIG1_PTR 0x08 1820 #define IXGBE_CORE0_PTR 0x09 1821 #define IXGBE_CORE1_PTR 0x0A 1822 #define IXGBE_MAC0_PTR 0x0B 1823 #define IXGBE_MAC1_PTR 0x0C 1824 #define IXGBE_CSR0_CONFIG_PTR 0x0D 1825 #define IXGBE_CSR1_CONFIG_PTR 0x0E 1826 #define IXGBE_PCIE_ANALOG_PTR_X550 0x02 1827 #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 1828 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 1829 #define IXGBE_PCIE_CONFIG_SIZE 0x08 1830 #define IXGBE_EEPROM_LAST_WORD 0x41 1831 #define IXGBE_FW_PTR 0x0F 1832 #define IXGBE_PBANUM0_PTR 0x15 1833 #define IXGBE_PBANUM1_PTR 0x16 1834 #define IXGBE_FREE_SPACE_PTR 0X3E 1835 1836 /* External Thermal Sensor Config */ 1837 #define IXGBE_ETS_CFG 0x26 1838 #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0 1839 #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6 1840 #define IXGBE_ETS_TYPE_MASK 0x0038 1841 #define IXGBE_ETS_TYPE_SHIFT 3 1842 #define IXGBE_ETS_TYPE_EMC 0x000 1843 #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000 1844 #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007 1845 #define IXGBE_ETS_DATA_LOC_MASK 0x3C00 1846 #define IXGBE_ETS_DATA_LOC_SHIFT 10 1847 #define IXGBE_ETS_DATA_INDEX_MASK 0x0300 1848 #define IXGBE_ETS_DATA_INDEX_SHIFT 8 1849 #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF 1850 1851 #define IXGBE_SAN_MAC_ADDR_PTR 0x28 1852 #define IXGBE_DEVICE_CAPS 0x2C 1853 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1854 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1855 #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 1856 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1857 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 1858 1859 /* MSI-X capability fields masks */ 1860 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1861 1862 /* Legacy EEPROM word offsets */ 1863 #define IXGBE_ISCSI_BOOT_CAPS 0x0033 1864 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1865 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1866 1867 /* EEPROM Commands - SPI */ 1868 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1869 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1870 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1871 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1872 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1873 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1874 /* EEPROM reset Write Enable latch */ 1875 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1876 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1877 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1878 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1879 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1880 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1881 1882 /* EEPROM Read Register */ 1883 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1884 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1885 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1886 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1887 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1888 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1889 1890 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 1891 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ 1892 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ 1893 1894 #define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 1895 #define IXGBE_EEPROM_CCD_BIT 2 /* EEPROM Core Clock Disable bit */ 1896 1897 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1898 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1899 #endif 1900 1901 #ifndef IXGBE_EERD_EEWR_ATTEMPTS 1902 /* Number of 5 microseconds we wait for EERD read and 1903 * EERW write to complete */ 1904 #define IXGBE_EERD_EEWR_ATTEMPTS 100000 1905 #endif 1906 1907 #ifndef IXGBE_FLUDONE_ATTEMPTS 1908 /* # attempts we wait for flush update to complete */ 1909 #define IXGBE_FLUDONE_ATTEMPTS 20000 1910 #endif 1911 1912 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1913 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1914 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1915 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1916 1917 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1918 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1919 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1920 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1921 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 1922 #define IXGBE_FW_LESM_STATE_1 0x1 1923 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 1924 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1925 #define IXGBE_FW_PATCH_VERSION_4 0x7 1926 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 1927 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 1928 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 1929 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 1930 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 1931 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1932 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ 1933 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ 1934 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ 1935 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ 1936 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ 1937 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ 1938 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ 1939 1940 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 1941 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 1942 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 1943 1944 /* PCI Bus Info */ 1945 #define IXGBE_PCI_DEVICE_STATUS 0xAA 1946 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 1947 #define IXGBE_PCI_LINK_STATUS 0xB2 1948 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1949 #define IXGBE_PCI_LINK_WIDTH 0x3F0 1950 #define IXGBE_PCI_LINK_WIDTH_1 0x10 1951 #define IXGBE_PCI_LINK_WIDTH_2 0x20 1952 #define IXGBE_PCI_LINK_WIDTH_4 0x40 1953 #define IXGBE_PCI_LINK_WIDTH_8 0x80 1954 #define IXGBE_PCI_LINK_SPEED 0xF 1955 #define IXGBE_PCI_LINK_SPEED_2500 0x1 1956 #define IXGBE_PCI_LINK_SPEED_5000 0x2 1957 #define IXGBE_PCI_LINK_SPEED_8000 0x3 1958 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1959 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1960 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1961 1962 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 1963 #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 1964 #define IXGBE_PCIDEVCTRL2_50_100us 0x1 1965 #define IXGBE_PCIDEVCTRL2_1_2ms 0x2 1966 #define IXGBE_PCIDEVCTRL2_16_32ms 0x5 1967 #define IXGBE_PCIDEVCTRL2_65_130ms 0x6 1968 #define IXGBE_PCIDEVCTRL2_260_520ms 0x9 1969 #define IXGBE_PCIDEVCTRL2_1_2s 0xa 1970 #define IXGBE_PCIDEVCTRL2_4_8s 0xd 1971 #define IXGBE_PCIDEVCTRL2_17_34s 0xe 1972 1973 /* Number of 100 microseconds we wait for PCI Express master disable */ 1974 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1975 1976 /* RAH */ 1977 #define IXGBE_RAH_VIND_MASK 0x003C0000 1978 #define IXGBE_RAH_VIND_SHIFT 18 1979 #define IXGBE_RAH_AV 0x80000000 1980 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 1981 1982 /* Header split receive */ 1983 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 1984 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 1985 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 1986 #define IXGBE_RFCTL_RSC_DIS 0x00000020 1987 #define IXGBE_RFCTL_NFSW_DIS 0x00000040 1988 #define IXGBE_RFCTL_NFSR_DIS 0x00000080 1989 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 1990 #define IXGBE_RFCTL_NFS_VER_SHIFT 8 1991 #define IXGBE_RFCTL_NFS_VER_2 0 1992 #define IXGBE_RFCTL_NFS_VER_3 1 1993 #define IXGBE_RFCTL_NFS_VER_4 2 1994 #define IXGBE_RFCTL_IPV6_DIS 0x00000400 1995 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 1996 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 1997 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 1998 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1999 2000 /* Transmit Config masks */ 2001 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 2002 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 2003 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2004 /* Enable short packet padding to 64 bytes */ 2005 #define IXGBE_TX_PAD_ENABLE 0x00000400 2006 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2007 /* This allows for 16K packets + 4k for vlan */ 2008 #define IXGBE_MAX_FRAME_SZ 0x40040000 2009 2010 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2011 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2012 2013 /* Receive Config masks */ 2014 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2015 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 2016 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 2017 #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 2018 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 2019 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 2020 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2021 2022 #define IXGBE_TSAUXC_EN_CLK 0x00000004 2023 #define IXGBE_TSAUXC_SYNCLK 0x00000008 2024 #define IXGBE_TSAUXC_SDP0_INT 0x00000040 2025 2026 #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 2027 #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 2028 2029 #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 2030 #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 2031 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 2032 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 2033 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2034 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 2035 #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2036 2037 #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 2038 #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 2039 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 2040 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 2041 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2042 #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2043 2044 #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2045 #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2046 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2047 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2048 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2049 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2050 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2051 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2052 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2053 #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00 2054 #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2055 2056 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2057 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2058 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2059 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2060 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2061 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2062 /* Receive Priority Flow Control Enable */ 2063 #define IXGBE_FCTRL_RPFCE 0x00004000 2064 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2065 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2066 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2067 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2068 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2069 #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */ 2070 2071 #define IXGBE_MFLCN_RPFCE_SHIFT 4 2072 2073 /* Multiple Receive Queue Control */ 2074 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2075 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2076 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2077 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2078 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2079 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2080 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2081 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2082 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2083 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2084 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2085 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2086 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2087 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2088 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2089 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2090 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2091 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2092 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2093 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2094 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2095 #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 2096 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2097 2098 #define IXGBE_FWSM_TS_ENABLED 0x1 2099 2100 /* Queue Drop Enable */ 2101 #define IXGBE_QDE_ENABLE 0x00000001 2102 #define IXGBE_QDE_HIDE_VLAN 0x00000002 2103 #define IXGBE_QDE_IDX_MASK 0x00007F00 2104 #define IXGBE_QDE_IDX_SHIFT 8 2105 #define IXGBE_QDE_WRITE 0x00010000 2106 2107 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2108 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2109 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2110 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2111 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2112 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2113 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 2114 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2115 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2116 2117 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2118 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2119 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2120 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2121 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2122 /* Multiple Transmit Queue Command Register */ 2123 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2124 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2125 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2126 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2127 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2128 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2129 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */ 2130 2131 /* Receive Descriptor bit definitions */ 2132 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2133 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2134 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2135 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2136 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2137 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2138 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2139 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2140 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2141 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2142 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2143 #define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ 2144 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2145 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2146 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2147 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2148 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2149 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2150 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2151 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2152 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2153 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2154 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2155 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2156 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2157 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2158 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2159 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2160 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2161 #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ 2162 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 2163 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2164 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2165 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2166 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2167 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2168 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2169 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2170 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2171 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2172 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2173 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2174 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2175 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2176 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2177 #define IXGBE_RXD_PRI_SHIFT 13 2178 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2179 #define IXGBE_RXD_CFI_SHIFT 12 2180 2181 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2182 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2183 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2184 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2185 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2186 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2187 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2188 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2189 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2190 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2191 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2192 #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */ 2193 2194 /* PSRTYPE bit definitions */ 2195 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 2196 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 2197 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2198 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2199 #define IXGBE_PSRTYPE_L2HDR 0x00001000 2200 2201 /* SRRCTL bit definitions */ 2202 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2203 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 2204 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2205 #define IXGBE_SRRCTL_DROP_EN 0x10000000 2206 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2207 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2208 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2209 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2210 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2211 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2212 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2213 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2214 2215 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2216 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2217 2218 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2219 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2220 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2221 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2222 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2223 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 2224 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2225 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2226 #define IXGBE_RXDADV_SPH 0x8000 2227 2228 /* RSS Hash results */ 2229 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2230 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2231 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2232 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2233 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2234 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2235 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2236 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2237 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2238 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2239 2240 /* RSS Packet Types as indicated in the receive descriptor. */ 2241 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2242 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2243 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2244 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2245 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2246 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2247 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2248 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2249 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2250 #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ 2251 #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ 2252 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2253 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2254 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2255 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2256 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2257 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2258 2259 /* Security Processing bit Indication */ 2260 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2261 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2262 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2263 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2264 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2265 2266 /* Masks to determine if packets should be dropped due to frame errors */ 2267 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2268 IXGBE_RXD_ERR_CE | \ 2269 IXGBE_RXD_ERR_LE | \ 2270 IXGBE_RXD_ERR_PE | \ 2271 IXGBE_RXD_ERR_OSE | \ 2272 IXGBE_RXD_ERR_USE) 2273 2274 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2275 IXGBE_RXDADV_ERR_CE | \ 2276 IXGBE_RXDADV_ERR_LE | \ 2277 IXGBE_RXDADV_ERR_PE | \ 2278 IXGBE_RXDADV_ERR_OSE | \ 2279 IXGBE_RXDADV_ERR_USE) 2280 2281 /* Multicast bit mask */ 2282 #define IXGBE_MCSTCTRL_MFE 0x4 2283 2284 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2285 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2286 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2287 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2288 2289 /* Vlan-specific macros */ 2290 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2291 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2292 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2293 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2294 2295 /* SR-IOV specific macros */ 2296 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2297 #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2298 #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) 2299 #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2300 /* Translated register #defines */ 2301 #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) 2302 #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) 2303 #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) 2304 #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) 2305 2306 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ 2307 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) 2308 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ 2309 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) 2310 2311 #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \ 2312 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) 2313 #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \ 2314 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) 2315 2316 enum ixgbe_fdir_pballoc_type { 2317 IXGBE_FDIR_PBALLOC_NONE = 0, 2318 IXGBE_FDIR_PBALLOC_64K = 1, 2319 IXGBE_FDIR_PBALLOC_128K = 2, 2320 IXGBE_FDIR_PBALLOC_256K = 3, 2321 }; 2322 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 2323 2324 /* Flow Director register values */ 2325 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2326 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2327 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2328 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2329 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2330 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2331 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2332 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2333 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2334 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2335 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2336 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2337 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2338 2339 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2340 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2341 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2342 #define IXGBE_FDIRM_VLANID 0x00000001 2343 #define IXGBE_FDIRM_VLANP 0x00000002 2344 #define IXGBE_FDIRM_POOL 0x00000004 2345 #define IXGBE_FDIRM_L4P 0x00000008 2346 #define IXGBE_FDIRM_FLEX 0x00000010 2347 #define IXGBE_FDIRM_DIPv6 0x00000020 2348 2349 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2350 #define IXGBE_FDIRFREE_FREE_SHIFT 0 2351 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2352 #define IXGBE_FDIRFREE_COLL_SHIFT 16 2353 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2354 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2355 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2356 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2357 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2358 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2359 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2360 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2361 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2362 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2363 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2364 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2365 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2366 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2367 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2368 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2369 2370 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2371 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2372 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2373 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2374 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2375 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2376 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2377 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2378 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2379 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2380 #define IXGBE_FDIRCMD_IPV6 0x00000080 2381 #define IXGBE_FDIRCMD_CLEARHT 0x00000100 2382 #define IXGBE_FDIRCMD_DROP 0x00000200 2383 #define IXGBE_FDIRCMD_INT 0x00000400 2384 #define IXGBE_FDIRCMD_LAST 0x00000800 2385 #define IXGBE_FDIRCMD_COLLISION 0x00001000 2386 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2387 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2388 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2389 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2390 #define IXGBE_FDIR_INIT_DONE_POLL 10 2391 #define IXGBE_FDIRCMD_CMD_POLL 10 2392 2393 #define IXGBE_FDIR_DROP_QUEUE 127 2394 2395 /* Manageablility Host Interface defines */ 2396 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2397 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2398 #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2399 #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ 2400 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 2401 #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ 2402 2403 /* CEM Support */ 2404 #define FW_CEM_HDR_LEN 0x4 2405 #define FW_CEM_CMD_DRIVER_INFO 0xDD 2406 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2407 #define FW_CEM_CMD_RESERVED 0x0 2408 #define FW_CEM_UNUSED_VER 0x0 2409 #define FW_CEM_MAX_RETRIES 3 2410 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 2411 #define FW_READ_SHADOW_RAM_CMD 0x31 2412 #define FW_READ_SHADOW_RAM_LEN 0x6 2413 #define FW_WRITE_SHADOW_RAM_CMD 0x33 2414 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 2415 #define FW_SHADOW_RAM_DUMP_CMD 0x36 2416 #define FW_SHADOW_RAM_DUMP_LEN 0 2417 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 2418 #define FW_NVM_DATA_OFFSET 3 2419 #define FW_MAX_READ_BUFFER_SIZE 1024 2420 #define FW_DISABLE_RXEN_CMD 0xDE 2421 #define FW_DISABLE_RXEN_LEN 0x1 2422 2423 /* Host Interface Command Structures */ 2424 struct ixgbe_hic_hdr { 2425 u8 cmd; 2426 u8 buf_len; 2427 union { 2428 u8 cmd_resv; 2429 u8 ret_status; 2430 } cmd_or_resp; 2431 u8 checksum; 2432 }; 2433 2434 struct ixgbe_hic_hdr2_req { 2435 u8 cmd; 2436 u8 buf_lenh; 2437 u8 buf_lenl; 2438 u8 checksum; 2439 }; 2440 2441 struct ixgbe_hic_hdr2_rsp { 2442 u8 cmd; 2443 u8 buf_lenl; 2444 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 2445 u8 checksum; 2446 }; 2447 2448 union ixgbe_hic_hdr2 { 2449 struct ixgbe_hic_hdr2_req req; 2450 struct ixgbe_hic_hdr2_rsp rsp; 2451 }; 2452 2453 struct ixgbe_hic_drv_info { 2454 struct ixgbe_hic_hdr hdr; 2455 u8 port_num; 2456 u8 ver_sub; 2457 u8 ver_build; 2458 u8 ver_min; 2459 u8 ver_maj; 2460 u8 pad; /* end spacing to ensure length is mult. of dword */ 2461 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2462 }; 2463 2464 /* These need to be dword aligned */ 2465 struct ixgbe_hic_read_shadow_ram { 2466 union ixgbe_hic_hdr2 hdr; 2467 u32 address; 2468 u16 length; 2469 u16 pad2; 2470 u16 data; 2471 u16 pad3; 2472 }; 2473 2474 struct ixgbe_hic_write_shadow_ram { 2475 union ixgbe_hic_hdr2 hdr; 2476 __be32 address; 2477 __be16 length; 2478 u16 pad2; 2479 u16 data; 2480 u16 pad3; 2481 }; 2482 2483 struct ixgbe_hic_disable_rxen { 2484 struct ixgbe_hic_hdr hdr; 2485 u8 port_number; 2486 u8 pad2; 2487 u16 pad3; 2488 }; 2489 2490 /* Transmit Descriptor - Advanced */ 2491 union ixgbe_adv_tx_desc { 2492 struct { 2493 __le64 buffer_addr; /* Address of descriptor's data buf */ 2494 __le32 cmd_type_len; 2495 __le32 olinfo_status; 2496 } read; 2497 struct { 2498 __le64 rsvd; /* Reserved */ 2499 __le32 nxtseq_seed; 2500 __le32 status; 2501 } wb; 2502 }; 2503 2504 /* Receive Descriptor - Advanced */ 2505 union ixgbe_adv_rx_desc { 2506 struct { 2507 __le64 pkt_addr; /* Packet buffer address */ 2508 __le64 hdr_addr; /* Header buffer address */ 2509 } read; 2510 struct { 2511 struct { 2512 union { 2513 __le32 data; 2514 struct { 2515 __le16 pkt_info; /* RSS, Pkt type */ 2516 __le16 hdr_info; /* Splithdr, hdrlen */ 2517 } hs_rss; 2518 } lo_dword; 2519 union { 2520 __le32 rss; /* RSS Hash */ 2521 struct { 2522 __le16 ip_id; /* IP id */ 2523 __le16 csum; /* Packet Checksum */ 2524 } csum_ip; 2525 } hi_dword; 2526 } lower; 2527 struct { 2528 __le32 status_error; /* ext status/error */ 2529 __le16 length; /* Packet length */ 2530 __le16 vlan; /* VLAN tag */ 2531 } upper; 2532 } wb; /* writeback */ 2533 }; 2534 2535 /* Context descriptors */ 2536 struct ixgbe_adv_tx_context_desc { 2537 __le32 vlan_macip_lens; 2538 __le32 seqnum_seed; 2539 __le32 type_tucmd_mlhl; 2540 __le32 mss_l4len_idx; 2541 }; 2542 2543 /* Adv Transmit Descriptor Config Masks */ 2544 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2545 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2546 #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */ 2547 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2548 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2549 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2550 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 2551 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 2552 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2553 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2554 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2555 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2556 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 2557 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2558 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2559 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2560 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2561 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2562 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2563 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2564 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2565 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2566 IXGBE_ADVTXD_POPTS_SHIFT) 2567 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2568 IXGBE_ADVTXD_POPTS_SHIFT) 2569 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2570 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2571 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2572 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 2573 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2574 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2575 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2576 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2577 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2578 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2579 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2580 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2581 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2582 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ 2583 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2584 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2585 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2586 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2587 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2588 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2589 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2590 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ 2591 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ 2592 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2593 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2594 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2595 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2596 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2597 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2598 2599 /* Autonegotiation advertised speeds */ 2600 typedef u32 ixgbe_autoneg_advertised; 2601 /* Link speed */ 2602 typedef u32 ixgbe_link_speed; 2603 #define IXGBE_LINK_SPEED_UNKNOWN 0 2604 #define IXGBE_LINK_SPEED_100_FULL 0x0008 2605 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2606 #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 2607 #define IXGBE_LINK_SPEED_5GB_FULL 0x0800 2608 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2609 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2610 IXGBE_LINK_SPEED_10GB_FULL) 2611 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2612 IXGBE_LINK_SPEED_1GB_FULL | \ 2613 IXGBE_LINK_SPEED_10GB_FULL) 2614 2615 /* Flow Control Data Sheet defined values 2616 * Calculation and defines taken from 802.1bb Annex O 2617 */ 2618 2619 /* BitTimes (BT) conversion */ 2620 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 2621 #define IXGBE_B2BT(BT) (BT * 8) 2622 2623 /* Calculate Delay to respond to PFC */ 2624 #define IXGBE_PFC_D 672 2625 2626 /* Calculate Cable Delay */ 2627 #define IXGBE_CABLE_DC 5556 /* Delay Copper */ 2628 #define IXGBE_CABLE_DO 5000 /* Delay Optical */ 2629 2630 /* Calculate Interface Delay X540 */ 2631 #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 2632 #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 2633 #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 2634 2635 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 2636 2637 /* Calculate Interface Delay 82598, 82599 */ 2638 #define IXGBE_PHY_D 12800 2639 #define IXGBE_MAC_D 4096 2640 #define IXGBE_XAUI_D (2 * 1024) 2641 2642 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 2643 2644 /* Calculate Delay incurred from higher layer */ 2645 #define IXGBE_HD 6144 2646 2647 /* Calculate PCI Bus delay for low thresholds */ 2648 #define IXGBE_PCI_DELAY 10000 2649 2650 /* Calculate X540 delay value in bit times */ 2651 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 2652 ((36 * \ 2653 (IXGBE_B2BT(_max_frame_link) + \ 2654 IXGBE_PFC_D + \ 2655 (2 * IXGBE_CABLE_DC) + \ 2656 (2 * IXGBE_ID_X540) + \ 2657 IXGBE_HD) / 25 + 1) + \ 2658 2 * IXGBE_B2BT(_max_frame_tc)) 2659 2660 /* Calculate 82599, 82598 delay value in bit times */ 2661 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 2662 ((36 * \ 2663 (IXGBE_B2BT(_max_frame_link) + \ 2664 IXGBE_PFC_D + \ 2665 (2 * IXGBE_CABLE_DC) + \ 2666 (2 * IXGBE_ID) + \ 2667 IXGBE_HD) / 25 + 1) + \ 2668 2 * IXGBE_B2BT(_max_frame_tc)) 2669 2670 /* Calculate low threshold delay values */ 2671 #define IXGBE_LOW_DV_X540(_max_frame_tc) \ 2672 (2 * IXGBE_B2BT(_max_frame_tc) + \ 2673 (36 * IXGBE_PCI_DELAY / 25) + 1) 2674 #define IXGBE_LOW_DV(_max_frame_tc) \ 2675 (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 2676 2677 /* Software ATR hash keys */ 2678 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 2679 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 2680 2681 /* Software ATR input stream values and masks */ 2682 #define IXGBE_ATR_HASH_MASK 0x7fff 2683 #define IXGBE_ATR_L4TYPE_MASK 0x3 2684 #define IXGBE_ATR_L4TYPE_UDP 0x1 2685 #define IXGBE_ATR_L4TYPE_TCP 0x2 2686 #define IXGBE_ATR_L4TYPE_SCTP 0x3 2687 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2688 enum ixgbe_atr_flow_type { 2689 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 2690 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 2691 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 2692 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 2693 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 2694 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 2695 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 2696 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 2697 }; 2698 2699 /* Flow Director ATR input struct. */ 2700 union ixgbe_atr_input { 2701 /* 2702 * Byte layout in order, all values with MSB first: 2703 * 2704 * vm_pool - 1 byte 2705 * flow_type - 1 byte 2706 * vlan_id - 2 bytes 2707 * src_ip - 16 bytes 2708 * dst_ip - 16 bytes 2709 * src_port - 2 bytes 2710 * dst_port - 2 bytes 2711 * flex_bytes - 2 bytes 2712 * bkt_hash - 2 bytes 2713 */ 2714 struct { 2715 u8 vm_pool; 2716 u8 flow_type; 2717 __be16 vlan_id; 2718 __be32 dst_ip[4]; 2719 __be32 src_ip[4]; 2720 __be16 src_port; 2721 __be16 dst_port; 2722 __be16 flex_bytes; 2723 __be16 bkt_hash; 2724 } formatted; 2725 __be32 dword_stream[11]; 2726 }; 2727 2728 /* Flow Director compressed ATR hash input struct */ 2729 union ixgbe_atr_hash_dword { 2730 struct { 2731 u8 vm_pool; 2732 u8 flow_type; 2733 __be16 vlan_id; 2734 } formatted; 2735 __be32 ip; 2736 struct { 2737 __be16 src; 2738 __be16 dst; 2739 } port; 2740 __be16 flex_bytes; 2741 __be32 dword; 2742 }; 2743 2744 enum ixgbe_eeprom_type { 2745 ixgbe_eeprom_uninitialized = 0, 2746 ixgbe_eeprom_spi, 2747 ixgbe_flash, 2748 ixgbe_eeprom_none /* No NVM support */ 2749 }; 2750 2751 enum ixgbe_mac_type { 2752 ixgbe_mac_unknown = 0, 2753 ixgbe_mac_82598EB, 2754 ixgbe_mac_82599EB, 2755 ixgbe_mac_X540, 2756 ixgbe_mac_X550, 2757 ixgbe_mac_X550EM_x, 2758 ixgbe_num_macs 2759 }; 2760 2761 enum ixgbe_phy_type { 2762 ixgbe_phy_unknown = 0, 2763 ixgbe_phy_none, 2764 ixgbe_phy_tn, 2765 ixgbe_phy_aq, 2766 ixgbe_phy_x550em_kr, 2767 ixgbe_phy_x550em_kx4, 2768 ixgbe_phy_x550em_ext_t, 2769 ixgbe_phy_cu_unknown, 2770 ixgbe_phy_qt, 2771 ixgbe_phy_xaui, 2772 ixgbe_phy_nl, 2773 ixgbe_phy_sfp_passive_tyco, 2774 ixgbe_phy_sfp_passive_unknown, 2775 ixgbe_phy_sfp_active_unknown, 2776 ixgbe_phy_sfp_avago, 2777 ixgbe_phy_sfp_ftl, 2778 ixgbe_phy_sfp_ftl_active, 2779 ixgbe_phy_sfp_unknown, 2780 ixgbe_phy_sfp_intel, 2781 ixgbe_phy_qsfp_passive_unknown, 2782 ixgbe_phy_qsfp_active_unknown, 2783 ixgbe_phy_qsfp_intel, 2784 ixgbe_phy_qsfp_unknown, 2785 ixgbe_phy_sfp_unsupported, 2786 ixgbe_phy_generic 2787 }; 2788 2789 /* 2790 * SFP+ module type IDs: 2791 * 2792 * ID Module Type 2793 * ============= 2794 * 0 SFP_DA_CU 2795 * 1 SFP_SR 2796 * 2 SFP_LR 2797 * 3 SFP_DA_CU_CORE0 - 82599-specific 2798 * 4 SFP_DA_CU_CORE1 - 82599-specific 2799 * 5 SFP_SR/LR_CORE0 - 82599-specific 2800 * 6 SFP_SR/LR_CORE1 - 82599-specific 2801 */ 2802 enum ixgbe_sfp_type { 2803 ixgbe_sfp_type_da_cu = 0, 2804 ixgbe_sfp_type_sr = 1, 2805 ixgbe_sfp_type_lr = 2, 2806 ixgbe_sfp_type_da_cu_core0 = 3, 2807 ixgbe_sfp_type_da_cu_core1 = 4, 2808 ixgbe_sfp_type_srlr_core0 = 5, 2809 ixgbe_sfp_type_srlr_core1 = 6, 2810 ixgbe_sfp_type_da_act_lmt_core0 = 7, 2811 ixgbe_sfp_type_da_act_lmt_core1 = 8, 2812 ixgbe_sfp_type_1g_cu_core0 = 9, 2813 ixgbe_sfp_type_1g_cu_core1 = 10, 2814 ixgbe_sfp_type_1g_sx_core0 = 11, 2815 ixgbe_sfp_type_1g_sx_core1 = 12, 2816 ixgbe_sfp_type_1g_lx_core0 = 13, 2817 ixgbe_sfp_type_1g_lx_core1 = 14, 2818 ixgbe_sfp_type_not_present = 0xFFFE, 2819 ixgbe_sfp_type_unknown = 0xFFFF 2820 }; 2821 2822 enum ixgbe_media_type { 2823 ixgbe_media_type_unknown = 0, 2824 ixgbe_media_type_fiber, 2825 ixgbe_media_type_fiber_qsfp, 2826 ixgbe_media_type_fiber_lco, 2827 ixgbe_media_type_copper, 2828 ixgbe_media_type_backplane, 2829 ixgbe_media_type_cx4, 2830 ixgbe_media_type_virtual 2831 }; 2832 2833 /* Flow Control Settings */ 2834 enum ixgbe_fc_mode { 2835 ixgbe_fc_none = 0, 2836 ixgbe_fc_rx_pause, 2837 ixgbe_fc_tx_pause, 2838 ixgbe_fc_full, 2839 ixgbe_fc_default 2840 }; 2841 2842 /* Smart Speed Settings */ 2843 #define IXGBE_SMARTSPEED_MAX_RETRIES 3 2844 enum ixgbe_smart_speed { 2845 ixgbe_smart_speed_auto = 0, 2846 ixgbe_smart_speed_on, 2847 ixgbe_smart_speed_off 2848 }; 2849 2850 /* PCI bus types */ 2851 enum ixgbe_bus_type { 2852 ixgbe_bus_type_unknown = 0, 2853 ixgbe_bus_type_pci, 2854 ixgbe_bus_type_pcix, 2855 ixgbe_bus_type_pci_express, 2856 ixgbe_bus_type_reserved 2857 }; 2858 2859 /* PCI bus speeds */ 2860 enum ixgbe_bus_speed { 2861 ixgbe_bus_speed_unknown = 0, 2862 ixgbe_bus_speed_33 = 33, 2863 ixgbe_bus_speed_66 = 66, 2864 ixgbe_bus_speed_100 = 100, 2865 ixgbe_bus_speed_120 = 120, 2866 ixgbe_bus_speed_133 = 133, 2867 ixgbe_bus_speed_2500 = 2500, 2868 ixgbe_bus_speed_5000 = 5000, 2869 ixgbe_bus_speed_8000 = 8000, 2870 ixgbe_bus_speed_reserved 2871 }; 2872 2873 /* PCI bus widths */ 2874 enum ixgbe_bus_width { 2875 ixgbe_bus_width_unknown = 0, 2876 ixgbe_bus_width_pcie_x1 = 1, 2877 ixgbe_bus_width_pcie_x2 = 2, 2878 ixgbe_bus_width_pcie_x4 = 4, 2879 ixgbe_bus_width_pcie_x8 = 8, 2880 ixgbe_bus_width_32 = 32, 2881 ixgbe_bus_width_64 = 64, 2882 ixgbe_bus_width_reserved 2883 }; 2884 2885 struct ixgbe_addr_filter_info { 2886 u32 num_mc_addrs; 2887 u32 rar_used_count; 2888 u32 mta_in_use; 2889 u32 overflow_promisc; 2890 bool uc_set_promisc; 2891 bool user_set_promisc; 2892 }; 2893 2894 /* Bus parameters */ 2895 struct ixgbe_bus_info { 2896 enum ixgbe_bus_speed speed; 2897 enum ixgbe_bus_width width; 2898 enum ixgbe_bus_type type; 2899 2900 u16 func; 2901 u16 lan_id; 2902 }; 2903 2904 /* Flow control parameters */ 2905 struct ixgbe_fc_info { 2906 u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ 2907 u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */ 2908 u16 pause_time; /* Flow Control Pause timer */ 2909 bool send_xon; /* Flow control send XON */ 2910 bool strict_ieee; /* Strict IEEE mode */ 2911 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2912 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2913 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2914 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2915 }; 2916 2917 /* Statistics counters collected by the MAC */ 2918 struct ixgbe_hw_stats { 2919 u64 crcerrs; 2920 u64 illerrc; 2921 u64 errbc; 2922 u64 mspdc; 2923 u64 mpctotal; 2924 u64 mpc[8]; 2925 u64 mlfc; 2926 u64 mrfc; 2927 u64 rlec; 2928 u64 lxontxc; 2929 u64 lxonrxc; 2930 u64 lxofftxc; 2931 u64 lxoffrxc; 2932 u64 pxontxc[8]; 2933 u64 pxonrxc[8]; 2934 u64 pxofftxc[8]; 2935 u64 pxoffrxc[8]; 2936 u64 prc64; 2937 u64 prc127; 2938 u64 prc255; 2939 u64 prc511; 2940 u64 prc1023; 2941 u64 prc1522; 2942 u64 gprc; 2943 u64 bprc; 2944 u64 mprc; 2945 u64 gptc; 2946 u64 gorc; 2947 u64 gotc; 2948 u64 rnbc[8]; 2949 u64 ruc; 2950 u64 rfc; 2951 u64 roc; 2952 u64 rjc; 2953 u64 mngprc; 2954 u64 mngpdc; 2955 u64 mngptc; 2956 u64 tor; 2957 u64 tpr; 2958 u64 tpt; 2959 u64 ptc64; 2960 u64 ptc127; 2961 u64 ptc255; 2962 u64 ptc511; 2963 u64 ptc1023; 2964 u64 ptc1522; 2965 u64 mptc; 2966 u64 bptc; 2967 u64 xec; 2968 u64 rqsmr[16]; 2969 u64 tqsmr[8]; 2970 u64 qprc[16]; 2971 u64 qptc[16]; 2972 u64 qbrc[16]; 2973 u64 qbtc[16]; 2974 u64 qprdc[16]; 2975 u64 pxon2offc[8]; 2976 u64 fdirustat_add; 2977 u64 fdirustat_remove; 2978 u64 fdirfstat_fadd; 2979 u64 fdirfstat_fremove; 2980 u64 fdirmatch; 2981 u64 fdirmiss; 2982 u64 fccrc; 2983 u64 fcoerpdc; 2984 u64 fcoeprc; 2985 u64 fcoeptc; 2986 u64 fcoedwrc; 2987 u64 fcoedwtc; 2988 u64 fcoe_noddp; 2989 u64 fcoe_noddp_ext_buff; 2990 u64 b2ospc; 2991 u64 b2ogprc; 2992 u64 o2bgptc; 2993 u64 o2bspc; 2994 }; 2995 2996 /* forward declaration */ 2997 struct ixgbe_hw; 2998 2999 /* iterator type for walking multicast address lists */ 3000 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 3001 u32 *vmdq); 3002 3003 /* Function pointer table */ 3004 struct ixgbe_eeprom_operations { 3005 s32 (*init_params)(struct ixgbe_hw *); 3006 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 3007 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3008 s32 (*write)(struct ixgbe_hw *, u16, u16); 3009 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3010 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 3011 s32 (*update_checksum)(struct ixgbe_hw *); 3012 s32 (*calc_checksum)(struct ixgbe_hw *); 3013 }; 3014 3015 struct ixgbe_mac_operations { 3016 s32 (*init_hw)(struct ixgbe_hw *); 3017 s32 (*reset_hw)(struct ixgbe_hw *); 3018 s32 (*start_hw)(struct ixgbe_hw *); 3019 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 3020 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3021 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 3022 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 3023 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 3024 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 3025 s32 (*stop_adapter)(struct ixgbe_hw *); 3026 s32 (*get_bus_info)(struct ixgbe_hw *); 3027 void (*set_lan_id)(struct ixgbe_hw *); 3028 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 3029 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 3030 s32 (*setup_sfp)(struct ixgbe_hw *); 3031 s32 (*disable_rx_buff)(struct ixgbe_hw *); 3032 s32 (*enable_rx_buff)(struct ixgbe_hw *); 3033 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 3034 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); 3035 void (*release_swfw_sync)(struct ixgbe_hw *, u32); 3036 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); 3037 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); 3038 3039 /* Link */ 3040 void (*disable_tx_laser)(struct ixgbe_hw *); 3041 void (*enable_tx_laser)(struct ixgbe_hw *); 3042 void (*flap_tx_laser)(struct ixgbe_hw *); 3043 void (*stop_link_on_d3)(struct ixgbe_hw *); 3044 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3045 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3046 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3047 bool *); 3048 3049 /* Packet Buffer Manipulation */ 3050 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); 3051 3052 /* LED */ 3053 s32 (*led_on)(struct ixgbe_hw *, u32); 3054 s32 (*led_off)(struct ixgbe_hw *, u32); 3055 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3056 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3057 3058 /* RAR, Multicast, VLAN */ 3059 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3060 s32 (*clear_rar)(struct ixgbe_hw *, u32); 3061 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 3062 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3063 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3064 s32 (*init_rx_addrs)(struct ixgbe_hw *); 3065 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); 3066 s32 (*enable_mc)(struct ixgbe_hw *); 3067 s32 (*disable_mc)(struct ixgbe_hw *); 3068 s32 (*clear_vfta)(struct ixgbe_hw *); 3069 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 3070 s32 (*init_uta_tables)(struct ixgbe_hw *); 3071 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3072 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3073 3074 /* Flow Control */ 3075 s32 (*fc_enable)(struct ixgbe_hw *); 3076 3077 /* Manageability interface */ 3078 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); 3079 s32 (*get_thermal_sensor_data)(struct ixgbe_hw *); 3080 s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw); 3081 void (*disable_rx)(struct ixgbe_hw *hw); 3082 void (*enable_rx)(struct ixgbe_hw *hw); 3083 void (*set_source_address_pruning)(struct ixgbe_hw *, bool, 3084 unsigned int); 3085 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); 3086 3087 /* DMA Coalescing */ 3088 s32 (*dmac_config)(struct ixgbe_hw *hw); 3089 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 3090 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 3091 }; 3092 3093 struct ixgbe_phy_operations { 3094 s32 (*identify)(struct ixgbe_hw *); 3095 s32 (*identify_sfp)(struct ixgbe_hw *); 3096 s32 (*init)(struct ixgbe_hw *); 3097 s32 (*reset)(struct ixgbe_hw *); 3098 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3099 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 3100 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 3101 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 3102 s32 (*setup_link)(struct ixgbe_hw *); 3103 s32 (*setup_internal_link)(struct ixgbe_hw *); 3104 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3105 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3106 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 3107 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3108 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 3109 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3110 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3111 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3112 s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); 3113 s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); 3114 s32 (*check_overtemp)(struct ixgbe_hw *); 3115 }; 3116 3117 struct ixgbe_eeprom_info { 3118 struct ixgbe_eeprom_operations ops; 3119 enum ixgbe_eeprom_type type; 3120 u32 semaphore_delay; 3121 u16 word_size; 3122 u16 address_bits; 3123 u16 word_page_size; 3124 }; 3125 3126 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 3127 struct ixgbe_mac_info { 3128 struct ixgbe_mac_operations ops; 3129 enum ixgbe_mac_type type; 3130 u8 addr[ETH_ALEN]; 3131 u8 perm_addr[ETH_ALEN]; 3132 u8 san_addr[ETH_ALEN]; 3133 /* prefix for World Wide Node Name (WWNN) */ 3134 u16 wwnn_prefix; 3135 /* prefix for World Wide Port Name (WWPN) */ 3136 u16 wwpn_prefix; 3137 u16 max_msix_vectors; 3138 #define IXGBE_MAX_MTA 128 3139 u32 mta_shadow[IXGBE_MAX_MTA]; 3140 s32 mc_filter_type; 3141 u32 mcft_size; 3142 u32 vft_size; 3143 u32 num_rar_entries; 3144 u32 rar_highwater; 3145 u32 rx_pb_size; 3146 u32 max_tx_queues; 3147 u32 max_rx_queues; 3148 u32 orig_autoc; 3149 u32 orig_autoc2; 3150 bool orig_link_settings_stored; 3151 bool autotry_restart; 3152 u8 flags; 3153 u8 san_mac_rar_index; 3154 struct ixgbe_thermal_sensor_data thermal_sensor_data; 3155 bool set_lben; 3156 }; 3157 3158 struct ixgbe_phy_info { 3159 struct ixgbe_phy_operations ops; 3160 struct mdio_if_info mdio; 3161 enum ixgbe_phy_type type; 3162 u32 id; 3163 enum ixgbe_sfp_type sfp_type; 3164 bool sfp_setup_needed; 3165 u32 revision; 3166 enum ixgbe_media_type media_type; 3167 u8 lan_id; 3168 u32 phy_semaphore_mask; 3169 bool reset_disable; 3170 ixgbe_autoneg_advertised autoneg_advertised; 3171 enum ixgbe_smart_speed smart_speed; 3172 bool smart_speed_active; 3173 bool multispeed_fiber; 3174 bool reset_if_overtemp; 3175 bool qsfp_shared_i2c_bus; 3176 }; 3177 3178 #include "ixgbe_mbx.h" 3179 3180 struct ixgbe_mbx_operations { 3181 s32 (*init_params)(struct ixgbe_hw *hw); 3182 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 3183 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 3184 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3185 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3186 s32 (*check_for_msg)(struct ixgbe_hw *, u16); 3187 s32 (*check_for_ack)(struct ixgbe_hw *, u16); 3188 s32 (*check_for_rst)(struct ixgbe_hw *, u16); 3189 }; 3190 3191 struct ixgbe_mbx_stats { 3192 u32 msgs_tx; 3193 u32 msgs_rx; 3194 3195 u32 acks; 3196 u32 reqs; 3197 u32 rsts; 3198 }; 3199 3200 struct ixgbe_mbx_info { 3201 struct ixgbe_mbx_operations ops; 3202 struct ixgbe_mbx_stats stats; 3203 u32 timeout; 3204 u32 usec_delay; 3205 u32 v2p_mailbox; 3206 u16 size; 3207 }; 3208 3209 struct ixgbe_hw { 3210 u8 __iomem *hw_addr; 3211 void *back; 3212 struct ixgbe_mac_info mac; 3213 struct ixgbe_addr_filter_info addr_ctrl; 3214 struct ixgbe_fc_info fc; 3215 struct ixgbe_phy_info phy; 3216 struct ixgbe_eeprom_info eeprom; 3217 struct ixgbe_bus_info bus; 3218 struct ixgbe_mbx_info mbx; 3219 u16 device_id; 3220 u16 vendor_id; 3221 u16 subsystem_device_id; 3222 u16 subsystem_vendor_id; 3223 u8 revision_id; 3224 bool adapter_stopped; 3225 bool force_full_reset; 3226 bool allow_unsupported_sfp; 3227 bool wol_enabled; 3228 }; 3229 3230 struct ixgbe_info { 3231 enum ixgbe_mac_type mac; 3232 s32 (*get_invariants)(struct ixgbe_hw *); 3233 struct ixgbe_mac_operations *mac_ops; 3234 struct ixgbe_eeprom_operations *eeprom_ops; 3235 struct ixgbe_phy_operations *phy_ops; 3236 struct ixgbe_mbx_operations *mbx_ops; 3237 }; 3238 3239 3240 /* Error Codes */ 3241 #define IXGBE_ERR_EEPROM -1 3242 #define IXGBE_ERR_EEPROM_CHECKSUM -2 3243 #define IXGBE_ERR_PHY -3 3244 #define IXGBE_ERR_CONFIG -4 3245 #define IXGBE_ERR_PARAM -5 3246 #define IXGBE_ERR_MAC_TYPE -6 3247 #define IXGBE_ERR_UNKNOWN_PHY -7 3248 #define IXGBE_ERR_LINK_SETUP -8 3249 #define IXGBE_ERR_ADAPTER_STOPPED -9 3250 #define IXGBE_ERR_INVALID_MAC_ADDR -10 3251 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 3252 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 3253 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 3254 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 3255 #define IXGBE_ERR_RESET_FAILED -15 3256 #define IXGBE_ERR_SWFW_SYNC -16 3257 #define IXGBE_ERR_PHY_ADDR_INVALID -17 3258 #define IXGBE_ERR_I2C -18 3259 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 3260 #define IXGBE_ERR_SFP_NOT_PRESENT -20 3261 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 3262 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 3263 #define IXGBE_ERR_FDIR_REINIT_FAILED -23 3264 #define IXGBE_ERR_EEPROM_VERSION -24 3265 #define IXGBE_ERR_NO_SPACE -25 3266 #define IXGBE_ERR_OVERTEMP -26 3267 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 3268 #define IXGBE_ERR_FC_NOT_SUPPORTED -28 3269 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 3270 #define IXGBE_ERR_PBA_SECTION -31 3271 #define IXGBE_ERR_INVALID_ARGUMENT -32 3272 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 3273 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 3274 3275 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P == 0) ? (0x4010) : (0x8010)) 3276 #define IXGBE_KRM_LINK_CTRL_1(P) ((P == 0) ? (0x420C) : (0x820C)) 3277 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P == 0) ? (0x4634) : (0x8634)) 3278 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P == 0) ? (0x4638) : (0x8638)) 3279 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P == 0) ? (0x4B00) : (0x8B00)) 3280 #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P == 0) ? (0x4E00) : (0x8E00)) 3281 #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P == 0) ? (0x5520) : (0x9520)) 3282 #define IXGBE_KRM_RX_ANA_CTL(P) ((P == 0) ? (0x5A00) : (0x9A00)) 3283 3284 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) 3285 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) 3286 3287 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) 3288 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) 3289 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) 3290 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) 3291 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) 3292 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) 3293 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) 3294 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) 3295 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) 3296 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) 3297 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) 3298 3299 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) 3300 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) 3301 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) 3302 3303 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) 3304 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) 3305 3306 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) 3307 3308 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) 3309 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) 3310 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) 3311 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) 3312 3313 #define IXGBE_KX4_LINK_CNTL_1 0x4C 3314 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16) 3315 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17) 3316 #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24) 3317 #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25) 3318 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29) 3319 #define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30) 3320 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31) 3321 3322 #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 3323 #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 3324 3325 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 3326 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF 3327 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 3328 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ 3329 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) 3330 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 3331 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ 3332 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) 3333 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 3334 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 3335 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 3336 #define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 3337 #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 3338 #define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1 3339 #define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2 3340 #define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3 3341 3342 #endif /* _IXGBE_TYPE_H_ */ 3343