1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
50
51 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
52 (d) == I40E_DEV_ID_QSFP_B || \
53 (d) == I40E_DEV_ID_QSFP_C)
54
55 /* I40E_MASK is a macro used on 32 bit registers */
56 #define I40E_MASK(mask, shift) (mask << shift)
57
58 #define I40E_MAX_VSI_QP 16
59 #define I40E_MAX_VF_VSI 3
60 #define I40E_MAX_CHAINED_RX_BUFFERS 5
61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62
63 /* Max default timeout in ms, */
64 #define I40E_MAX_NVM_TIMEOUT 18000
65
66 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
67 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
68
69 /* forward declaration */
70 struct i40e_hw;
71 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72
73 /* Data type manipulation macros. */
74
75 #define I40E_DESC_UNUSED(R) \
76 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
77 (R)->next_to_clean - (R)->next_to_use - 1)
78
79 /* bitfields for Tx queue mapping in QTX_CTL */
80 #define I40E_QTX_CTL_VF_QUEUE 0x0
81 #define I40E_QTX_CTL_VM_QUEUE 0x1
82 #define I40E_QTX_CTL_PF_QUEUE 0x2
83
84 /* debug masks - set these bits in hw->debug_mask to control output */
85 enum i40e_debug_mask {
86 I40E_DEBUG_INIT = 0x00000001,
87 I40E_DEBUG_RELEASE = 0x00000002,
88
89 I40E_DEBUG_LINK = 0x00000010,
90 I40E_DEBUG_PHY = 0x00000020,
91 I40E_DEBUG_HMC = 0x00000040,
92 I40E_DEBUG_NVM = 0x00000080,
93 I40E_DEBUG_LAN = 0x00000100,
94 I40E_DEBUG_FLOW = 0x00000200,
95 I40E_DEBUG_DCB = 0x00000400,
96 I40E_DEBUG_DIAG = 0x00000800,
97 I40E_DEBUG_FD = 0x00001000,
98
99 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
100 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
101 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
102 I40E_DEBUG_AQ_COMMAND = 0x06000000,
103 I40E_DEBUG_AQ = 0x0F000000,
104
105 I40E_DEBUG_USER = 0xF0000000,
106
107 I40E_DEBUG_ALL = 0xFFFFFFFF
108 };
109
110 /* These are structs for managing the hardware information and the operations.
111 * The structures of function pointers are filled out at init time when we
112 * know for sure exactly which hardware we're working with. This gives us the
113 * flexibility of using the same main driver code but adapting to slightly
114 * different hardware needs as new parts are developed. For this architecture,
115 * the Firmware and AdminQ are intended to insulate the driver from most of the
116 * future changes, but these structures will also do part of the job.
117 */
118 enum i40e_mac_type {
119 I40E_MAC_UNKNOWN = 0,
120 I40E_MAC_X710,
121 I40E_MAC_XL710,
122 I40E_MAC_VF,
123 I40E_MAC_GENERIC,
124 };
125
126 enum i40e_media_type {
127 I40E_MEDIA_TYPE_UNKNOWN = 0,
128 I40E_MEDIA_TYPE_FIBER,
129 I40E_MEDIA_TYPE_BASET,
130 I40E_MEDIA_TYPE_BACKPLANE,
131 I40E_MEDIA_TYPE_CX4,
132 I40E_MEDIA_TYPE_DA,
133 I40E_MEDIA_TYPE_VIRTUAL
134 };
135
136 enum i40e_fc_mode {
137 I40E_FC_NONE = 0,
138 I40E_FC_RX_PAUSE,
139 I40E_FC_TX_PAUSE,
140 I40E_FC_FULL,
141 I40E_FC_PFC,
142 I40E_FC_DEFAULT
143 };
144
145 enum i40e_set_fc_aq_failures {
146 I40E_SET_FC_AQ_FAIL_NONE = 0,
147 I40E_SET_FC_AQ_FAIL_GET = 1,
148 I40E_SET_FC_AQ_FAIL_SET = 2,
149 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
150 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
151 };
152
153 enum i40e_vsi_type {
154 I40E_VSI_MAIN = 0,
155 I40E_VSI_VMDQ1,
156 I40E_VSI_VMDQ2,
157 I40E_VSI_CTRL,
158 I40E_VSI_FCOE,
159 I40E_VSI_MIRROR,
160 I40E_VSI_SRIOV,
161 I40E_VSI_FDIR,
162 I40E_VSI_TYPE_UNKNOWN
163 };
164
165 enum i40e_queue_type {
166 I40E_QUEUE_TYPE_RX = 0,
167 I40E_QUEUE_TYPE_TX,
168 I40E_QUEUE_TYPE_PE_CEQ,
169 I40E_QUEUE_TYPE_UNKNOWN
170 };
171
172 struct i40e_link_status {
173 enum i40e_aq_phy_type phy_type;
174 enum i40e_aq_link_speed link_speed;
175 u8 link_info;
176 u8 an_info;
177 u8 ext_info;
178 u8 loopback;
179 /* is Link Status Event notification to SW enabled */
180 bool lse_enable;
181 u16 max_frame_size;
182 bool crc_enable;
183 u8 pacing;
184 u8 requested_speeds;
185 };
186
187 struct i40e_phy_info {
188 struct i40e_link_status link_info;
189 struct i40e_link_status link_info_old;
190 u32 autoneg_advertised;
191 u32 phy_id;
192 u32 module_type;
193 bool get_link_info;
194 enum i40e_media_type media_type;
195 };
196
197 #define I40E_HW_CAP_MAX_GPIO 30
198 /* Capabilities of a PF or a VF or the whole device */
199 struct i40e_hw_capabilities {
200 u32 switch_mode;
201 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
202 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
203 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
204
205 u32 management_mode;
206 u32 npar_enable;
207 u32 os2bmc;
208 u32 valid_functions;
209 bool sr_iov_1_1;
210 bool vmdq;
211 bool evb_802_1_qbg; /* Edge Virtual Bridging */
212 bool evb_802_1_qbh; /* Bridge Port Extension */
213 bool dcb;
214 bool fcoe;
215 bool iscsi; /* Indicates iSCSI enabled */
216 bool mfp_mode_1;
217 bool mgmt_cem;
218 bool ieee_1588;
219 bool iwarp;
220 bool fd;
221 u32 fd_filters_guaranteed;
222 u32 fd_filters_best_effort;
223 bool rss;
224 u32 rss_table_size;
225 u32 rss_table_entry_width;
226 bool led[I40E_HW_CAP_MAX_GPIO];
227 bool sdp[I40E_HW_CAP_MAX_GPIO];
228 u32 nvm_image_type;
229 u32 num_flow_director_filters;
230 u32 num_vfs;
231 u32 vf_base_id;
232 u32 num_vsis;
233 u32 num_rx_qp;
234 u32 num_tx_qp;
235 u32 base_queue;
236 u32 num_msix_vectors;
237 u32 num_msix_vectors_vf;
238 u32 led_pin_num;
239 u32 sdp_pin_num;
240 u32 mdio_port_num;
241 u32 mdio_port_mode;
242 u8 rx_buf_chain_len;
243 u32 enabled_tcmap;
244 u32 maxtc;
245 u64 wr_csr_prot;
246 };
247
248 struct i40e_mac_info {
249 enum i40e_mac_type type;
250 u8 addr[ETH_ALEN];
251 u8 perm_addr[ETH_ALEN];
252 u8 san_addr[ETH_ALEN];
253 u8 port_addr[ETH_ALEN];
254 u16 max_fcoeq;
255 };
256
257 enum i40e_aq_resources_ids {
258 I40E_NVM_RESOURCE_ID = 1
259 };
260
261 enum i40e_aq_resource_access_type {
262 I40E_RESOURCE_READ = 1,
263 I40E_RESOURCE_WRITE
264 };
265
266 struct i40e_nvm_info {
267 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
268 u32 timeout; /* [ms] */
269 u16 sr_size; /* Shadow RAM size in words */
270 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
271 u16 version; /* NVM package version */
272 u32 eetrack; /* NVM data version */
273 };
274
275 /* definitions used in NVM update support */
276
277 enum i40e_nvmupd_cmd {
278 I40E_NVMUPD_INVALID,
279 I40E_NVMUPD_READ_CON,
280 I40E_NVMUPD_READ_SNT,
281 I40E_NVMUPD_READ_LCB,
282 I40E_NVMUPD_READ_SA,
283 I40E_NVMUPD_WRITE_ERA,
284 I40E_NVMUPD_WRITE_CON,
285 I40E_NVMUPD_WRITE_SNT,
286 I40E_NVMUPD_WRITE_LCB,
287 I40E_NVMUPD_WRITE_SA,
288 I40E_NVMUPD_CSUM_CON,
289 I40E_NVMUPD_CSUM_SA,
290 I40E_NVMUPD_CSUM_LCB,
291 };
292
293 enum i40e_nvmupd_state {
294 I40E_NVMUPD_STATE_INIT,
295 I40E_NVMUPD_STATE_READING,
296 I40E_NVMUPD_STATE_WRITING
297 };
298
299 /* nvm_access definition and its masks/shifts need to be accessible to
300 * application, core driver, and shared code. Where is the right file?
301 */
302 #define I40E_NVM_READ 0xB
303 #define I40E_NVM_WRITE 0xC
304
305 #define I40E_NVM_MOD_PNT_MASK 0xFF
306
307 #define I40E_NVM_TRANS_SHIFT 8
308 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
309 #define I40E_NVM_CON 0x0
310 #define I40E_NVM_SNT 0x1
311 #define I40E_NVM_LCB 0x2
312 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
313 #define I40E_NVM_ERA 0x4
314 #define I40E_NVM_CSUM 0x8
315
316 #define I40E_NVM_ADAPT_SHIFT 16
317 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
318
319 #define I40E_NVMUPD_MAX_DATA 4096
320 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
321
322 struct i40e_nvm_access {
323 u32 command;
324 u32 config;
325 u32 offset; /* in bytes */
326 u32 data_size; /* in bytes */
327 u8 data[1];
328 };
329
330 /* PCI bus types */
331 enum i40e_bus_type {
332 i40e_bus_type_unknown = 0,
333 i40e_bus_type_pci,
334 i40e_bus_type_pcix,
335 i40e_bus_type_pci_express,
336 i40e_bus_type_reserved
337 };
338
339 /* PCI bus speeds */
340 enum i40e_bus_speed {
341 i40e_bus_speed_unknown = 0,
342 i40e_bus_speed_33 = 33,
343 i40e_bus_speed_66 = 66,
344 i40e_bus_speed_100 = 100,
345 i40e_bus_speed_120 = 120,
346 i40e_bus_speed_133 = 133,
347 i40e_bus_speed_2500 = 2500,
348 i40e_bus_speed_5000 = 5000,
349 i40e_bus_speed_8000 = 8000,
350 i40e_bus_speed_reserved
351 };
352
353 /* PCI bus widths */
354 enum i40e_bus_width {
355 i40e_bus_width_unknown = 0,
356 i40e_bus_width_pcie_x1 = 1,
357 i40e_bus_width_pcie_x2 = 2,
358 i40e_bus_width_pcie_x4 = 4,
359 i40e_bus_width_pcie_x8 = 8,
360 i40e_bus_width_32 = 32,
361 i40e_bus_width_64 = 64,
362 i40e_bus_width_reserved
363 };
364
365 /* Bus parameters */
366 struct i40e_bus_info {
367 enum i40e_bus_speed speed;
368 enum i40e_bus_width width;
369 enum i40e_bus_type type;
370
371 u16 func;
372 u16 device;
373 u16 lan_id;
374 };
375
376 /* Flow control (FC) parameters */
377 struct i40e_fc_info {
378 enum i40e_fc_mode current_mode; /* FC mode in effect */
379 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
380 };
381
382 #define I40E_MAX_TRAFFIC_CLASS 8
383 #define I40E_MAX_USER_PRIORITY 8
384 #define I40E_DCBX_MAX_APPS 32
385 #define I40E_LLDPDU_SIZE 1500
386 #define I40E_TLV_STATUS_OPER 0x1
387 #define I40E_TLV_STATUS_SYNC 0x2
388 #define I40E_TLV_STATUS_ERR 0x4
389 #define I40E_CEE_OPER_MAX_APPS 3
390 #define I40E_APP_PROTOID_FCOE 0x8906
391 #define I40E_APP_PROTOID_ISCSI 0x0cbc
392 #define I40E_APP_PROTOID_FIP 0x8914
393 #define I40E_APP_SEL_ETHTYPE 0x1
394 #define I40E_APP_SEL_TCPIP 0x2
395
396 /* CEE or IEEE 802.1Qaz ETS Configuration data */
397 struct i40e_dcb_ets_config {
398 u8 willing;
399 u8 cbs;
400 u8 maxtcs;
401 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
402 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
403 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
404 };
405
406 /* CEE or IEEE 802.1Qaz PFC Configuration data */
407 struct i40e_dcb_pfc_config {
408 u8 willing;
409 u8 mbc;
410 u8 pfccap;
411 u8 pfcenable;
412 };
413
414 /* CEE or IEEE 802.1Qaz Application Priority data */
415 struct i40e_dcb_app_priority_table {
416 u8 priority;
417 u8 selector;
418 u16 protocolid;
419 };
420
421 struct i40e_dcbx_config {
422 u8 dcbx_mode;
423 #define I40E_DCBX_MODE_CEE 0x1
424 #define I40E_DCBX_MODE_IEEE 0x2
425 u32 numapps;
426 struct i40e_dcb_ets_config etscfg;
427 struct i40e_dcb_ets_config etsrec;
428 struct i40e_dcb_pfc_config pfc;
429 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
430 };
431
432 /* Port hardware description */
433 struct i40e_hw {
434 u8 __iomem *hw_addr;
435 void *back;
436
437 /* subsystem structs */
438 struct i40e_phy_info phy;
439 struct i40e_mac_info mac;
440 struct i40e_bus_info bus;
441 struct i40e_nvm_info nvm;
442 struct i40e_fc_info fc;
443
444 /* pci info */
445 u16 device_id;
446 u16 vendor_id;
447 u16 subsystem_device_id;
448 u16 subsystem_vendor_id;
449 u8 revision_id;
450 u8 port;
451 bool adapter_stopped;
452
453 /* capabilities for entire device and PCI func */
454 struct i40e_hw_capabilities dev_caps;
455 struct i40e_hw_capabilities func_caps;
456
457 /* Flow Director shared filter space */
458 u16 fdir_shared_filter_count;
459
460 /* device profile info */
461 u8 pf_id;
462 u16 main_vsi_seid;
463
464 /* for multi-function MACs */
465 u16 partition_id;
466 u16 num_partitions;
467 u16 num_ports;
468
469 /* Closest numa node to the device */
470 u16 numa_node;
471
472 /* Admin Queue info */
473 struct i40e_adminq_info aq;
474
475 /* state of nvm update process */
476 enum i40e_nvmupd_state nvmupd_state;
477
478 /* HMC info */
479 struct i40e_hmc_info hmc; /* HMC info struct */
480
481 /* LLDP/DCBX Status */
482 u16 dcbx_status;
483
484 /* DCBX info */
485 struct i40e_dcbx_config local_dcbx_config;
486 struct i40e_dcbx_config remote_dcbx_config;
487
488 /* debug mask */
489 u32 debug_mask;
490 };
491
i40e_is_vf(struct i40e_hw * hw)492 static inline bool i40e_is_vf(struct i40e_hw *hw)
493 {
494 return hw->mac.type == I40E_MAC_VF;
495 }
496
497 struct i40e_driver_version {
498 u8 major_version;
499 u8 minor_version;
500 u8 build_version;
501 u8 subbuild_version;
502 u8 driver_string[32];
503 };
504
505 /* RX Descriptors */
506 union i40e_16byte_rx_desc {
507 struct {
508 __le64 pkt_addr; /* Packet buffer address */
509 __le64 hdr_addr; /* Header buffer address */
510 } read;
511 struct {
512 struct {
513 struct {
514 union {
515 __le16 mirroring_status;
516 __le16 fcoe_ctx_id;
517 } mirr_fcoe;
518 __le16 l2tag1;
519 } lo_dword;
520 union {
521 __le32 rss; /* RSS Hash */
522 __le32 fd_id; /* Flow director filter id */
523 __le32 fcoe_param; /* FCoE DDP Context id */
524 } hi_dword;
525 } qword0;
526 struct {
527 /* ext status/error/pktype/length */
528 __le64 status_error_len;
529 } qword1;
530 } wb; /* writeback */
531 };
532
533 union i40e_32byte_rx_desc {
534 struct {
535 __le64 pkt_addr; /* Packet buffer address */
536 __le64 hdr_addr; /* Header buffer address */
537 /* bit 0 of hdr_buffer_addr is DD bit */
538 __le64 rsvd1;
539 __le64 rsvd2;
540 } read;
541 struct {
542 struct {
543 struct {
544 union {
545 __le16 mirroring_status;
546 __le16 fcoe_ctx_id;
547 } mirr_fcoe;
548 __le16 l2tag1;
549 } lo_dword;
550 union {
551 __le32 rss; /* RSS Hash */
552 __le32 fcoe_param; /* FCoE DDP Context id */
553 /* Flow director filter id in case of
554 * Programming status desc WB
555 */
556 __le32 fd_id;
557 } hi_dword;
558 } qword0;
559 struct {
560 /* status/error/pktype/length */
561 __le64 status_error_len;
562 } qword1;
563 struct {
564 __le16 ext_status; /* extended status */
565 __le16 rsvd;
566 __le16 l2tag2_1;
567 __le16 l2tag2_2;
568 } qword2;
569 struct {
570 union {
571 __le32 flex_bytes_lo;
572 __le32 pe_status;
573 } lo_dword;
574 union {
575 __le32 flex_bytes_hi;
576 __le32 fd_id;
577 } hi_dword;
578 } qword3;
579 } wb; /* writeback */
580 };
581
582 enum i40e_rx_desc_status_bits {
583 /* Note: These are predefined bit offsets */
584 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
585 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
586 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
587 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
588 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
589 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
590 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
591 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
592 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
593 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
594 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
595 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
596 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
597 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
598 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
599 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
600 };
601
602 #define I40E_RXD_QW1_STATUS_SHIFT 0
603 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
604 << I40E_RXD_QW1_STATUS_SHIFT)
605
606 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
607 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
608 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
609
610 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
611 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
612 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
613
614 enum i40e_rx_desc_fltstat_values {
615 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
616 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
617 I40E_RX_DESC_FLTSTAT_RSV = 2,
618 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
619 };
620
621 #define I40E_RXD_QW1_ERROR_SHIFT 19
622 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
623
624 enum i40e_rx_desc_error_bits {
625 /* Note: These are predefined bit offsets */
626 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
627 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
628 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
629 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
630 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
631 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
632 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
633 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
634 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
635 };
636
637 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
638 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
639 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
640 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
641 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
642 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
643 };
644
645 #define I40E_RXD_QW1_PTYPE_SHIFT 30
646 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
647
648 /* Packet type non-ip values */
649 enum i40e_rx_l2_ptype {
650 I40E_RX_PTYPE_L2_RESERVED = 0,
651 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
652 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
653 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
654 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
655 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
656 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
657 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
658 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
659 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
660 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
661 I40E_RX_PTYPE_L2_ARP = 11,
662 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
663 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
664 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
665 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
666 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
667 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
668 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
669 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
670 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
671 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
672 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
673 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
674 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
675 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
676 };
677
678 struct i40e_rx_ptype_decoded {
679 u32 ptype:8;
680 u32 known:1;
681 u32 outer_ip:1;
682 u32 outer_ip_ver:1;
683 u32 outer_frag:1;
684 u32 tunnel_type:3;
685 u32 tunnel_end_prot:2;
686 u32 tunnel_end_frag:1;
687 u32 inner_prot:4;
688 u32 payload_layer:3;
689 };
690
691 enum i40e_rx_ptype_outer_ip {
692 I40E_RX_PTYPE_OUTER_L2 = 0,
693 I40E_RX_PTYPE_OUTER_IP = 1
694 };
695
696 enum i40e_rx_ptype_outer_ip_ver {
697 I40E_RX_PTYPE_OUTER_NONE = 0,
698 I40E_RX_PTYPE_OUTER_IPV4 = 0,
699 I40E_RX_PTYPE_OUTER_IPV6 = 1
700 };
701
702 enum i40e_rx_ptype_outer_fragmented {
703 I40E_RX_PTYPE_NOT_FRAG = 0,
704 I40E_RX_PTYPE_FRAG = 1
705 };
706
707 enum i40e_rx_ptype_tunnel_type {
708 I40E_RX_PTYPE_TUNNEL_NONE = 0,
709 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
710 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
711 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
712 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
713 };
714
715 enum i40e_rx_ptype_tunnel_end_prot {
716 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
717 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
718 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
719 };
720
721 enum i40e_rx_ptype_inner_prot {
722 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
723 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
724 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
725 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
726 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
727 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
728 };
729
730 enum i40e_rx_ptype_payload_layer {
731 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
732 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
733 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
734 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
735 };
736
737 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
738 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
739 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
740
741 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
742 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
743 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
744
745 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
746 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
747 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
748
749 enum i40e_rx_desc_ext_status_bits {
750 /* Note: These are predefined bit offsets */
751 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
752 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
753 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
754 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
755 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
756 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
757 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
758 };
759
760 enum i40e_rx_desc_pe_status_bits {
761 /* Note: These are predefined bit offsets */
762 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
763 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
764 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
765 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
766 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
767 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
768 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
769 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
770 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
771 };
772
773 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
774 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
775
776 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
777 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
778 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
779
780 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
781 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
782 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
783
784 enum i40e_rx_prog_status_desc_status_bits {
785 /* Note: These are predefined bit offsets */
786 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
787 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
788 };
789
790 enum i40e_rx_prog_status_desc_prog_id_masks {
791 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
792 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
793 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
794 };
795
796 enum i40e_rx_prog_status_desc_error_bits {
797 /* Note: These are predefined bit offsets */
798 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
799 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
800 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
801 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
802 };
803
804 /* TX Descriptor */
805 struct i40e_tx_desc {
806 __le64 buffer_addr; /* Address of descriptor's data buf */
807 __le64 cmd_type_offset_bsz;
808 };
809
810 #define I40E_TXD_QW1_DTYPE_SHIFT 0
811 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
812
813 enum i40e_tx_desc_dtype_value {
814 I40E_TX_DESC_DTYPE_DATA = 0x0,
815 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
816 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
817 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
818 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
819 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
820 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
821 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
822 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
823 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
824 };
825
826 #define I40E_TXD_QW1_CMD_SHIFT 4
827 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
828
829 enum i40e_tx_desc_cmd_bits {
830 I40E_TX_DESC_CMD_EOP = 0x0001,
831 I40E_TX_DESC_CMD_RS = 0x0002,
832 I40E_TX_DESC_CMD_ICRC = 0x0004,
833 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
834 I40E_TX_DESC_CMD_DUMMY = 0x0010,
835 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
836 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
837 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
838 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
839 I40E_TX_DESC_CMD_FCOET = 0x0080,
840 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
841 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
842 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
843 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
844 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
845 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
846 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
847 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
848 };
849
850 #define I40E_TXD_QW1_OFFSET_SHIFT 16
851 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
852 I40E_TXD_QW1_OFFSET_SHIFT)
853
854 enum i40e_tx_desc_length_fields {
855 /* Note: These are predefined bit offsets */
856 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
857 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
858 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
859 };
860
861 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
862 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
863 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
864
865 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
866 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
867
868 /* Context descriptors */
869 struct i40e_tx_context_desc {
870 __le32 tunneling_params;
871 __le16 l2tag2;
872 __le16 rsvd;
873 __le64 type_cmd_tso_mss;
874 };
875
876 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
877 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
878
879 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
880 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
881
882 enum i40e_tx_ctx_desc_cmd_bits {
883 I40E_TX_CTX_DESC_TSO = 0x01,
884 I40E_TX_CTX_DESC_TSYN = 0x02,
885 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
886 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
887 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
888 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
889 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
890 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
891 I40E_TX_CTX_DESC_SWPE = 0x40
892 };
893
894 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
895 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
896 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
897
898 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
899 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
900 I40E_TXD_CTX_QW1_MSS_SHIFT)
901
902 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
903 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
904
905 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
906 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
907 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
908
909 enum i40e_tx_ctx_desc_eipt_offload {
910 I40E_TX_CTX_EXT_IP_NONE = 0x0,
911 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
912 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
913 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
914 };
915
916 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
917 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
918 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
919
920 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
921 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
922
923 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
924 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
925
926 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
927 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
928 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
929
930 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
931
932 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
933 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
934 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
935
936 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
937 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
938 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
939
940 struct i40e_filter_program_desc {
941 __le32 qindex_flex_ptype_vsi;
942 __le32 rsvd;
943 __le32 dtype_cmd_cntindex;
944 __le32 fd_id;
945 };
946 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
947 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
948 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
949 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
950 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
951 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
952 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
953 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
954 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
955
956 /* Packet Classifier Types for filters */
957 enum i40e_filter_pctype {
958 /* Note: Values 0-30 are reserved for future use */
959 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
960 /* Note: Value 32 is reserved for future use */
961 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
962 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
963 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
964 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
965 /* Note: Values 37-40 are reserved for future use */
966 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
967 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
968 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
969 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
970 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
971 /* Note: Value 47 is reserved for future use */
972 I40E_FILTER_PCTYPE_FCOE_OX = 48,
973 I40E_FILTER_PCTYPE_FCOE_RX = 49,
974 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
975 /* Note: Values 51-62 are reserved for future use */
976 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
977 };
978
979 enum i40e_filter_program_desc_dest {
980 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
981 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
982 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
983 };
984
985 enum i40e_filter_program_desc_fd_status {
986 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
987 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
988 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
989 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
990 };
991
992 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
993 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
994 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
995
996 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
997 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
998 I40E_TXD_FLTR_QW1_CMD_SHIFT)
999
1000 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1001 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1002
1003 enum i40e_filter_program_desc_pcmd {
1004 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1005 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1006 };
1007
1008 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1009 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1010
1011 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1012 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1013 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1014
1015 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1016 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1017 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1018 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1019
1020 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1021 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1022 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1023
1024 enum i40e_filter_type {
1025 I40E_FLOW_DIRECTOR_FLTR = 0,
1026 I40E_PE_QUAD_HASH_FLTR = 1,
1027 I40E_ETHERTYPE_FLTR,
1028 I40E_FCOE_CTX_FLTR,
1029 I40E_MAC_VLAN_FLTR,
1030 I40E_HASH_FLTR
1031 };
1032
1033 struct i40e_vsi_context {
1034 u16 seid;
1035 u16 uplink_seid;
1036 u16 vsi_number;
1037 u16 vsis_allocated;
1038 u16 vsis_unallocated;
1039 u16 flags;
1040 u8 pf_num;
1041 u8 vf_num;
1042 u8 connection_type;
1043 struct i40e_aqc_vsi_properties_data info;
1044 };
1045
1046 struct i40e_veb_context {
1047 u16 seid;
1048 u16 uplink_seid;
1049 u16 veb_number;
1050 u16 vebs_allocated;
1051 u16 vebs_unallocated;
1052 u16 flags;
1053 struct i40e_aqc_get_veb_parameters_completion info;
1054 };
1055
1056 /* Statistics collected by each port, VSI, VEB, and S-channel */
1057 struct i40e_eth_stats {
1058 u64 rx_bytes; /* gorc */
1059 u64 rx_unicast; /* uprc */
1060 u64 rx_multicast; /* mprc */
1061 u64 rx_broadcast; /* bprc */
1062 u64 rx_discards; /* rdpc */
1063 u64 rx_unknown_protocol; /* rupp */
1064 u64 tx_bytes; /* gotc */
1065 u64 tx_unicast; /* uptc */
1066 u64 tx_multicast; /* mptc */
1067 u64 tx_broadcast; /* bptc */
1068 u64 tx_discards; /* tdpc */
1069 u64 tx_errors; /* tepc */
1070 };
1071
1072 #ifdef I40E_FCOE
1073 /* Statistics collected per function for FCoE */
1074 struct i40e_fcoe_stats {
1075 u64 rx_fcoe_packets; /* fcoeprc */
1076 u64 rx_fcoe_dwords; /* focedwrc */
1077 u64 rx_fcoe_dropped; /* fcoerpdc */
1078 u64 tx_fcoe_packets; /* fcoeptc */
1079 u64 tx_fcoe_dwords; /* focedwtc */
1080 u64 fcoe_bad_fccrc; /* fcoecrc */
1081 u64 fcoe_last_error; /* fcoelast */
1082 u64 fcoe_ddp_count; /* fcoeddpc */
1083 };
1084
1085 /* offset to per function FCoE statistics block */
1086 #define I40E_FCOE_VF_STAT_OFFSET 0
1087 #define I40E_FCOE_PF_STAT_OFFSET 128
1088 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1089
1090 #endif
1091 /* Statistics collected by the MAC */
1092 struct i40e_hw_port_stats {
1093 /* eth stats collected by the port */
1094 struct i40e_eth_stats eth;
1095
1096 /* additional port specific stats */
1097 u64 tx_dropped_link_down; /* tdold */
1098 u64 crc_errors; /* crcerrs */
1099 u64 illegal_bytes; /* illerrc */
1100 u64 error_bytes; /* errbc */
1101 u64 mac_local_faults; /* mlfc */
1102 u64 mac_remote_faults; /* mrfc */
1103 u64 rx_length_errors; /* rlec */
1104 u64 link_xon_rx; /* lxonrxc */
1105 u64 link_xoff_rx; /* lxoffrxc */
1106 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1107 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1108 u64 link_xon_tx; /* lxontxc */
1109 u64 link_xoff_tx; /* lxofftxc */
1110 u64 priority_xon_tx[8]; /* pxontxc[8] */
1111 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1112 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1113 u64 rx_size_64; /* prc64 */
1114 u64 rx_size_127; /* prc127 */
1115 u64 rx_size_255; /* prc255 */
1116 u64 rx_size_511; /* prc511 */
1117 u64 rx_size_1023; /* prc1023 */
1118 u64 rx_size_1522; /* prc1522 */
1119 u64 rx_size_big; /* prc9522 */
1120 u64 rx_undersize; /* ruc */
1121 u64 rx_fragments; /* rfc */
1122 u64 rx_oversize; /* roc */
1123 u64 rx_jabber; /* rjc */
1124 u64 tx_size_64; /* ptc64 */
1125 u64 tx_size_127; /* ptc127 */
1126 u64 tx_size_255; /* ptc255 */
1127 u64 tx_size_511; /* ptc511 */
1128 u64 tx_size_1023; /* ptc1023 */
1129 u64 tx_size_1522; /* ptc1522 */
1130 u64 tx_size_big; /* ptc9522 */
1131 u64 mac_short_packet_dropped; /* mspdc */
1132 u64 checksum_error; /* xec */
1133 /* flow director stats */
1134 u64 fd_atr_match;
1135 u64 fd_sb_match;
1136 /* EEE LPI */
1137 u32 tx_lpi_status;
1138 u32 rx_lpi_status;
1139 u64 tx_lpi_count; /* etlpic */
1140 u64 rx_lpi_count; /* erlpic */
1141 };
1142
1143 /* Checksum and Shadow RAM pointers */
1144 #define I40E_SR_NVM_CONTROL_WORD 0x00
1145 #define I40E_SR_EMP_MODULE_PTR 0x0F
1146 #define I40E_SR_PBA_FLAGS 0x15
1147 #define I40E_SR_PBA_BLOCK_PTR 0x16
1148 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1149 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1150 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1151 #define I40E_SR_NVM_EETRACK_LO 0x2D
1152 #define I40E_SR_NVM_EETRACK_HI 0x2E
1153 #define I40E_SR_VPD_PTR 0x2F
1154 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1155 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1156
1157 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1158 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1159 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1160 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1161 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1162
1163 /* Shadow RAM related */
1164 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1165 #define I40E_SR_WORDS_IN_1KB 512
1166 /* Checksum should be calculated such that after adding all the words,
1167 * including the checksum word itself, the sum should be 0xBABA.
1168 */
1169 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1170
1171 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1172
1173 #ifdef I40E_FCOE
1174 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1175
1176 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1177 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1178 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1179 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1180 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1181 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1182 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1183 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1184 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1185 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1186 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1187 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1188 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1189 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1190 };
1191
1192 /* FCoE DDP Context descriptor */
1193 struct i40e_fcoe_ddp_context_desc {
1194 __le64 rsvd;
1195 __le64 type_cmd_foff_lsize;
1196 };
1197
1198 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1199 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1200 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1201
1202 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1203 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1204 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1205
1206 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1207 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1208 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1209 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1210 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1211 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1212 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1213 };
1214
1215 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1216 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1217 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1218
1219 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1220 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1221 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1222
1223 /* FCoE DDP/DWO Queue Context descriptor */
1224 struct i40e_fcoe_queue_context_desc {
1225 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1226 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1227 };
1228
1229 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1230 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1231 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1232
1233 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1234 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1235 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1236
1237 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1238 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1239 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1240
1241 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1242 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1243 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1244
1245 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1246 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1247 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1248 };
1249
1250 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1251 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1252 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1253
1254 /* FCoE DDP/DWO Filter Context descriptor */
1255 struct i40e_fcoe_filter_context_desc {
1256 __le32 param;
1257 __le16 seqn;
1258
1259 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1260 __le16 rsvd_dmaindx;
1261
1262 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1263 __le64 flags_rsvd_lanq;
1264 };
1265
1266 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1267 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1268 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1269
1270 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1271 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1272 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1273 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1274 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1275 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1276 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1277 };
1278
1279 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1280 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1281 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1282
1283 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1284 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1285 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1286
1287 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1288 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1289 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1290
1291 #endif /* I40E_FCOE */
1292 enum i40e_switch_element_types {
1293 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1294 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1295 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1296 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1297 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1298 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1299 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1300 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1301 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1302 };
1303
1304 /* Supported EtherType filters */
1305 enum i40e_ether_type_index {
1306 I40E_ETHER_TYPE_1588 = 0,
1307 I40E_ETHER_TYPE_FIP = 1,
1308 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1309 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1310 I40E_ETHER_TYPE_LLDP = 4,
1311 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1312 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1313 I40E_ETHER_TYPE_QCN_CNM = 7,
1314 I40E_ETHER_TYPE_8021X = 8,
1315 I40E_ETHER_TYPE_ARP = 9,
1316 I40E_ETHER_TYPE_RSV1 = 10,
1317 I40E_ETHER_TYPE_RSV2 = 11,
1318 };
1319
1320 /* Filter context base size is 1K */
1321 #define I40E_HASH_FILTER_BASE_SIZE 1024
1322 /* Supported Hash filter values */
1323 enum i40e_hash_filter_size {
1324 I40E_HASH_FILTER_SIZE_1K = 0,
1325 I40E_HASH_FILTER_SIZE_2K = 1,
1326 I40E_HASH_FILTER_SIZE_4K = 2,
1327 I40E_HASH_FILTER_SIZE_8K = 3,
1328 I40E_HASH_FILTER_SIZE_16K = 4,
1329 I40E_HASH_FILTER_SIZE_32K = 5,
1330 I40E_HASH_FILTER_SIZE_64K = 6,
1331 I40E_HASH_FILTER_SIZE_128K = 7,
1332 I40E_HASH_FILTER_SIZE_256K = 8,
1333 I40E_HASH_FILTER_SIZE_512K = 9,
1334 I40E_HASH_FILTER_SIZE_1M = 10,
1335 };
1336
1337 /* DMA context base size is 0.5K */
1338 #define I40E_DMA_CNTX_BASE_SIZE 512
1339 /* Supported DMA context values */
1340 enum i40e_dma_cntx_size {
1341 I40E_DMA_CNTX_SIZE_512 = 0,
1342 I40E_DMA_CNTX_SIZE_1K = 1,
1343 I40E_DMA_CNTX_SIZE_2K = 2,
1344 I40E_DMA_CNTX_SIZE_4K = 3,
1345 I40E_DMA_CNTX_SIZE_8K = 4,
1346 I40E_DMA_CNTX_SIZE_16K = 5,
1347 I40E_DMA_CNTX_SIZE_32K = 6,
1348 I40E_DMA_CNTX_SIZE_64K = 7,
1349 I40E_DMA_CNTX_SIZE_128K = 8,
1350 I40E_DMA_CNTX_SIZE_256K = 9,
1351 };
1352
1353 /* Supported Hash look up table (LUT) sizes */
1354 enum i40e_hash_lut_size {
1355 I40E_HASH_LUT_SIZE_128 = 0,
1356 I40E_HASH_LUT_SIZE_512 = 1,
1357 };
1358
1359 /* Structure to hold a per PF filter control settings */
1360 struct i40e_filter_control_settings {
1361 /* number of PE Quad Hash filter buckets */
1362 enum i40e_hash_filter_size pe_filt_num;
1363 /* number of PE Quad Hash contexts */
1364 enum i40e_dma_cntx_size pe_cntx_num;
1365 /* number of FCoE filter buckets */
1366 enum i40e_hash_filter_size fcoe_filt_num;
1367 /* number of FCoE DDP contexts */
1368 enum i40e_dma_cntx_size fcoe_cntx_num;
1369 /* size of the Hash LUT */
1370 enum i40e_hash_lut_size hash_lut_size;
1371 /* enable FDIR filters for PF and its VFs */
1372 bool enable_fdir;
1373 /* enable Ethertype filters for PF and its VFs */
1374 bool enable_ethtype;
1375 /* enable MAC/VLAN filters for PF and its VFs */
1376 bool enable_macvlan;
1377 };
1378
1379 /* Structure to hold device level control filter counts */
1380 struct i40e_control_filter_stats {
1381 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1382 u16 etype_used; /* Used perfect EtherType filters */
1383 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1384 u16 etype_free; /* Un-used perfect EtherType filters */
1385 };
1386
1387 enum i40e_reset_type {
1388 I40E_RESET_POR = 0,
1389 I40E_RESET_CORER = 1,
1390 I40E_RESET_GLOBR = 2,
1391 I40E_RESET_EMPR = 3,
1392 };
1393
1394 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1395 #define I40E_NVM_LLDP_CFG_PTR 0xD
1396 struct i40e_lldp_variables {
1397 u16 length;
1398 u16 adminstatus;
1399 u16 msgfasttx;
1400 u16 msgtxinterval;
1401 u16 txparams;
1402 u16 timers;
1403 u16 crc8;
1404 };
1405
1406 /* Offsets into Alternate Ram */
1407 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1408 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1409 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1410 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1411 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1412 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1413
1414 /* Alternate Ram Bandwidth Masks */
1415 #define I40E_ALT_BW_VALUE_MASK 0xFF
1416 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1417 #define I40E_ALT_BW_VALID_MASK 0x80000000
1418
1419 /* RSS Hash Table Size */
1420 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1421 #endif /* _I40E_TYPE_H_ */
1422