1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/radeon_drm.h>
36 #include <drm/drm_cache.h>
37 #include "radeon.h"
38 #include "radeon_trace.h"
39
40
41 int radeon_ttm_init(struct radeon_device *rdev);
42 void radeon_ttm_fini(struct radeon_device *rdev);
43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
44
45 /*
46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
47 * function are calling it.
48 */
49
radeon_update_memory_usage(struct radeon_bo * bo,unsigned mem_type,int sign)50 static void radeon_update_memory_usage(struct radeon_bo *bo,
51 unsigned mem_type, int sign)
52 {
53 struct radeon_device *rdev = bo->rdev;
54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
55
56 switch (mem_type) {
57 case TTM_PL_TT:
58 if (sign > 0)
59 atomic64_add(size, &rdev->gtt_usage);
60 else
61 atomic64_sub(size, &rdev->gtt_usage);
62 break;
63 case TTM_PL_VRAM:
64 if (sign > 0)
65 atomic64_add(size, &rdev->vram_usage);
66 else
67 atomic64_sub(size, &rdev->vram_usage);
68 break;
69 }
70 }
71
radeon_ttm_bo_destroy(struct ttm_buffer_object * tbo)72 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
73 {
74 struct radeon_bo *bo;
75
76 bo = container_of(tbo, struct radeon_bo, tbo);
77
78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
79
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON(!list_empty(&bo->va));
85 drm_gem_object_release(&bo->gem_base);
86 kfree(bo);
87 }
88
radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object * bo)89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90 {
91 if (bo->destroy == &radeon_ttm_bo_destroy)
92 return true;
93 return false;
94 }
95
radeon_ttm_placement_from_domain(struct radeon_bo * rbo,u32 domain)96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
97 {
98 u32 c = 0, i;
99
100 rbo->placement.placement = rbo->placements;
101 rbo->placement.busy_placement = rbo->placements;
102 if (domain & RADEON_GEM_DOMAIN_VRAM) {
103 /* Try placing BOs which don't need CPU access outside of the
104 * CPU accessible part of VRAM
105 */
106 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
107 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
108 rbo->placements[c].fpfn =
109 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
110 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
111 TTM_PL_FLAG_UNCACHED |
112 TTM_PL_FLAG_VRAM;
113 }
114
115 rbo->placements[c].fpfn = 0;
116 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
117 TTM_PL_FLAG_UNCACHED |
118 TTM_PL_FLAG_VRAM;
119 }
120
121 if (domain & RADEON_GEM_DOMAIN_GTT) {
122 if (rbo->flags & RADEON_GEM_GTT_UC) {
123 rbo->placements[c].fpfn = 0;
124 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
125 TTM_PL_FLAG_TT;
126
127 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
128 (rbo->rdev->flags & RADEON_IS_AGP)) {
129 rbo->placements[c].fpfn = 0;
130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
132 TTM_PL_FLAG_TT;
133 } else {
134 rbo->placements[c].fpfn = 0;
135 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
136 TTM_PL_FLAG_TT;
137 }
138 }
139
140 if (domain & RADEON_GEM_DOMAIN_CPU) {
141 if (rbo->flags & RADEON_GEM_GTT_UC) {
142 rbo->placements[c].fpfn = 0;
143 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
144 TTM_PL_FLAG_SYSTEM;
145
146 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
147 rbo->rdev->flags & RADEON_IS_AGP) {
148 rbo->placements[c].fpfn = 0;
149 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
150 TTM_PL_FLAG_UNCACHED |
151 TTM_PL_FLAG_SYSTEM;
152 } else {
153 rbo->placements[c].fpfn = 0;
154 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
155 TTM_PL_FLAG_SYSTEM;
156 }
157 }
158 if (!c) {
159 rbo->placements[c].fpfn = 0;
160 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
161 TTM_PL_FLAG_SYSTEM;
162 }
163
164 rbo->placement.num_placement = c;
165 rbo->placement.num_busy_placement = c;
166
167 for (i = 0; i < c; ++i) {
168 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
169 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
170 !rbo->placements[i].fpfn)
171 rbo->placements[i].lpfn =
172 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
173 else
174 rbo->placements[i].lpfn = 0;
175 }
176 }
177
radeon_bo_create(struct radeon_device * rdev,unsigned long size,int byte_align,bool kernel,u32 domain,u32 flags,struct sg_table * sg,struct reservation_object * resv,struct radeon_bo ** bo_ptr)178 int radeon_bo_create(struct radeon_device *rdev,
179 unsigned long size, int byte_align, bool kernel,
180 u32 domain, u32 flags, struct sg_table *sg,
181 struct reservation_object *resv,
182 struct radeon_bo **bo_ptr)
183 {
184 struct radeon_bo *bo;
185 enum ttm_bo_type type;
186 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
187 size_t acc_size;
188 int r;
189
190 size = ALIGN(size, PAGE_SIZE);
191
192 if (kernel) {
193 type = ttm_bo_type_kernel;
194 } else if (sg) {
195 type = ttm_bo_type_sg;
196 } else {
197 type = ttm_bo_type_device;
198 }
199 *bo_ptr = NULL;
200
201 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
202 sizeof(struct radeon_bo));
203
204 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
205 if (bo == NULL)
206 return -ENOMEM;
207 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
208 if (unlikely(r)) {
209 kfree(bo);
210 return r;
211 }
212 bo->rdev = rdev;
213 bo->surface_reg = -1;
214 INIT_LIST_HEAD(&bo->list);
215 INIT_LIST_HEAD(&bo->va);
216 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
217 RADEON_GEM_DOMAIN_GTT |
218 RADEON_GEM_DOMAIN_CPU);
219
220 bo->flags = flags;
221 /* PCI GART is always snooped */
222 if (!(rdev->flags & RADEON_IS_PCIE))
223 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
224
225 #ifdef CONFIG_X86_32
226 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
227 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
228 */
229 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
230 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
231 /* Don't try to enable write-combining when it can't work, or things
232 * may be slow
233 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
234 */
235
236 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
237 thanks to write-combining
238
239 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
240 "better performance thanks to write-combining\n");
241 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
242 #else
243 /* For architectures that don't support WC memory,
244 * mask out the WC flag from the BO
245 */
246 if (!drm_arch_can_wc_memory())
247 bo->flags &= ~RADEON_GEM_GTT_WC;
248 #endif
249
250 radeon_ttm_placement_from_domain(bo, domain);
251 /* Kernel allocation are uninterruptible */
252 down_read(&rdev->pm.mclk_lock);
253 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
254 &bo->placement, page_align, !kernel, NULL,
255 acc_size, sg, resv, &radeon_ttm_bo_destroy);
256 up_read(&rdev->pm.mclk_lock);
257 if (unlikely(r != 0)) {
258 return r;
259 }
260 *bo_ptr = bo;
261
262 trace_radeon_bo_create(bo);
263
264 return 0;
265 }
266
radeon_bo_kmap(struct radeon_bo * bo,void ** ptr)267 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
268 {
269 bool is_iomem;
270 int r;
271
272 if (bo->kptr) {
273 if (ptr) {
274 *ptr = bo->kptr;
275 }
276 return 0;
277 }
278 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
279 if (r) {
280 return r;
281 }
282 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
283 if (ptr) {
284 *ptr = bo->kptr;
285 }
286 radeon_bo_check_tiling(bo, 0, 0);
287 return 0;
288 }
289
radeon_bo_kunmap(struct radeon_bo * bo)290 void radeon_bo_kunmap(struct radeon_bo *bo)
291 {
292 if (bo->kptr == NULL)
293 return;
294 bo->kptr = NULL;
295 radeon_bo_check_tiling(bo, 0, 0);
296 ttm_bo_kunmap(&bo->kmap);
297 }
298
radeon_bo_ref(struct radeon_bo * bo)299 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
300 {
301 if (bo == NULL)
302 return NULL;
303
304 ttm_bo_reference(&bo->tbo);
305 return bo;
306 }
307
radeon_bo_unref(struct radeon_bo ** bo)308 void radeon_bo_unref(struct radeon_bo **bo)
309 {
310 struct ttm_buffer_object *tbo;
311 struct radeon_device *rdev;
312
313 if ((*bo) == NULL)
314 return;
315 rdev = (*bo)->rdev;
316 tbo = &((*bo)->tbo);
317 ttm_bo_unref(&tbo);
318 if (tbo == NULL)
319 *bo = NULL;
320 }
321
radeon_bo_pin_restricted(struct radeon_bo * bo,u32 domain,u64 max_offset,u64 * gpu_addr)322 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
323 u64 *gpu_addr)
324 {
325 int r, i;
326
327 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
328 return -EPERM;
329
330 if (bo->pin_count) {
331 bo->pin_count++;
332 if (gpu_addr)
333 *gpu_addr = radeon_bo_gpu_offset(bo);
334
335 if (max_offset != 0) {
336 u64 domain_start;
337
338 if (domain == RADEON_GEM_DOMAIN_VRAM)
339 domain_start = bo->rdev->mc.vram_start;
340 else
341 domain_start = bo->rdev->mc.gtt_start;
342 WARN_ON_ONCE(max_offset <
343 (radeon_bo_gpu_offset(bo) - domain_start));
344 }
345
346 return 0;
347 }
348 radeon_ttm_placement_from_domain(bo, domain);
349 for (i = 0; i < bo->placement.num_placement; i++) {
350 /* force to pin into visible video ram */
351 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
352 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
353 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
354 bo->placements[i].lpfn =
355 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
356 else
357 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
358
359 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
360 }
361
362 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
363 if (likely(r == 0)) {
364 bo->pin_count = 1;
365 if (gpu_addr != NULL)
366 *gpu_addr = radeon_bo_gpu_offset(bo);
367 if (domain == RADEON_GEM_DOMAIN_VRAM)
368 bo->rdev->vram_pin_size += radeon_bo_size(bo);
369 else
370 bo->rdev->gart_pin_size += radeon_bo_size(bo);
371 } else {
372 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
373 }
374 return r;
375 }
376
radeon_bo_pin(struct radeon_bo * bo,u32 domain,u64 * gpu_addr)377 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
378 {
379 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
380 }
381
radeon_bo_unpin(struct radeon_bo * bo)382 int radeon_bo_unpin(struct radeon_bo *bo)
383 {
384 int r, i;
385
386 if (!bo->pin_count) {
387 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
388 return 0;
389 }
390 bo->pin_count--;
391 if (bo->pin_count)
392 return 0;
393 for (i = 0; i < bo->placement.num_placement; i++) {
394 bo->placements[i].lpfn = 0;
395 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
396 }
397 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
398 if (likely(r == 0)) {
399 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
400 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
401 else
402 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
403 } else {
404 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
405 }
406 return r;
407 }
408
radeon_bo_evict_vram(struct radeon_device * rdev)409 int radeon_bo_evict_vram(struct radeon_device *rdev)
410 {
411 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
412 if (0 && (rdev->flags & RADEON_IS_IGP)) {
413 if (rdev->mc.igp_sideport_enabled == false)
414 /* Useless to evict on IGP chips */
415 return 0;
416 }
417 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
418 }
419
radeon_bo_force_delete(struct radeon_device * rdev)420 void radeon_bo_force_delete(struct radeon_device *rdev)
421 {
422 struct radeon_bo *bo, *n;
423
424 if (list_empty(&rdev->gem.objects)) {
425 return;
426 }
427 dev_err(rdev->dev, "Userspace still has active objects !\n");
428 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
429 mutex_lock(&rdev->ddev->struct_mutex);
430 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
431 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
432 *((unsigned long *)&bo->gem_base.refcount));
433 mutex_lock(&bo->rdev->gem.mutex);
434 list_del_init(&bo->list);
435 mutex_unlock(&bo->rdev->gem.mutex);
436 /* this should unref the ttm bo */
437 drm_gem_object_unreference(&bo->gem_base);
438 mutex_unlock(&rdev->ddev->struct_mutex);
439 }
440 }
441
radeon_bo_init(struct radeon_device * rdev)442 int radeon_bo_init(struct radeon_device *rdev)
443 {
444 /* Add an MTRR for the VRAM */
445 if (!rdev->fastfb_working) {
446 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
447 rdev->mc.aper_size);
448 }
449 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
450 rdev->mc.mc_vram_size >> 20,
451 (unsigned long long)rdev->mc.aper_size >> 20);
452 DRM_INFO("RAM width %dbits %cDR\n",
453 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
454 return radeon_ttm_init(rdev);
455 }
456
radeon_bo_fini(struct radeon_device * rdev)457 void radeon_bo_fini(struct radeon_device *rdev)
458 {
459 radeon_ttm_fini(rdev);
460 arch_phys_wc_del(rdev->mc.vram_mtrr);
461 }
462
463 /* Returns how many bytes TTM can move per IB.
464 */
radeon_bo_get_threshold_for_moves(struct radeon_device * rdev)465 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
466 {
467 u64 real_vram_size = rdev->mc.real_vram_size;
468 u64 vram_usage = atomic64_read(&rdev->vram_usage);
469
470 /* This function is based on the current VRAM usage.
471 *
472 * - If all of VRAM is free, allow relocating the number of bytes that
473 * is equal to 1/4 of the size of VRAM for this IB.
474
475 * - If more than one half of VRAM is occupied, only allow relocating
476 * 1 MB of data for this IB.
477 *
478 * - From 0 to one half of used VRAM, the threshold decreases
479 * linearly.
480 * __________________
481 * 1/4 of -|\ |
482 * VRAM | \ |
483 * | \ |
484 * | \ |
485 * | \ |
486 * | \ |
487 * | \ |
488 * | \________|1 MB
489 * |----------------|
490 * VRAM 0 % 100 %
491 * used used
492 *
493 * Note: It's a threshold, not a limit. The threshold must be crossed
494 * for buffer relocations to stop, so any buffer of an arbitrary size
495 * can be moved as long as the threshold isn't crossed before
496 * the relocation takes place. We don't want to disable buffer
497 * relocations completely.
498 *
499 * The idea is that buffers should be placed in VRAM at creation time
500 * and TTM should only do a minimum number of relocations during
501 * command submission. In practice, you need to submit at least
502 * a dozen IBs to move all buffers to VRAM if they are in GTT.
503 *
504 * Also, things can get pretty crazy under memory pressure and actual
505 * VRAM usage can change a lot, so playing safe even at 50% does
506 * consistently increase performance.
507 */
508
509 u64 half_vram = real_vram_size >> 1;
510 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
511 u64 bytes_moved_threshold = half_free_vram >> 1;
512 return max(bytes_moved_threshold, 1024*1024ull);
513 }
514
radeon_bo_list_validate(struct radeon_device * rdev,struct ww_acquire_ctx * ticket,struct list_head * head,int ring)515 int radeon_bo_list_validate(struct radeon_device *rdev,
516 struct ww_acquire_ctx *ticket,
517 struct list_head *head, int ring)
518 {
519 struct radeon_bo_list *lobj;
520 struct list_head duplicates;
521 int r;
522 u64 bytes_moved = 0, initial_bytes_moved;
523 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
524
525 INIT_LIST_HEAD(&duplicates);
526 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
527 if (unlikely(r != 0)) {
528 return r;
529 }
530
531 list_for_each_entry(lobj, head, tv.head) {
532 struct radeon_bo *bo = lobj->robj;
533 if (!bo->pin_count) {
534 u32 domain = lobj->prefered_domains;
535 u32 allowed = lobj->allowed_domains;
536 u32 current_domain =
537 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
538
539 /* Check if this buffer will be moved and don't move it
540 * if we have moved too many buffers for this IB already.
541 *
542 * Note that this allows moving at least one buffer of
543 * any size, because it doesn't take the current "bo"
544 * into account. We don't want to disallow buffer moves
545 * completely.
546 */
547 if ((allowed & current_domain) != 0 &&
548 (domain & current_domain) == 0 && /* will be moved */
549 bytes_moved > bytes_moved_threshold) {
550 /* don't move it */
551 domain = current_domain;
552 }
553
554 retry:
555 radeon_ttm_placement_from_domain(bo, domain);
556 if (ring == R600_RING_TYPE_UVD_INDEX)
557 radeon_uvd_force_into_uvd_segment(bo, allowed);
558
559 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
560 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
561 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
562 initial_bytes_moved;
563
564 if (unlikely(r)) {
565 if (r != -ERESTARTSYS &&
566 domain != lobj->allowed_domains) {
567 domain = lobj->allowed_domains;
568 goto retry;
569 }
570 ttm_eu_backoff_reservation(ticket, head);
571 return r;
572 }
573 }
574 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
575 lobj->tiling_flags = bo->tiling_flags;
576 }
577
578 list_for_each_entry(lobj, &duplicates, tv.head) {
579 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
580 lobj->tiling_flags = lobj->robj->tiling_flags;
581 }
582
583 return 0;
584 }
585
radeon_bo_get_surface_reg(struct radeon_bo * bo)586 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
587 {
588 struct radeon_device *rdev = bo->rdev;
589 struct radeon_surface_reg *reg;
590 struct radeon_bo *old_object;
591 int steal;
592 int i;
593
594 lockdep_assert_held(&bo->tbo.resv->lock.base);
595
596 if (!bo->tiling_flags)
597 return 0;
598
599 if (bo->surface_reg >= 0) {
600 reg = &rdev->surface_regs[bo->surface_reg];
601 i = bo->surface_reg;
602 goto out;
603 }
604
605 steal = -1;
606 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
607
608 reg = &rdev->surface_regs[i];
609 if (!reg->bo)
610 break;
611
612 old_object = reg->bo;
613 if (old_object->pin_count == 0)
614 steal = i;
615 }
616
617 /* if we are all out */
618 if (i == RADEON_GEM_MAX_SURFACES) {
619 if (steal == -1)
620 return -ENOMEM;
621 /* find someone with a surface reg and nuke their BO */
622 reg = &rdev->surface_regs[steal];
623 old_object = reg->bo;
624 /* blow away the mapping */
625 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
626 ttm_bo_unmap_virtual(&old_object->tbo);
627 old_object->surface_reg = -1;
628 i = steal;
629 }
630
631 bo->surface_reg = i;
632 reg->bo = bo;
633
634 out:
635 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
636 bo->tbo.mem.start << PAGE_SHIFT,
637 bo->tbo.num_pages << PAGE_SHIFT);
638 return 0;
639 }
640
radeon_bo_clear_surface_reg(struct radeon_bo * bo)641 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
642 {
643 struct radeon_device *rdev = bo->rdev;
644 struct radeon_surface_reg *reg;
645
646 if (bo->surface_reg == -1)
647 return;
648
649 reg = &rdev->surface_regs[bo->surface_reg];
650 radeon_clear_surface_reg(rdev, bo->surface_reg);
651
652 reg->bo = NULL;
653 bo->surface_reg = -1;
654 }
655
radeon_bo_set_tiling_flags(struct radeon_bo * bo,uint32_t tiling_flags,uint32_t pitch)656 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
657 uint32_t tiling_flags, uint32_t pitch)
658 {
659 struct radeon_device *rdev = bo->rdev;
660 int r;
661
662 if (rdev->family >= CHIP_CEDAR) {
663 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
664
665 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
666 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
667 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
668 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
669 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
670 switch (bankw) {
671 case 0:
672 case 1:
673 case 2:
674 case 4:
675 case 8:
676 break;
677 default:
678 return -EINVAL;
679 }
680 switch (bankh) {
681 case 0:
682 case 1:
683 case 2:
684 case 4:
685 case 8:
686 break;
687 default:
688 return -EINVAL;
689 }
690 switch (mtaspect) {
691 case 0:
692 case 1:
693 case 2:
694 case 4:
695 case 8:
696 break;
697 default:
698 return -EINVAL;
699 }
700 if (tilesplit > 6) {
701 return -EINVAL;
702 }
703 if (stilesplit > 6) {
704 return -EINVAL;
705 }
706 }
707 r = radeon_bo_reserve(bo, false);
708 if (unlikely(r != 0))
709 return r;
710 bo->tiling_flags = tiling_flags;
711 bo->pitch = pitch;
712 radeon_bo_unreserve(bo);
713 return 0;
714 }
715
radeon_bo_get_tiling_flags(struct radeon_bo * bo,uint32_t * tiling_flags,uint32_t * pitch)716 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
717 uint32_t *tiling_flags,
718 uint32_t *pitch)
719 {
720 lockdep_assert_held(&bo->tbo.resv->lock.base);
721
722 if (tiling_flags)
723 *tiling_flags = bo->tiling_flags;
724 if (pitch)
725 *pitch = bo->pitch;
726 }
727
radeon_bo_check_tiling(struct radeon_bo * bo,bool has_moved,bool force_drop)728 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
729 bool force_drop)
730 {
731 if (!force_drop)
732 lockdep_assert_held(&bo->tbo.resv->lock.base);
733
734 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
735 return 0;
736
737 if (force_drop) {
738 radeon_bo_clear_surface_reg(bo);
739 return 0;
740 }
741
742 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
743 if (!has_moved)
744 return 0;
745
746 if (bo->surface_reg >= 0)
747 radeon_bo_clear_surface_reg(bo);
748 return 0;
749 }
750
751 if ((bo->surface_reg >= 0) && !has_moved)
752 return 0;
753
754 return radeon_bo_get_surface_reg(bo);
755 }
756
radeon_bo_move_notify(struct ttm_buffer_object * bo,struct ttm_mem_reg * new_mem)757 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
758 struct ttm_mem_reg *new_mem)
759 {
760 struct radeon_bo *rbo;
761
762 if (!radeon_ttm_bo_is_radeon_bo(bo))
763 return;
764
765 rbo = container_of(bo, struct radeon_bo, tbo);
766 radeon_bo_check_tiling(rbo, 0, 1);
767 radeon_vm_bo_invalidate(rbo->rdev, rbo);
768
769 /* update statistics */
770 if (!new_mem)
771 return;
772
773 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
774 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
775 }
776
radeon_bo_fault_reserve_notify(struct ttm_buffer_object * bo)777 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
778 {
779 struct radeon_device *rdev;
780 struct radeon_bo *rbo;
781 unsigned long offset, size, lpfn;
782 int i, r;
783
784 if (!radeon_ttm_bo_is_radeon_bo(bo))
785 return 0;
786 rbo = container_of(bo, struct radeon_bo, tbo);
787 radeon_bo_check_tiling(rbo, 0, 0);
788 rdev = rbo->rdev;
789 if (bo->mem.mem_type != TTM_PL_VRAM)
790 return 0;
791
792 size = bo->mem.num_pages << PAGE_SHIFT;
793 offset = bo->mem.start << PAGE_SHIFT;
794 if ((offset + size) <= rdev->mc.visible_vram_size)
795 return 0;
796
797 /* hurrah the memory is not visible ! */
798 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
799 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
800 for (i = 0; i < rbo->placement.num_placement; i++) {
801 /* Force into visible VRAM */
802 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
803 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
804 rbo->placements[i].lpfn = lpfn;
805 }
806 r = ttm_bo_validate(bo, &rbo->placement, false, false);
807 if (unlikely(r == -ENOMEM)) {
808 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
809 return ttm_bo_validate(bo, &rbo->placement, false, false);
810 } else if (unlikely(r != 0)) {
811 return r;
812 }
813
814 offset = bo->mem.start << PAGE_SHIFT;
815 /* this should never happen */
816 if ((offset + size) > rdev->mc.visible_vram_size)
817 return -EINVAL;
818
819 return 0;
820 }
821
radeon_bo_wait(struct radeon_bo * bo,u32 * mem_type,bool no_wait)822 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
823 {
824 int r;
825
826 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
827 if (unlikely(r != 0))
828 return r;
829 if (mem_type)
830 *mem_type = bo->tbo.mem.mem_type;
831
832 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
833 ttm_bo_unreserve(&bo->tbo);
834 return r;
835 }
836
837 /**
838 * radeon_bo_fence - add fence to buffer object
839 *
840 * @bo: buffer object in question
841 * @fence: fence to add
842 * @shared: true if fence should be added shared
843 *
844 */
radeon_bo_fence(struct radeon_bo * bo,struct radeon_fence * fence,bool shared)845 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
846 bool shared)
847 {
848 struct reservation_object *resv = bo->tbo.resv;
849
850 if (shared)
851 reservation_object_add_shared_fence(resv, &fence->base);
852 else
853 reservation_object_add_excl_fence(resv, &fence->base);
854 }
855