1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2014 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #include "qla_def.h"
8 
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20 
21 #include "qla_target.h"
22 
23 /*
24  * Driver version
25  */
26 char qla2x00_version_str[40];
27 
28 static int apidev_major;
29 
30 /*
31  * SRB allocation cache
32  */
33 static struct kmem_cache *srb_cachep;
34 
35 /*
36  * CT6 CTX allocation cache
37  */
38 static struct kmem_cache *ctx_cachep;
39 /*
40  * error level for logging
41  */
42 int ql_errlev = ql_log_all;
43 
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 		"Specify if Class 2 operations are supported from the very "
48 		"beginning. Default is 0 - class 2 not supported.");
49 
50 
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 		"Login timeout value in seconds.");
55 
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 		"Maximum number of command retries to a port that returns "
60 		"a PORT-DOWN status.");
61 
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 		"Option to enable PLOGI to devices that are not present after "
66 		"a Fabric scan.  This is needed for several broken switches. "
67 		"Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68 
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 		"Specify an alternate value for the NVRAM login retry count.");
73 
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 		"Option to enable allocation of memory for a firmware dump "
78 		"during HBA initialization.  Memory allocation requirements "
79 		"vary by ISP type.  Default is 1 - allocate memory.");
80 
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 		"Option to enable extended error logging,\n"
85 		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
86 		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
88 		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
89 		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
90 		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
91 		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
92 		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
93 		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
94 		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
95 		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 		"\t\t0x1e400000 - Preferred value for capturing essential "
97 		"debug information (equivalent to old "
98 		"ql2xextended_error_logging=1).\n"
99 		"\t\tDo LOGICAL OR of the value to enable more than one level");
100 
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 		"Set to control shifting of command type processing "
105 		"based on total number of SG elements.");
106 
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 		"Enables FDMI registrations. "
111 		"0 - no FDMI. Default is 1 - perform FDMI.");
112 
113 #define MAX_Q_DEPTH	32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 		"Maximum queue depth to set for each LUN. "
118 		"Default is 32.");
119 
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 		" Enable T10-CRC-DIF:\n"
124 		" Default is 2.\n"
125 		"  0 -- No DIF Support\n"
126 		"  1 -- Enable DIF for all types\n"
127 		"  2 -- Enable DIF for all types, except Type 0.\n");
128 
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 		" Enable T10-CRC-DIF Error isolation by HBA:\n"
133 		" Default is 2.\n"
134 		"  0 -- Error isolation disabled\n"
135 		"  1 -- Error isolation enabled only for DIX Type 0\n"
136 		"  2 -- Error isolation enabled for all Types\n");
137 
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 		"Enables iIDMA settings "
142 		"Default is 1 - perform iIDMA. 0 - no iIDMA.");
143 
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 		"Enables MQ settings "
148 		"Default is 1 for single queue. Set it to number "
149 		"of queues in MQ mode.");
150 
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 		"Enables CPU affinity settings for the driver "
155 		"Default is 0 for no affinity of request and response IO. "
156 		"Set it to 1 to turn on the cpu affinity.");
157 
158 int ql2xfwloadbin;
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 		"Option to specify location from which to load ISP firmware:.\n"
162 		" 2 -- load firmware via the request_firmware() (hotplug).\n"
163 		"      interface.\n"
164 		" 1 -- load firmware from flash.\n"
165 		" 0 -- use default semantics.\n");
166 
167 int ql2xetsenable;
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 		"Enables firmware ETS burst."
171 		"Default is 0 - skip ETS enablement.");
172 
173 int ql2xdbwr = 1;
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 		"Option to specify scheme for request queue posting.\n"
177 		" 0 -- Regular doorbell.\n"
178 		" 1 -- CAMRAM doorbell (faster).\n");
179 
180 int ql2xtargetreset = 1;
181 module_param(ql2xtargetreset, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xtargetreset,
183 		 "Enable target reset."
184 		 "Default is 1 - use hw defaults.");
185 
186 int ql2xgffidenable;
187 module_param(ql2xgffidenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xgffidenable,
189 		"Enables GFF_ID checks of port type. "
190 		"Default is 0 - Do not use GFF_ID information.");
191 
192 int ql2xasynctmfenable;
193 module_param(ql2xasynctmfenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xasynctmfenable,
195 		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 		"Default is 0 - Issue TM IOCBs via mailbox mechanism.");
197 
198 int ql2xdontresethba;
199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdontresethba,
201 		"Option to specify reset behaviour.\n"
202 		" 0 (Default) -- Reset on failure.\n"
203 		" 1 -- Do not reset on failure.\n");
204 
205 uint64_t ql2xmaxlun = MAX_LUNS;
206 module_param(ql2xmaxlun, ullong, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmaxlun,
208 		"Defines the maximum LU number to register with the SCSI "
209 		"midlayer. Default is 65535.");
210 
211 int ql2xmdcapmask = 0x1F;
212 module_param(ql2xmdcapmask, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdcapmask,
214 		"Set the Minidump driver capture mask level. "
215 		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
216 
217 int ql2xmdenable = 1;
218 module_param(ql2xmdenable, int, S_IRUGO);
219 MODULE_PARM_DESC(ql2xmdenable,
220 		"Enable/disable MiniDump. "
221 		"0 - MiniDump disabled. "
222 		"1 (Default) - MiniDump enabled.");
223 
224 /*
225  * SCSI host template entry points
226  */
227 static int qla2xxx_slave_configure(struct scsi_device * device);
228 static int qla2xxx_slave_alloc(struct scsi_device *);
229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230 static void qla2xxx_scan_start(struct Scsi_Host *);
231 static void qla2xxx_slave_destroy(struct scsi_device *);
232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
238 
239 static void qla2x00_clear_drv_active(struct qla_hw_data *);
240 static void qla2x00_free_device(scsi_qla_host_t *);
241 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
242 
243 struct scsi_host_template qla2xxx_driver_template = {
244 	.module			= THIS_MODULE,
245 	.name			= QLA2XXX_DRIVER_NAME,
246 	.queuecommand		= qla2xxx_queuecommand,
247 
248 	.eh_abort_handler	= qla2xxx_eh_abort,
249 	.eh_device_reset_handler = qla2xxx_eh_device_reset,
250 	.eh_target_reset_handler = qla2xxx_eh_target_reset,
251 	.eh_bus_reset_handler	= qla2xxx_eh_bus_reset,
252 	.eh_host_reset_handler	= qla2xxx_eh_host_reset,
253 
254 	.slave_configure	= qla2xxx_slave_configure,
255 
256 	.slave_alloc		= qla2xxx_slave_alloc,
257 	.slave_destroy		= qla2xxx_slave_destroy,
258 	.scan_finished		= qla2xxx_scan_finished,
259 	.scan_start		= qla2xxx_scan_start,
260 	.change_queue_depth	= scsi_change_queue_depth,
261 	.this_id		= -1,
262 	.cmd_per_lun		= 3,
263 	.use_clustering		= ENABLE_CLUSTERING,
264 	.sg_tablesize		= SG_ALL,
265 
266 	.max_sectors		= 0xFFFF,
267 	.shost_attrs		= qla2x00_host_attrs,
268 
269 	.supported_mode		= MODE_INITIATOR,
270 	.track_queue_depth	= 1,
271 };
272 
273 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
274 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
275 
276 /* TODO Convert to inlines
277  *
278  * Timer routines
279  */
280 
281 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,void * func,unsigned long interval)282 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
283 {
284 	init_timer(&vha->timer);
285 	vha->timer.expires = jiffies + interval * HZ;
286 	vha->timer.data = (unsigned long)vha;
287 	vha->timer.function = (void (*)(unsigned long))func;
288 	add_timer(&vha->timer);
289 	vha->timer_active = 1;
290 }
291 
292 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)293 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
294 {
295 	/* Currently used for 82XX only. */
296 	if (vha->device_flags & DFLG_DEV_FAILED) {
297 		ql_dbg(ql_dbg_timer, vha, 0x600d,
298 		    "Device in a failed state, returning.\n");
299 		return;
300 	}
301 
302 	mod_timer(&vha->timer, jiffies + interval * HZ);
303 }
304 
305 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)306 qla2x00_stop_timer(scsi_qla_host_t *vha)
307 {
308 	del_timer_sync(&vha->timer);
309 	vha->timer_active = 0;
310 }
311 
312 static int qla2x00_do_dpc(void *data);
313 
314 static void qla2x00_rst_aen(scsi_qla_host_t *);
315 
316 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
317 	struct req_que **, struct rsp_que **);
318 static void qla2x00_free_fw_dump(struct qla_hw_data *);
319 static void qla2x00_mem_free(struct qla_hw_data *);
320 
321 /* -------------------------------------------------------------------------- */
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)322 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
323 				struct rsp_que *rsp)
324 {
325 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
326 	ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
327 				GFP_KERNEL);
328 	if (!ha->req_q_map) {
329 		ql_log(ql_log_fatal, vha, 0x003b,
330 		    "Unable to allocate memory for request queue ptrs.\n");
331 		goto fail_req_map;
332 	}
333 
334 	ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
335 				GFP_KERNEL);
336 	if (!ha->rsp_q_map) {
337 		ql_log(ql_log_fatal, vha, 0x003c,
338 		    "Unable to allocate memory for response queue ptrs.\n");
339 		goto fail_rsp_map;
340 	}
341 	/*
342 	 * Make sure we record at least the request and response queue zero in
343 	 * case we need to free them if part of the probe fails.
344 	 */
345 	ha->rsp_q_map[0] = rsp;
346 	ha->req_q_map[0] = req;
347 	set_bit(0, ha->rsp_qid_map);
348 	set_bit(0, ha->req_qid_map);
349 	return 1;
350 
351 fail_rsp_map:
352 	kfree(ha->req_q_map);
353 	ha->req_q_map = NULL;
354 fail_req_map:
355 	return -ENOMEM;
356 }
357 
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)358 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
359 {
360 	if (IS_QLAFX00(ha)) {
361 		if (req && req->ring_fx00)
362 			dma_free_coherent(&ha->pdev->dev,
363 			    (req->length_fx00 + 1) * sizeof(request_t),
364 			    req->ring_fx00, req->dma_fx00);
365 	} else if (req && req->ring)
366 		dma_free_coherent(&ha->pdev->dev,
367 		(req->length + 1) * sizeof(request_t),
368 		req->ring, req->dma);
369 
370 	if (req)
371 		kfree(req->outstanding_cmds);
372 
373 	kfree(req);
374 	req = NULL;
375 }
376 
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)377 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
378 {
379 	if (IS_QLAFX00(ha)) {
380 		if (rsp && rsp->ring)
381 			dma_free_coherent(&ha->pdev->dev,
382 			    (rsp->length_fx00 + 1) * sizeof(request_t),
383 			    rsp->ring_fx00, rsp->dma_fx00);
384 	} else if (rsp && rsp->ring) {
385 		dma_free_coherent(&ha->pdev->dev,
386 		(rsp->length + 1) * sizeof(response_t),
387 		rsp->ring, rsp->dma);
388 	}
389 	kfree(rsp);
390 	rsp = NULL;
391 }
392 
qla2x00_free_queues(struct qla_hw_data * ha)393 static void qla2x00_free_queues(struct qla_hw_data *ha)
394 {
395 	struct req_que *req;
396 	struct rsp_que *rsp;
397 	int cnt;
398 
399 	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
400 		if (!test_bit(cnt, ha->req_qid_map))
401 			continue;
402 
403 		req = ha->req_q_map[cnt];
404 		qla2x00_free_req_que(ha, req);
405 	}
406 	kfree(ha->req_q_map);
407 	ha->req_q_map = NULL;
408 
409 	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
410 		if (!test_bit(cnt, ha->rsp_qid_map))
411 			continue;
412 
413 		rsp = ha->rsp_q_map[cnt];
414 		qla2x00_free_rsp_que(ha, rsp);
415 	}
416 	kfree(ha->rsp_q_map);
417 	ha->rsp_q_map = NULL;
418 }
419 
qla25xx_setup_mode(struct scsi_qla_host * vha)420 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
421 {
422 	uint16_t options = 0;
423 	int ques, req, ret;
424 	struct qla_hw_data *ha = vha->hw;
425 
426 	if (!(ha->fw_attributes & BIT_6)) {
427 		ql_log(ql_log_warn, vha, 0x00d8,
428 		    "Firmware is not multi-queue capable.\n");
429 		goto fail;
430 	}
431 	if (ql2xmultique_tag) {
432 		/* create a request queue for IO */
433 		options |= BIT_7;
434 		req = qla25xx_create_req_que(ha, options, 0, 0, -1,
435 			QLA_DEFAULT_QUE_QOS);
436 		if (!req) {
437 			ql_log(ql_log_warn, vha, 0x00e0,
438 			    "Failed to create request queue.\n");
439 			goto fail;
440 		}
441 		ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
442 		vha->req = ha->req_q_map[req];
443 		options |= BIT_1;
444 		for (ques = 1; ques < ha->max_rsp_queues; ques++) {
445 			ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
446 			if (!ret) {
447 				ql_log(ql_log_warn, vha, 0x00e8,
448 				    "Failed to create response queue.\n");
449 				goto fail2;
450 			}
451 		}
452 		ha->flags.cpu_affinity_enabled = 1;
453 		ql_dbg(ql_dbg_multiq, vha, 0xc007,
454 		    "CPU affinity mode enabled, "
455 		    "no. of response queues:%d no. of request queues:%d.\n",
456 		    ha->max_rsp_queues, ha->max_req_queues);
457 		ql_dbg(ql_dbg_init, vha, 0x00e9,
458 		    "CPU affinity mode enabled, "
459 		    "no. of response queues:%d no. of request queues:%d.\n",
460 		    ha->max_rsp_queues, ha->max_req_queues);
461 	}
462 	return 0;
463 fail2:
464 	qla25xx_delete_queues(vha);
465 	destroy_workqueue(ha->wq);
466 	ha->wq = NULL;
467 	vha->req = ha->req_q_map[0];
468 fail:
469 	ha->mqenable = 0;
470 	kfree(ha->req_q_map);
471 	kfree(ha->rsp_q_map);
472 	ha->max_req_queues = ha->max_rsp_queues = 1;
473 	return 1;
474 }
475 
476 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str)477 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
478 {
479 	struct qla_hw_data *ha = vha->hw;
480 	static char *pci_bus_modes[] = {
481 		"33", "66", "100", "133",
482 	};
483 	uint16_t pci_bus;
484 
485 	strcpy(str, "PCI");
486 	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
487 	if (pci_bus) {
488 		strcat(str, "-X (");
489 		strcat(str, pci_bus_modes[pci_bus]);
490 	} else {
491 		pci_bus = (ha->pci_attr & BIT_8) >> 8;
492 		strcat(str, " (");
493 		strcat(str, pci_bus_modes[pci_bus]);
494 	}
495 	strcat(str, " MHz)");
496 
497 	return (str);
498 }
499 
500 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str)501 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
502 {
503 	static char *pci_bus_modes[] = { "33", "66", "100", "133", };
504 	struct qla_hw_data *ha = vha->hw;
505 	uint32_t pci_bus;
506 
507 	if (pci_is_pcie(ha->pdev)) {
508 		char lwstr[6];
509 		uint32_t lstat, lspeed, lwidth;
510 
511 		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
512 		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
513 		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
514 
515 		strcpy(str, "PCIe (");
516 		switch (lspeed) {
517 		case 1:
518 			strcat(str, "2.5GT/s ");
519 			break;
520 		case 2:
521 			strcat(str, "5.0GT/s ");
522 			break;
523 		case 3:
524 			strcat(str, "8.0GT/s ");
525 			break;
526 		default:
527 			strcat(str, "<unknown> ");
528 			break;
529 		}
530 		snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
531 		strcat(str, lwstr);
532 
533 		return str;
534 	}
535 
536 	strcpy(str, "PCI");
537 	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
538 	if (pci_bus == 0 || pci_bus == 8) {
539 		strcat(str, " (");
540 		strcat(str, pci_bus_modes[pci_bus >> 3]);
541 	} else {
542 		strcat(str, "-X ");
543 		if (pci_bus & BIT_2)
544 			strcat(str, "Mode 2");
545 		else
546 			strcat(str, "Mode 1");
547 		strcat(str, " (");
548 		strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
549 	}
550 	strcat(str, " MHz)");
551 
552 	return str;
553 }
554 
555 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)556 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
557 {
558 	char un_str[10];
559 	struct qla_hw_data *ha = vha->hw;
560 
561 	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
562 	    ha->fw_minor_version, ha->fw_subminor_version);
563 
564 	if (ha->fw_attributes & BIT_9) {
565 		strcat(str, "FLX");
566 		return (str);
567 	}
568 
569 	switch (ha->fw_attributes & 0xFF) {
570 	case 0x7:
571 		strcat(str, "EF");
572 		break;
573 	case 0x17:
574 		strcat(str, "TP");
575 		break;
576 	case 0x37:
577 		strcat(str, "IP");
578 		break;
579 	case 0x77:
580 		strcat(str, "VI");
581 		break;
582 	default:
583 		sprintf(un_str, "(%x)", ha->fw_attributes);
584 		strcat(str, un_str);
585 		break;
586 	}
587 	if (ha->fw_attributes & 0x100)
588 		strcat(str, "X");
589 
590 	return (str);
591 }
592 
593 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)594 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
595 {
596 	struct qla_hw_data *ha = vha->hw;
597 
598 	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
599 	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
600 	return str;
601 }
602 
603 void
qla2x00_sp_free_dma(void * vha,void * ptr)604 qla2x00_sp_free_dma(void *vha, void *ptr)
605 {
606 	srb_t *sp = (srb_t *)ptr;
607 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
608 	struct qla_hw_data *ha = sp->fcport->vha->hw;
609 	void *ctx = GET_CMD_CTX_SP(sp);
610 
611 	if (sp->flags & SRB_DMA_VALID) {
612 		scsi_dma_unmap(cmd);
613 		sp->flags &= ~SRB_DMA_VALID;
614 	}
615 
616 	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
617 		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
618 		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
619 		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
620 	}
621 
622 	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
623 		/* List assured to be having elements */
624 		qla2x00_clean_dsd_pool(ha, sp, NULL);
625 		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
626 	}
627 
628 	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
629 		dma_pool_free(ha->dl_dma_pool, ctx,
630 		    ((struct crc_context *)ctx)->crc_ctx_dma);
631 		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
632 	}
633 
634 	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
635 		struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
636 
637 		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
638 			ctx1->fcp_cmnd_dma);
639 		list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
640 		ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
641 		ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
642 		mempool_free(ctx1, ha->ctx_mempool);
643 		ctx1 = NULL;
644 	}
645 
646 	CMD_SP(cmd) = NULL;
647 	qla2x00_rel_sp(sp->fcport->vha, sp);
648 }
649 
650 static void
qla2x00_sp_compl(void * data,void * ptr,int res)651 qla2x00_sp_compl(void *data, void *ptr, int res)
652 {
653 	struct qla_hw_data *ha = (struct qla_hw_data *)data;
654 	srb_t *sp = (srb_t *)ptr;
655 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
656 
657 	cmd->result = res;
658 
659 	if (atomic_read(&sp->ref_count) == 0) {
660 		ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
661 		    "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
662 		    sp, GET_CMD_SP(sp));
663 		if (ql2xextended_error_logging & ql_dbg_io)
664 			WARN_ON(atomic_read(&sp->ref_count) == 0);
665 		return;
666 	}
667 	if (!atomic_dec_and_test(&sp->ref_count))
668 		return;
669 
670 	qla2x00_sp_free_dma(ha, sp);
671 	cmd->scsi_done(cmd);
672 }
673 
674 /* If we are SP1 here, we need to still take and release the host_lock as SP1
675  * does not have the changes necessary to avoid taking host->host_lock.
676  */
677 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)678 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
679 {
680 	scsi_qla_host_t *vha = shost_priv(host);
681 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
682 	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
683 	struct qla_hw_data *ha = vha->hw;
684 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
685 	srb_t *sp;
686 	int rval;
687 
688 	if (ha->flags.eeh_busy) {
689 		if (ha->flags.pci_channel_io_perm_failure) {
690 			ql_dbg(ql_dbg_aer, vha, 0x9010,
691 			    "PCI Channel IO permanent failure, exiting "
692 			    "cmd=%p.\n", cmd);
693 			cmd->result = DID_NO_CONNECT << 16;
694 		} else {
695 			ql_dbg(ql_dbg_aer, vha, 0x9011,
696 			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
697 			cmd->result = DID_REQUEUE << 16;
698 		}
699 		goto qc24_fail_command;
700 	}
701 
702 	rval = fc_remote_port_chkready(rport);
703 	if (rval) {
704 		cmd->result = rval;
705 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
706 		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
707 		    cmd, rval);
708 		goto qc24_fail_command;
709 	}
710 
711 	if (!vha->flags.difdix_supported &&
712 		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
713 			ql_dbg(ql_dbg_io, vha, 0x3004,
714 			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
715 			    cmd);
716 			cmd->result = DID_NO_CONNECT << 16;
717 			goto qc24_fail_command;
718 	}
719 
720 	if (!fcport) {
721 		cmd->result = DID_NO_CONNECT << 16;
722 		goto qc24_fail_command;
723 	}
724 
725 	if (atomic_read(&fcport->state) != FCS_ONLINE) {
726 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
727 			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
728 			ql_dbg(ql_dbg_io, vha, 0x3005,
729 			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
730 			    atomic_read(&fcport->state),
731 			    atomic_read(&base_vha->loop_state));
732 			cmd->result = DID_NO_CONNECT << 16;
733 			goto qc24_fail_command;
734 		}
735 		goto qc24_target_busy;
736 	}
737 
738 	/*
739 	 * Return target busy if we've received a non-zero retry_delay_timer
740 	 * in a FCP_RSP.
741 	 */
742 	if (fcport->retry_delay_timestamp == 0) {
743 		/* retry delay not set */
744 	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
745 		fcport->retry_delay_timestamp = 0;
746 	else
747 		goto qc24_target_busy;
748 
749 	sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
750 	if (!sp)
751 		goto qc24_host_busy;
752 
753 	sp->u.scmd.cmd = cmd;
754 	sp->type = SRB_SCSI_CMD;
755 	atomic_set(&sp->ref_count, 1);
756 	CMD_SP(cmd) = (void *)sp;
757 	sp->free = qla2x00_sp_free_dma;
758 	sp->done = qla2x00_sp_compl;
759 
760 	rval = ha->isp_ops->start_scsi(sp);
761 	if (rval != QLA_SUCCESS) {
762 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
763 		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
764 		goto qc24_host_busy_free_sp;
765 	}
766 
767 	return 0;
768 
769 qc24_host_busy_free_sp:
770 	qla2x00_sp_free_dma(ha, sp);
771 
772 qc24_host_busy:
773 	return SCSI_MLQUEUE_HOST_BUSY;
774 
775 qc24_target_busy:
776 	return SCSI_MLQUEUE_TARGET_BUSY;
777 
778 qc24_fail_command:
779 	cmd->scsi_done(cmd);
780 
781 	return 0;
782 }
783 
784 /*
785  * qla2x00_eh_wait_on_command
786  *    Waits for the command to be returned by the Firmware for some
787  *    max time.
788  *
789  * Input:
790  *    cmd = Scsi Command to wait on.
791  *
792  * Return:
793  *    Not Found : 0
794  *    Found : 1
795  */
796 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)797 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
798 {
799 #define ABORT_POLLING_PERIOD	1000
800 #define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
801 	unsigned long wait_iter = ABORT_WAIT_ITER;
802 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
803 	struct qla_hw_data *ha = vha->hw;
804 	int ret = QLA_SUCCESS;
805 
806 	if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
807 		ql_dbg(ql_dbg_taskm, vha, 0x8005,
808 		    "Return:eh_wait.\n");
809 		return ret;
810 	}
811 
812 	while (CMD_SP(cmd) && wait_iter--) {
813 		msleep(ABORT_POLLING_PERIOD);
814 	}
815 	if (CMD_SP(cmd))
816 		ret = QLA_FUNCTION_FAILED;
817 
818 	return ret;
819 }
820 
821 /*
822  * qla2x00_wait_for_hba_online
823  *    Wait till the HBA is online after going through
824  *    <= MAX_RETRIES_OF_ISP_ABORT  or
825  *    finally HBA is disabled ie marked offline
826  *
827  * Input:
828  *     ha - pointer to host adapter structure
829  *
830  * Note:
831  *    Does context switching-Release SPIN_LOCK
832  *    (if any) before calling this routine.
833  *
834  * Return:
835  *    Success (Adapter is online) : 0
836  *    Failed  (Adapter is offline/disabled) : 1
837  */
838 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)839 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
840 {
841 	int		return_status;
842 	unsigned long	wait_online;
843 	struct qla_hw_data *ha = vha->hw;
844 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
845 
846 	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
847 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
848 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
849 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
850 	    ha->dpc_active) && time_before(jiffies, wait_online)) {
851 
852 		msleep(1000);
853 	}
854 	if (base_vha->flags.online)
855 		return_status = QLA_SUCCESS;
856 	else
857 		return_status = QLA_FUNCTION_FAILED;
858 
859 	return (return_status);
860 }
861 
862 /*
863  * qla2x00_wait_for_hba_ready
864  * Wait till the HBA is ready before doing driver unload
865  *
866  * Input:
867  *     ha - pointer to host adapter structure
868  *
869  * Note:
870  *    Does context switching-Release SPIN_LOCK
871  *    (if any) before calling this routine.
872  *
873  */
874 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)875 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
876 {
877 	struct qla_hw_data *ha = vha->hw;
878 
879 	while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
880 	    ha->flags.mbox_busy) ||
881 		test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
882 		test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
883 		msleep(1000);
884 }
885 
886 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)887 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
888 {
889 	int		return_status;
890 	unsigned long	wait_reset;
891 	struct qla_hw_data *ha = vha->hw;
892 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
893 
894 	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
895 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
896 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
897 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
898 	    ha->dpc_active) && time_before(jiffies, wait_reset)) {
899 
900 		msleep(1000);
901 
902 		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
903 		    ha->flags.chip_reset_done)
904 			break;
905 	}
906 	if (ha->flags.chip_reset_done)
907 		return_status = QLA_SUCCESS;
908 	else
909 		return_status = QLA_FUNCTION_FAILED;
910 
911 	return return_status;
912 }
913 
914 static void
sp_get(struct srb * sp)915 sp_get(struct srb *sp)
916 {
917 	atomic_inc(&sp->ref_count);
918 }
919 
920 /**************************************************************************
921 * qla2xxx_eh_abort
922 *
923 * Description:
924 *    The abort function will abort the specified command.
925 *
926 * Input:
927 *    cmd = Linux SCSI command packet to be aborted.
928 *
929 * Returns:
930 *    Either SUCCESS or FAILED.
931 *
932 * Note:
933 *    Only return FAILED if command not returned by firmware.
934 **************************************************************************/
935 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)936 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
937 {
938 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
939 	srb_t *sp;
940 	int ret;
941 	unsigned int id;
942 	uint64_t lun;
943 	unsigned long flags;
944 	int rval, wait = 0;
945 	struct qla_hw_data *ha = vha->hw;
946 
947 	if (!CMD_SP(cmd))
948 		return SUCCESS;
949 
950 	ret = fc_block_scsi_eh(cmd);
951 	if (ret != 0)
952 		return ret;
953 	ret = SUCCESS;
954 
955 	id = cmd->device->id;
956 	lun = cmd->device->lun;
957 
958 	spin_lock_irqsave(&ha->hardware_lock, flags);
959 	sp = (srb_t *) CMD_SP(cmd);
960 	if (!sp) {
961 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
962 		return SUCCESS;
963 	}
964 
965 	ql_dbg(ql_dbg_taskm, vha, 0x8002,
966 	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
967 	    vha->host_no, id, lun, sp, cmd, sp->handle);
968 
969 	/* Get a reference to the sp and drop the lock.*/
970 	sp_get(sp);
971 
972 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
973 	rval = ha->isp_ops->abort_command(sp);
974 	if (rval) {
975 		if (rval == QLA_FUNCTION_PARAMETER_ERROR)
976 			ret = SUCCESS;
977 		else
978 			ret = FAILED;
979 
980 		ql_dbg(ql_dbg_taskm, vha, 0x8003,
981 		    "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
982 	} else {
983 		ql_dbg(ql_dbg_taskm, vha, 0x8004,
984 		    "Abort command mbx success cmd=%p.\n", cmd);
985 		wait = 1;
986 	}
987 
988 	spin_lock_irqsave(&ha->hardware_lock, flags);
989 	sp->done(ha, sp, 0);
990 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
991 
992 	/* Did the command return during mailbox execution? */
993 	if (ret == FAILED && !CMD_SP(cmd))
994 		ret = SUCCESS;
995 
996 	/* Wait for the command to be returned. */
997 	if (wait) {
998 		if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
999 			ql_log(ql_log_warn, vha, 0x8006,
1000 			    "Abort handler timed out cmd=%p.\n", cmd);
1001 			ret = FAILED;
1002 		}
1003 	}
1004 
1005 	ql_log(ql_log_info, vha, 0x801c,
1006 	    "Abort command issued nexus=%ld:%d:%llu --  %d %x.\n",
1007 	    vha->host_no, id, lun, wait, ret);
1008 
1009 	return ret;
1010 }
1011 
1012 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1013 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1014 	uint64_t l, enum nexus_wait_type type)
1015 {
1016 	int cnt, match, status;
1017 	unsigned long flags;
1018 	struct qla_hw_data *ha = vha->hw;
1019 	struct req_que *req;
1020 	srb_t *sp;
1021 	struct scsi_cmnd *cmd;
1022 
1023 	status = QLA_SUCCESS;
1024 
1025 	spin_lock_irqsave(&ha->hardware_lock, flags);
1026 	req = vha->req;
1027 	for (cnt = 1; status == QLA_SUCCESS &&
1028 		cnt < req->num_outstanding_cmds; cnt++) {
1029 		sp = req->outstanding_cmds[cnt];
1030 		if (!sp)
1031 			continue;
1032 		if (sp->type != SRB_SCSI_CMD)
1033 			continue;
1034 		if (vha->vp_idx != sp->fcport->vha->vp_idx)
1035 			continue;
1036 		match = 0;
1037 		cmd = GET_CMD_SP(sp);
1038 		switch (type) {
1039 		case WAIT_HOST:
1040 			match = 1;
1041 			break;
1042 		case WAIT_TARGET:
1043 			match = cmd->device->id == t;
1044 			break;
1045 		case WAIT_LUN:
1046 			match = (cmd->device->id == t &&
1047 				cmd->device->lun == l);
1048 			break;
1049 		}
1050 		if (!match)
1051 			continue;
1052 
1053 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
1054 		status = qla2x00_eh_wait_on_command(cmd);
1055 		spin_lock_irqsave(&ha->hardware_lock, flags);
1056 	}
1057 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1058 
1059 	return status;
1060 }
1061 
1062 static char *reset_errors[] = {
1063 	"HBA not online",
1064 	"HBA not ready",
1065 	"Task management failed",
1066 	"Waiting for command completions",
1067 };
1068 
1069 static int
__qla2xxx_eh_generic_reset(char * name,enum nexus_wait_type type,struct scsi_cmnd * cmd,int (* do_reset)(struct fc_port *,uint64_t,int))1070 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1071     struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1072 {
1073 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1074 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1075 	int err;
1076 
1077 	if (!fcport) {
1078 		return FAILED;
1079 	}
1080 
1081 	err = fc_block_scsi_eh(cmd);
1082 	if (err != 0)
1083 		return err;
1084 
1085 	ql_log(ql_log_info, vha, 0x8009,
1086 	    "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1087 	    cmd->device->id, cmd->device->lun, cmd);
1088 
1089 	err = 0;
1090 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1091 		ql_log(ql_log_warn, vha, 0x800a,
1092 		    "Wait for hba online failed for cmd=%p.\n", cmd);
1093 		goto eh_reset_failed;
1094 	}
1095 	err = 2;
1096 	if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1097 		!= QLA_SUCCESS) {
1098 		ql_log(ql_log_warn, vha, 0x800c,
1099 		    "do_reset failed for cmd=%p.\n", cmd);
1100 		goto eh_reset_failed;
1101 	}
1102 	err = 3;
1103 	if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1104 	    cmd->device->lun, type) != QLA_SUCCESS) {
1105 		ql_log(ql_log_warn, vha, 0x800d,
1106 		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1107 		goto eh_reset_failed;
1108 	}
1109 
1110 	ql_log(ql_log_info, vha, 0x800e,
1111 	    "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1112 	    vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1113 
1114 	return SUCCESS;
1115 
1116 eh_reset_failed:
1117 	ql_log(ql_log_info, vha, 0x800f,
1118 	    "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1119 	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1120 	    cmd);
1121 	return FAILED;
1122 }
1123 
1124 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1125 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1126 {
1127 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1128 	struct qla_hw_data *ha = vha->hw;
1129 
1130 	return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1131 	    ha->isp_ops->lun_reset);
1132 }
1133 
1134 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1135 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1136 {
1137 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1138 	struct qla_hw_data *ha = vha->hw;
1139 
1140 	return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1141 	    ha->isp_ops->target_reset);
1142 }
1143 
1144 /**************************************************************************
1145 * qla2xxx_eh_bus_reset
1146 *
1147 * Description:
1148 *    The bus reset function will reset the bus and abort any executing
1149 *    commands.
1150 *
1151 * Input:
1152 *    cmd = Linux SCSI command packet of the command that cause the
1153 *          bus reset.
1154 *
1155 * Returns:
1156 *    SUCCESS/FAILURE (defined as macro in scsi.h).
1157 *
1158 **************************************************************************/
1159 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1160 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1161 {
1162 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1163 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1164 	int ret = FAILED;
1165 	unsigned int id;
1166 	uint64_t lun;
1167 
1168 	id = cmd->device->id;
1169 	lun = cmd->device->lun;
1170 
1171 	if (!fcport) {
1172 		return ret;
1173 	}
1174 
1175 	ret = fc_block_scsi_eh(cmd);
1176 	if (ret != 0)
1177 		return ret;
1178 	ret = FAILED;
1179 
1180 	ql_log(ql_log_info, vha, 0x8012,
1181 	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1182 
1183 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1184 		ql_log(ql_log_fatal, vha, 0x8013,
1185 		    "Wait for hba online failed board disabled.\n");
1186 		goto eh_bus_reset_done;
1187 	}
1188 
1189 	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1190 		ret = SUCCESS;
1191 
1192 	if (ret == FAILED)
1193 		goto eh_bus_reset_done;
1194 
1195 	/* Flush outstanding commands. */
1196 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1197 	    QLA_SUCCESS) {
1198 		ql_log(ql_log_warn, vha, 0x8014,
1199 		    "Wait for pending commands failed.\n");
1200 		ret = FAILED;
1201 	}
1202 
1203 eh_bus_reset_done:
1204 	ql_log(ql_log_warn, vha, 0x802b,
1205 	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
1206 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1207 
1208 	return ret;
1209 }
1210 
1211 /**************************************************************************
1212 * qla2xxx_eh_host_reset
1213 *
1214 * Description:
1215 *    The reset function will reset the Adapter.
1216 *
1217 * Input:
1218 *      cmd = Linux SCSI command packet of the command that cause the
1219 *            adapter reset.
1220 *
1221 * Returns:
1222 *      Either SUCCESS or FAILED.
1223 *
1224 * Note:
1225 **************************************************************************/
1226 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1227 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1228 {
1229 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1230 	struct qla_hw_data *ha = vha->hw;
1231 	int ret = FAILED;
1232 	unsigned int id;
1233 	uint64_t lun;
1234 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1235 
1236 	id = cmd->device->id;
1237 	lun = cmd->device->lun;
1238 
1239 	ql_log(ql_log_info, vha, 0x8018,
1240 	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1241 
1242 	/*
1243 	 * No point in issuing another reset if one is active.  Also do not
1244 	 * attempt a reset if we are updating flash.
1245 	 */
1246 	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1247 		goto eh_host_reset_lock;
1248 
1249 	if (vha != base_vha) {
1250 		if (qla2x00_vp_abort_isp(vha))
1251 			goto eh_host_reset_lock;
1252 	} else {
1253 		if (IS_P3P_TYPE(vha->hw)) {
1254 			if (!qla82xx_fcoe_ctx_reset(vha)) {
1255 				/* Ctx reset success */
1256 				ret = SUCCESS;
1257 				goto eh_host_reset_lock;
1258 			}
1259 			/* fall thru if ctx reset failed */
1260 		}
1261 		if (ha->wq)
1262 			flush_workqueue(ha->wq);
1263 
1264 		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1265 		if (ha->isp_ops->abort_isp(base_vha)) {
1266 			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1267 			/* failed. schedule dpc to try */
1268 			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1269 
1270 			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1271 				ql_log(ql_log_warn, vha, 0x802a,
1272 				    "wait for hba online failed.\n");
1273 				goto eh_host_reset_lock;
1274 			}
1275 		}
1276 		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1277 	}
1278 
1279 	/* Waiting for command to be returned to OS.*/
1280 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1281 		QLA_SUCCESS)
1282 		ret = SUCCESS;
1283 
1284 eh_host_reset_lock:
1285 	ql_log(ql_log_info, vha, 0x8017,
1286 	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1287 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1288 
1289 	return ret;
1290 }
1291 
1292 /*
1293 * qla2x00_loop_reset
1294 *      Issue loop reset.
1295 *
1296 * Input:
1297 *      ha = adapter block pointer.
1298 *
1299 * Returns:
1300 *      0 = success
1301 */
1302 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1303 qla2x00_loop_reset(scsi_qla_host_t *vha)
1304 {
1305 	int ret;
1306 	struct fc_port *fcport;
1307 	struct qla_hw_data *ha = vha->hw;
1308 
1309 	if (IS_QLAFX00(ha)) {
1310 		return qlafx00_loop_reset(vha);
1311 	}
1312 
1313 	if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1314 		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1315 			if (fcport->port_type != FCT_TARGET)
1316 				continue;
1317 
1318 			ret = ha->isp_ops->target_reset(fcport, 0, 0);
1319 			if (ret != QLA_SUCCESS) {
1320 				ql_dbg(ql_dbg_taskm, vha, 0x802c,
1321 				    "Bus Reset failed: Reset=%d "
1322 				    "d_id=%x.\n", ret, fcport->d_id.b24);
1323 			}
1324 		}
1325 	}
1326 
1327 
1328 	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1329 		atomic_set(&vha->loop_state, LOOP_DOWN);
1330 		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1331 		qla2x00_mark_all_devices_lost(vha, 0);
1332 		ret = qla2x00_full_login_lip(vha);
1333 		if (ret != QLA_SUCCESS) {
1334 			ql_dbg(ql_dbg_taskm, vha, 0x802d,
1335 			    "full_login_lip=%d.\n", ret);
1336 		}
1337 	}
1338 
1339 	if (ha->flags.enable_lip_reset) {
1340 		ret = qla2x00_lip_reset(vha);
1341 		if (ret != QLA_SUCCESS)
1342 			ql_dbg(ql_dbg_taskm, vha, 0x802e,
1343 			    "lip_reset failed (%d).\n", ret);
1344 	}
1345 
1346 	/* Issue marker command only when we are going to start the I/O */
1347 	vha->marker_needed = 1;
1348 
1349 	return QLA_SUCCESS;
1350 }
1351 
1352 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1353 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1354 {
1355 	int que, cnt;
1356 	unsigned long flags;
1357 	srb_t *sp;
1358 	struct qla_hw_data *ha = vha->hw;
1359 	struct req_que *req;
1360 
1361 	qlt_host_reset_handler(ha);
1362 
1363 	spin_lock_irqsave(&ha->hardware_lock, flags);
1364 	for (que = 0; que < ha->max_req_queues; que++) {
1365 		req = ha->req_q_map[que];
1366 		if (!req)
1367 			continue;
1368 		if (!req->outstanding_cmds)
1369 			continue;
1370 		for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1371 			sp = req->outstanding_cmds[cnt];
1372 			if (sp) {
1373 				req->outstanding_cmds[cnt] = NULL;
1374 				sp->done(vha, sp, res);
1375 			}
1376 		}
1377 	}
1378 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1379 }
1380 
1381 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1382 qla2xxx_slave_alloc(struct scsi_device *sdev)
1383 {
1384 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1385 
1386 	if (!rport || fc_remote_port_chkready(rport))
1387 		return -ENXIO;
1388 
1389 	sdev->hostdata = *(fc_port_t **)rport->dd_data;
1390 
1391 	return 0;
1392 }
1393 
1394 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1395 qla2xxx_slave_configure(struct scsi_device *sdev)
1396 {
1397 	scsi_qla_host_t *vha = shost_priv(sdev->host);
1398 	struct req_que *req = vha->req;
1399 
1400 	if (IS_T10_PI_CAPABLE(vha->hw))
1401 		blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1402 
1403 	scsi_change_queue_depth(sdev, req->max_q_depth);
1404 	return 0;
1405 }
1406 
1407 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1408 qla2xxx_slave_destroy(struct scsi_device *sdev)
1409 {
1410 	sdev->hostdata = NULL;
1411 }
1412 
1413 /**
1414  * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1415  * @ha: HA context
1416  *
1417  * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1418  * supported addressing method.
1419  */
1420 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1421 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1422 {
1423 	/* Assume a 32bit DMA mask. */
1424 	ha->flags.enable_64bit_addressing = 0;
1425 
1426 	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1427 		/* Any upper-dword bits set? */
1428 		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1429 		    !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1430 			/* Ok, a 64bit DMA mask is applicable. */
1431 			ha->flags.enable_64bit_addressing = 1;
1432 			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1433 			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1434 			return;
1435 		}
1436 	}
1437 
1438 	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1439 	pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1440 }
1441 
1442 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1443 qla2x00_enable_intrs(struct qla_hw_data *ha)
1444 {
1445 	unsigned long flags = 0;
1446 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1447 
1448 	spin_lock_irqsave(&ha->hardware_lock, flags);
1449 	ha->interrupts_on = 1;
1450 	/* enable risc and host interrupts */
1451 	WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1452 	RD_REG_WORD(&reg->ictrl);
1453 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1454 
1455 }
1456 
1457 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1458 qla2x00_disable_intrs(struct qla_hw_data *ha)
1459 {
1460 	unsigned long flags = 0;
1461 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1462 
1463 	spin_lock_irqsave(&ha->hardware_lock, flags);
1464 	ha->interrupts_on = 0;
1465 	/* disable risc and host interrupts */
1466 	WRT_REG_WORD(&reg->ictrl, 0);
1467 	RD_REG_WORD(&reg->ictrl);
1468 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1469 }
1470 
1471 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1472 qla24xx_enable_intrs(struct qla_hw_data *ha)
1473 {
1474 	unsigned long flags = 0;
1475 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1476 
1477 	spin_lock_irqsave(&ha->hardware_lock, flags);
1478 	ha->interrupts_on = 1;
1479 	WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1480 	RD_REG_DWORD(&reg->ictrl);
1481 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1482 }
1483 
1484 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1485 qla24xx_disable_intrs(struct qla_hw_data *ha)
1486 {
1487 	unsigned long flags = 0;
1488 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1489 
1490 	if (IS_NOPOLLING_TYPE(ha))
1491 		return;
1492 	spin_lock_irqsave(&ha->hardware_lock, flags);
1493 	ha->interrupts_on = 0;
1494 	WRT_REG_DWORD(&reg->ictrl, 0);
1495 	RD_REG_DWORD(&reg->ictrl);
1496 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1497 }
1498 
1499 static int
qla2x00_iospace_config(struct qla_hw_data * ha)1500 qla2x00_iospace_config(struct qla_hw_data *ha)
1501 {
1502 	resource_size_t pio;
1503 	uint16_t msix;
1504 	int cpus;
1505 
1506 	if (pci_request_selected_regions(ha->pdev, ha->bars,
1507 	    QLA2XXX_DRIVER_NAME)) {
1508 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1509 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1510 		    pci_name(ha->pdev));
1511 		goto iospace_error_exit;
1512 	}
1513 	if (!(ha->bars & 1))
1514 		goto skip_pio;
1515 
1516 	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
1517 	pio = pci_resource_start(ha->pdev, 0);
1518 	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1519 		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1520 			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1521 			    "Invalid pci I/O region size (%s).\n",
1522 			    pci_name(ha->pdev));
1523 			pio = 0;
1524 		}
1525 	} else {
1526 		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1527 		    "Region #0 no a PIO resource (%s).\n",
1528 		    pci_name(ha->pdev));
1529 		pio = 0;
1530 	}
1531 	ha->pio_address = pio;
1532 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1533 	    "PIO address=%llu.\n",
1534 	    (unsigned long long)ha->pio_address);
1535 
1536 skip_pio:
1537 	/* Use MMIO operations for all accesses. */
1538 	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1539 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1540 		    "Region #1 not an MMIO resource (%s), aborting.\n",
1541 		    pci_name(ha->pdev));
1542 		goto iospace_error_exit;
1543 	}
1544 	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1545 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1546 		    "Invalid PCI mem region size (%s), aborting.\n",
1547 		    pci_name(ha->pdev));
1548 		goto iospace_error_exit;
1549 	}
1550 
1551 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1552 	if (!ha->iobase) {
1553 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1554 		    "Cannot remap MMIO (%s), aborting.\n",
1555 		    pci_name(ha->pdev));
1556 		goto iospace_error_exit;
1557 	}
1558 
1559 	/* Determine queue resources */
1560 	ha->max_req_queues = ha->max_rsp_queues = 1;
1561 	if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1562 		(ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1563 		(!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1564 		goto mqiobase_exit;
1565 
1566 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1567 			pci_resource_len(ha->pdev, 3));
1568 	if (ha->mqiobase) {
1569 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1570 		    "MQIO Base=%p.\n", ha->mqiobase);
1571 		/* Read MSIX vector size of the board */
1572 		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1573 		ha->msix_count = msix;
1574 		/* Max queues are bounded by available msix vectors */
1575 		/* queue 0 uses two msix vectors */
1576 		if (ql2xmultique_tag) {
1577 			cpus = num_online_cpus();
1578 			ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1579 				(cpus + 1) : (ha->msix_count - 1);
1580 			ha->max_req_queues = 2;
1581 		} else if (ql2xmaxqueues > 1) {
1582 			ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1583 			    QLA_MQ_SIZE : ql2xmaxqueues;
1584 			ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1585 			    "QoS mode set, max no of request queues:%d.\n",
1586 			    ha->max_req_queues);
1587 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1588 			    "QoS mode set, max no of request queues:%d.\n",
1589 			    ha->max_req_queues);
1590 		}
1591 		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1592 		    "MSI-X vector count: %d.\n", msix);
1593 	} else
1594 		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1595 		    "BAR 3 not enabled.\n");
1596 
1597 mqiobase_exit:
1598 	ha->msix_count = ha->max_rsp_queues + 1;
1599 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1600 	    "MSIX Count:%d.\n", ha->msix_count);
1601 	return (0);
1602 
1603 iospace_error_exit:
1604 	return (-ENOMEM);
1605 }
1606 
1607 
1608 static int
qla83xx_iospace_config(struct qla_hw_data * ha)1609 qla83xx_iospace_config(struct qla_hw_data *ha)
1610 {
1611 	uint16_t msix;
1612 	int cpus;
1613 
1614 	if (pci_request_selected_regions(ha->pdev, ha->bars,
1615 	    QLA2XXX_DRIVER_NAME)) {
1616 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1617 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1618 		    pci_name(ha->pdev));
1619 
1620 		goto iospace_error_exit;
1621 	}
1622 
1623 	/* Use MMIO operations for all accesses. */
1624 	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1625 		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1626 		    "Invalid pci I/O region size (%s).\n",
1627 		    pci_name(ha->pdev));
1628 		goto iospace_error_exit;
1629 	}
1630 	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1631 		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1632 		    "Invalid PCI mem region size (%s), aborting\n",
1633 			pci_name(ha->pdev));
1634 		goto iospace_error_exit;
1635 	}
1636 
1637 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1638 	if (!ha->iobase) {
1639 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1640 		    "Cannot remap MMIO (%s), aborting.\n",
1641 		    pci_name(ha->pdev));
1642 		goto iospace_error_exit;
1643 	}
1644 
1645 	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1646 	/* 83XX 26XX always use MQ type access for queues
1647 	 * - mbar 2, a.k.a region 4 */
1648 	ha->max_req_queues = ha->max_rsp_queues = 1;
1649 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1650 			pci_resource_len(ha->pdev, 4));
1651 
1652 	if (!ha->mqiobase) {
1653 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1654 		    "BAR2/region4 not enabled\n");
1655 		goto mqiobase_exit;
1656 	}
1657 
1658 	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1659 			pci_resource_len(ha->pdev, 2));
1660 	if (ha->msixbase) {
1661 		/* Read MSIX vector size of the board */
1662 		pci_read_config_word(ha->pdev,
1663 		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
1664 		ha->msix_count = msix;
1665 		/* Max queues are bounded by available msix vectors */
1666 		/* queue 0 uses two msix vectors */
1667 		if (ql2xmultique_tag) {
1668 			cpus = num_online_cpus();
1669 			ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1670 				(cpus + 1) : (ha->msix_count - 1);
1671 			ha->max_req_queues = 2;
1672 		} else if (ql2xmaxqueues > 1) {
1673 			ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1674 						QLA_MQ_SIZE : ql2xmaxqueues;
1675 			ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1676 			    "QoS mode set, max no of request queues:%d.\n",
1677 			    ha->max_req_queues);
1678 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1679 			    "QoS mode set, max no of request queues:%d.\n",
1680 			    ha->max_req_queues);
1681 		}
1682 		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1683 		    "MSI-X vector count: %d.\n", msix);
1684 	} else
1685 		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1686 		    "BAR 1 not enabled.\n");
1687 
1688 mqiobase_exit:
1689 	ha->msix_count = ha->max_rsp_queues + 1;
1690 
1691 	qlt_83xx_iospace_config(ha);
1692 
1693 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1694 	    "MSIX Count:%d.\n", ha->msix_count);
1695 	return 0;
1696 
1697 iospace_error_exit:
1698 	return -ENOMEM;
1699 }
1700 
1701 static struct isp_operations qla2100_isp_ops = {
1702 	.pci_config		= qla2100_pci_config,
1703 	.reset_chip		= qla2x00_reset_chip,
1704 	.chip_diag		= qla2x00_chip_diag,
1705 	.config_rings		= qla2x00_config_rings,
1706 	.reset_adapter		= qla2x00_reset_adapter,
1707 	.nvram_config		= qla2x00_nvram_config,
1708 	.update_fw_options	= qla2x00_update_fw_options,
1709 	.load_risc		= qla2x00_load_risc,
1710 	.pci_info_str		= qla2x00_pci_info_str,
1711 	.fw_version_str		= qla2x00_fw_version_str,
1712 	.intr_handler		= qla2100_intr_handler,
1713 	.enable_intrs		= qla2x00_enable_intrs,
1714 	.disable_intrs		= qla2x00_disable_intrs,
1715 	.abort_command		= qla2x00_abort_command,
1716 	.target_reset		= qla2x00_abort_target,
1717 	.lun_reset		= qla2x00_lun_reset,
1718 	.fabric_login		= qla2x00_login_fabric,
1719 	.fabric_logout		= qla2x00_fabric_logout,
1720 	.calc_req_entries	= qla2x00_calc_iocbs_32,
1721 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
1722 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
1723 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
1724 	.read_nvram		= qla2x00_read_nvram_data,
1725 	.write_nvram		= qla2x00_write_nvram_data,
1726 	.fw_dump		= qla2100_fw_dump,
1727 	.beacon_on		= NULL,
1728 	.beacon_off		= NULL,
1729 	.beacon_blink		= NULL,
1730 	.read_optrom		= qla2x00_read_optrom_data,
1731 	.write_optrom		= qla2x00_write_optrom_data,
1732 	.get_flash_version	= qla2x00_get_flash_version,
1733 	.start_scsi		= qla2x00_start_scsi,
1734 	.abort_isp		= qla2x00_abort_isp,
1735 	.iospace_config     	= qla2x00_iospace_config,
1736 	.initialize_adapter	= qla2x00_initialize_adapter,
1737 };
1738 
1739 static struct isp_operations qla2300_isp_ops = {
1740 	.pci_config		= qla2300_pci_config,
1741 	.reset_chip		= qla2x00_reset_chip,
1742 	.chip_diag		= qla2x00_chip_diag,
1743 	.config_rings		= qla2x00_config_rings,
1744 	.reset_adapter		= qla2x00_reset_adapter,
1745 	.nvram_config		= qla2x00_nvram_config,
1746 	.update_fw_options	= qla2x00_update_fw_options,
1747 	.load_risc		= qla2x00_load_risc,
1748 	.pci_info_str		= qla2x00_pci_info_str,
1749 	.fw_version_str		= qla2x00_fw_version_str,
1750 	.intr_handler		= qla2300_intr_handler,
1751 	.enable_intrs		= qla2x00_enable_intrs,
1752 	.disable_intrs		= qla2x00_disable_intrs,
1753 	.abort_command		= qla2x00_abort_command,
1754 	.target_reset		= qla2x00_abort_target,
1755 	.lun_reset		= qla2x00_lun_reset,
1756 	.fabric_login		= qla2x00_login_fabric,
1757 	.fabric_logout		= qla2x00_fabric_logout,
1758 	.calc_req_entries	= qla2x00_calc_iocbs_32,
1759 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
1760 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
1761 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
1762 	.read_nvram		= qla2x00_read_nvram_data,
1763 	.write_nvram		= qla2x00_write_nvram_data,
1764 	.fw_dump		= qla2300_fw_dump,
1765 	.beacon_on		= qla2x00_beacon_on,
1766 	.beacon_off		= qla2x00_beacon_off,
1767 	.beacon_blink		= qla2x00_beacon_blink,
1768 	.read_optrom		= qla2x00_read_optrom_data,
1769 	.write_optrom		= qla2x00_write_optrom_data,
1770 	.get_flash_version	= qla2x00_get_flash_version,
1771 	.start_scsi		= qla2x00_start_scsi,
1772 	.abort_isp		= qla2x00_abort_isp,
1773 	.iospace_config		= qla2x00_iospace_config,
1774 	.initialize_adapter	= qla2x00_initialize_adapter,
1775 };
1776 
1777 static struct isp_operations qla24xx_isp_ops = {
1778 	.pci_config		= qla24xx_pci_config,
1779 	.reset_chip		= qla24xx_reset_chip,
1780 	.chip_diag		= qla24xx_chip_diag,
1781 	.config_rings		= qla24xx_config_rings,
1782 	.reset_adapter		= qla24xx_reset_adapter,
1783 	.nvram_config		= qla24xx_nvram_config,
1784 	.update_fw_options	= qla24xx_update_fw_options,
1785 	.load_risc		= qla24xx_load_risc,
1786 	.pci_info_str		= qla24xx_pci_info_str,
1787 	.fw_version_str		= qla24xx_fw_version_str,
1788 	.intr_handler		= qla24xx_intr_handler,
1789 	.enable_intrs		= qla24xx_enable_intrs,
1790 	.disable_intrs		= qla24xx_disable_intrs,
1791 	.abort_command		= qla24xx_abort_command,
1792 	.target_reset		= qla24xx_abort_target,
1793 	.lun_reset		= qla24xx_lun_reset,
1794 	.fabric_login		= qla24xx_login_fabric,
1795 	.fabric_logout		= qla24xx_fabric_logout,
1796 	.calc_req_entries	= NULL,
1797 	.build_iocbs		= NULL,
1798 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1799 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1800 	.read_nvram		= qla24xx_read_nvram_data,
1801 	.write_nvram		= qla24xx_write_nvram_data,
1802 	.fw_dump		= qla24xx_fw_dump,
1803 	.beacon_on		= qla24xx_beacon_on,
1804 	.beacon_off		= qla24xx_beacon_off,
1805 	.beacon_blink		= qla24xx_beacon_blink,
1806 	.read_optrom		= qla24xx_read_optrom_data,
1807 	.write_optrom		= qla24xx_write_optrom_data,
1808 	.get_flash_version	= qla24xx_get_flash_version,
1809 	.start_scsi		= qla24xx_start_scsi,
1810 	.abort_isp		= qla2x00_abort_isp,
1811 	.iospace_config		= qla2x00_iospace_config,
1812 	.initialize_adapter	= qla2x00_initialize_adapter,
1813 };
1814 
1815 static struct isp_operations qla25xx_isp_ops = {
1816 	.pci_config		= qla25xx_pci_config,
1817 	.reset_chip		= qla24xx_reset_chip,
1818 	.chip_diag		= qla24xx_chip_diag,
1819 	.config_rings		= qla24xx_config_rings,
1820 	.reset_adapter		= qla24xx_reset_adapter,
1821 	.nvram_config		= qla24xx_nvram_config,
1822 	.update_fw_options	= qla24xx_update_fw_options,
1823 	.load_risc		= qla24xx_load_risc,
1824 	.pci_info_str		= qla24xx_pci_info_str,
1825 	.fw_version_str		= qla24xx_fw_version_str,
1826 	.intr_handler		= qla24xx_intr_handler,
1827 	.enable_intrs		= qla24xx_enable_intrs,
1828 	.disable_intrs		= qla24xx_disable_intrs,
1829 	.abort_command		= qla24xx_abort_command,
1830 	.target_reset		= qla24xx_abort_target,
1831 	.lun_reset		= qla24xx_lun_reset,
1832 	.fabric_login		= qla24xx_login_fabric,
1833 	.fabric_logout		= qla24xx_fabric_logout,
1834 	.calc_req_entries	= NULL,
1835 	.build_iocbs		= NULL,
1836 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1837 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1838 	.read_nvram		= qla25xx_read_nvram_data,
1839 	.write_nvram		= qla25xx_write_nvram_data,
1840 	.fw_dump		= qla25xx_fw_dump,
1841 	.beacon_on		= qla24xx_beacon_on,
1842 	.beacon_off		= qla24xx_beacon_off,
1843 	.beacon_blink		= qla24xx_beacon_blink,
1844 	.read_optrom		= qla25xx_read_optrom_data,
1845 	.write_optrom		= qla24xx_write_optrom_data,
1846 	.get_flash_version	= qla24xx_get_flash_version,
1847 	.start_scsi		= qla24xx_dif_start_scsi,
1848 	.abort_isp		= qla2x00_abort_isp,
1849 	.iospace_config		= qla2x00_iospace_config,
1850 	.initialize_adapter	= qla2x00_initialize_adapter,
1851 };
1852 
1853 static struct isp_operations qla81xx_isp_ops = {
1854 	.pci_config		= qla25xx_pci_config,
1855 	.reset_chip		= qla24xx_reset_chip,
1856 	.chip_diag		= qla24xx_chip_diag,
1857 	.config_rings		= qla24xx_config_rings,
1858 	.reset_adapter		= qla24xx_reset_adapter,
1859 	.nvram_config		= qla81xx_nvram_config,
1860 	.update_fw_options	= qla81xx_update_fw_options,
1861 	.load_risc		= qla81xx_load_risc,
1862 	.pci_info_str		= qla24xx_pci_info_str,
1863 	.fw_version_str		= qla24xx_fw_version_str,
1864 	.intr_handler		= qla24xx_intr_handler,
1865 	.enable_intrs		= qla24xx_enable_intrs,
1866 	.disable_intrs		= qla24xx_disable_intrs,
1867 	.abort_command		= qla24xx_abort_command,
1868 	.target_reset		= qla24xx_abort_target,
1869 	.lun_reset		= qla24xx_lun_reset,
1870 	.fabric_login		= qla24xx_login_fabric,
1871 	.fabric_logout		= qla24xx_fabric_logout,
1872 	.calc_req_entries	= NULL,
1873 	.build_iocbs		= NULL,
1874 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1875 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1876 	.read_nvram		= NULL,
1877 	.write_nvram		= NULL,
1878 	.fw_dump		= qla81xx_fw_dump,
1879 	.beacon_on		= qla24xx_beacon_on,
1880 	.beacon_off		= qla24xx_beacon_off,
1881 	.beacon_blink		= qla83xx_beacon_blink,
1882 	.read_optrom		= qla25xx_read_optrom_data,
1883 	.write_optrom		= qla24xx_write_optrom_data,
1884 	.get_flash_version	= qla24xx_get_flash_version,
1885 	.start_scsi		= qla24xx_dif_start_scsi,
1886 	.abort_isp		= qla2x00_abort_isp,
1887 	.iospace_config		= qla2x00_iospace_config,
1888 	.initialize_adapter	= qla2x00_initialize_adapter,
1889 };
1890 
1891 static struct isp_operations qla82xx_isp_ops = {
1892 	.pci_config		= qla82xx_pci_config,
1893 	.reset_chip		= qla82xx_reset_chip,
1894 	.chip_diag		= qla24xx_chip_diag,
1895 	.config_rings		= qla82xx_config_rings,
1896 	.reset_adapter		= qla24xx_reset_adapter,
1897 	.nvram_config		= qla81xx_nvram_config,
1898 	.update_fw_options	= qla24xx_update_fw_options,
1899 	.load_risc		= qla82xx_load_risc,
1900 	.pci_info_str		= qla24xx_pci_info_str,
1901 	.fw_version_str		= qla24xx_fw_version_str,
1902 	.intr_handler		= qla82xx_intr_handler,
1903 	.enable_intrs		= qla82xx_enable_intrs,
1904 	.disable_intrs		= qla82xx_disable_intrs,
1905 	.abort_command		= qla24xx_abort_command,
1906 	.target_reset		= qla24xx_abort_target,
1907 	.lun_reset		= qla24xx_lun_reset,
1908 	.fabric_login		= qla24xx_login_fabric,
1909 	.fabric_logout		= qla24xx_fabric_logout,
1910 	.calc_req_entries	= NULL,
1911 	.build_iocbs		= NULL,
1912 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1913 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1914 	.read_nvram		= qla24xx_read_nvram_data,
1915 	.write_nvram		= qla24xx_write_nvram_data,
1916 	.fw_dump		= qla82xx_fw_dump,
1917 	.beacon_on		= qla82xx_beacon_on,
1918 	.beacon_off		= qla82xx_beacon_off,
1919 	.beacon_blink		= NULL,
1920 	.read_optrom		= qla82xx_read_optrom_data,
1921 	.write_optrom		= qla82xx_write_optrom_data,
1922 	.get_flash_version	= qla82xx_get_flash_version,
1923 	.start_scsi             = qla82xx_start_scsi,
1924 	.abort_isp		= qla82xx_abort_isp,
1925 	.iospace_config     	= qla82xx_iospace_config,
1926 	.initialize_adapter	= qla2x00_initialize_adapter,
1927 };
1928 
1929 static struct isp_operations qla8044_isp_ops = {
1930 	.pci_config		= qla82xx_pci_config,
1931 	.reset_chip		= qla82xx_reset_chip,
1932 	.chip_diag		= qla24xx_chip_diag,
1933 	.config_rings		= qla82xx_config_rings,
1934 	.reset_adapter		= qla24xx_reset_adapter,
1935 	.nvram_config		= qla81xx_nvram_config,
1936 	.update_fw_options	= qla24xx_update_fw_options,
1937 	.load_risc		= qla82xx_load_risc,
1938 	.pci_info_str		= qla24xx_pci_info_str,
1939 	.fw_version_str		= qla24xx_fw_version_str,
1940 	.intr_handler		= qla8044_intr_handler,
1941 	.enable_intrs		= qla82xx_enable_intrs,
1942 	.disable_intrs		= qla82xx_disable_intrs,
1943 	.abort_command		= qla24xx_abort_command,
1944 	.target_reset		= qla24xx_abort_target,
1945 	.lun_reset		= qla24xx_lun_reset,
1946 	.fabric_login		= qla24xx_login_fabric,
1947 	.fabric_logout		= qla24xx_fabric_logout,
1948 	.calc_req_entries	= NULL,
1949 	.build_iocbs		= NULL,
1950 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1951 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1952 	.read_nvram		= NULL,
1953 	.write_nvram		= NULL,
1954 	.fw_dump		= qla8044_fw_dump,
1955 	.beacon_on		= qla82xx_beacon_on,
1956 	.beacon_off		= qla82xx_beacon_off,
1957 	.beacon_blink		= NULL,
1958 	.read_optrom		= qla8044_read_optrom_data,
1959 	.write_optrom		= qla8044_write_optrom_data,
1960 	.get_flash_version	= qla82xx_get_flash_version,
1961 	.start_scsi             = qla82xx_start_scsi,
1962 	.abort_isp		= qla8044_abort_isp,
1963 	.iospace_config		= qla82xx_iospace_config,
1964 	.initialize_adapter	= qla2x00_initialize_adapter,
1965 };
1966 
1967 static struct isp_operations qla83xx_isp_ops = {
1968 	.pci_config		= qla25xx_pci_config,
1969 	.reset_chip		= qla24xx_reset_chip,
1970 	.chip_diag		= qla24xx_chip_diag,
1971 	.config_rings		= qla24xx_config_rings,
1972 	.reset_adapter		= qla24xx_reset_adapter,
1973 	.nvram_config		= qla81xx_nvram_config,
1974 	.update_fw_options	= qla81xx_update_fw_options,
1975 	.load_risc		= qla81xx_load_risc,
1976 	.pci_info_str		= qla24xx_pci_info_str,
1977 	.fw_version_str		= qla24xx_fw_version_str,
1978 	.intr_handler		= qla24xx_intr_handler,
1979 	.enable_intrs		= qla24xx_enable_intrs,
1980 	.disable_intrs		= qla24xx_disable_intrs,
1981 	.abort_command		= qla24xx_abort_command,
1982 	.target_reset		= qla24xx_abort_target,
1983 	.lun_reset		= qla24xx_lun_reset,
1984 	.fabric_login		= qla24xx_login_fabric,
1985 	.fabric_logout		= qla24xx_fabric_logout,
1986 	.calc_req_entries	= NULL,
1987 	.build_iocbs		= NULL,
1988 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
1989 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
1990 	.read_nvram		= NULL,
1991 	.write_nvram		= NULL,
1992 	.fw_dump		= qla83xx_fw_dump,
1993 	.beacon_on		= qla24xx_beacon_on,
1994 	.beacon_off		= qla24xx_beacon_off,
1995 	.beacon_blink		= qla83xx_beacon_blink,
1996 	.read_optrom		= qla25xx_read_optrom_data,
1997 	.write_optrom		= qla24xx_write_optrom_data,
1998 	.get_flash_version	= qla24xx_get_flash_version,
1999 	.start_scsi		= qla24xx_dif_start_scsi,
2000 	.abort_isp		= qla2x00_abort_isp,
2001 	.iospace_config		= qla83xx_iospace_config,
2002 	.initialize_adapter	= qla2x00_initialize_adapter,
2003 };
2004 
2005 static struct isp_operations qlafx00_isp_ops = {
2006 	.pci_config		= qlafx00_pci_config,
2007 	.reset_chip		= qlafx00_soft_reset,
2008 	.chip_diag		= qlafx00_chip_diag,
2009 	.config_rings		= qlafx00_config_rings,
2010 	.reset_adapter		= qlafx00_soft_reset,
2011 	.nvram_config		= NULL,
2012 	.update_fw_options	= NULL,
2013 	.load_risc		= NULL,
2014 	.pci_info_str		= qlafx00_pci_info_str,
2015 	.fw_version_str		= qlafx00_fw_version_str,
2016 	.intr_handler		= qlafx00_intr_handler,
2017 	.enable_intrs		= qlafx00_enable_intrs,
2018 	.disable_intrs		= qlafx00_disable_intrs,
2019 	.abort_command		= qla24xx_async_abort_command,
2020 	.target_reset		= qlafx00_abort_target,
2021 	.lun_reset		= qlafx00_lun_reset,
2022 	.fabric_login		= NULL,
2023 	.fabric_logout		= NULL,
2024 	.calc_req_entries	= NULL,
2025 	.build_iocbs		= NULL,
2026 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2027 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2028 	.read_nvram		= qla24xx_read_nvram_data,
2029 	.write_nvram		= qla24xx_write_nvram_data,
2030 	.fw_dump		= NULL,
2031 	.beacon_on		= qla24xx_beacon_on,
2032 	.beacon_off		= qla24xx_beacon_off,
2033 	.beacon_blink		= NULL,
2034 	.read_optrom		= qla24xx_read_optrom_data,
2035 	.write_optrom		= qla24xx_write_optrom_data,
2036 	.get_flash_version	= qla24xx_get_flash_version,
2037 	.start_scsi		= qlafx00_start_scsi,
2038 	.abort_isp		= qlafx00_abort_isp,
2039 	.iospace_config		= qlafx00_iospace_config,
2040 	.initialize_adapter	= qlafx00_initialize_adapter,
2041 };
2042 
2043 static struct isp_operations qla27xx_isp_ops = {
2044 	.pci_config		= qla25xx_pci_config,
2045 	.reset_chip		= qla24xx_reset_chip,
2046 	.chip_diag		= qla24xx_chip_diag,
2047 	.config_rings		= qla24xx_config_rings,
2048 	.reset_adapter		= qla24xx_reset_adapter,
2049 	.nvram_config		= qla81xx_nvram_config,
2050 	.update_fw_options	= qla81xx_update_fw_options,
2051 	.load_risc		= qla81xx_load_risc,
2052 	.pci_info_str		= qla24xx_pci_info_str,
2053 	.fw_version_str		= qla24xx_fw_version_str,
2054 	.intr_handler		= qla24xx_intr_handler,
2055 	.enable_intrs		= qla24xx_enable_intrs,
2056 	.disable_intrs		= qla24xx_disable_intrs,
2057 	.abort_command		= qla24xx_abort_command,
2058 	.target_reset		= qla24xx_abort_target,
2059 	.lun_reset		= qla24xx_lun_reset,
2060 	.fabric_login		= qla24xx_login_fabric,
2061 	.fabric_logout		= qla24xx_fabric_logout,
2062 	.calc_req_entries	= NULL,
2063 	.build_iocbs		= NULL,
2064 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2065 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2066 	.read_nvram		= NULL,
2067 	.write_nvram		= NULL,
2068 	.fw_dump		= qla27xx_fwdump,
2069 	.beacon_on		= qla24xx_beacon_on,
2070 	.beacon_off		= qla24xx_beacon_off,
2071 	.beacon_blink		= qla83xx_beacon_blink,
2072 	.read_optrom		= qla25xx_read_optrom_data,
2073 	.write_optrom		= qla24xx_write_optrom_data,
2074 	.get_flash_version	= qla24xx_get_flash_version,
2075 	.start_scsi		= qla24xx_dif_start_scsi,
2076 	.abort_isp		= qla2x00_abort_isp,
2077 	.iospace_config		= qla83xx_iospace_config,
2078 	.initialize_adapter	= qla2x00_initialize_adapter,
2079 };
2080 
2081 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2082 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2083 {
2084 	ha->device_type = DT_EXTENDED_IDS;
2085 	switch (ha->pdev->device) {
2086 	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2087 		ha->device_type |= DT_ISP2100;
2088 		ha->device_type &= ~DT_EXTENDED_IDS;
2089 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2090 		break;
2091 	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2092 		ha->device_type |= DT_ISP2200;
2093 		ha->device_type &= ~DT_EXTENDED_IDS;
2094 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2095 		break;
2096 	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2097 		ha->device_type |= DT_ISP2300;
2098 		ha->device_type |= DT_ZIO_SUPPORTED;
2099 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2100 		break;
2101 	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2102 		ha->device_type |= DT_ISP2312;
2103 		ha->device_type |= DT_ZIO_SUPPORTED;
2104 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2105 		break;
2106 	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2107 		ha->device_type |= DT_ISP2322;
2108 		ha->device_type |= DT_ZIO_SUPPORTED;
2109 		if (ha->pdev->subsystem_vendor == 0x1028 &&
2110 		    ha->pdev->subsystem_device == 0x0170)
2111 			ha->device_type |= DT_OEM_001;
2112 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2113 		break;
2114 	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2115 		ha->device_type |= DT_ISP6312;
2116 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2117 		break;
2118 	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2119 		ha->device_type |= DT_ISP6322;
2120 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2121 		break;
2122 	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2123 		ha->device_type |= DT_ISP2422;
2124 		ha->device_type |= DT_ZIO_SUPPORTED;
2125 		ha->device_type |= DT_FWI2;
2126 		ha->device_type |= DT_IIDMA;
2127 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2128 		break;
2129 	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2130 		ha->device_type |= DT_ISP2432;
2131 		ha->device_type |= DT_ZIO_SUPPORTED;
2132 		ha->device_type |= DT_FWI2;
2133 		ha->device_type |= DT_IIDMA;
2134 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2135 		break;
2136 	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2137 		ha->device_type |= DT_ISP8432;
2138 		ha->device_type |= DT_ZIO_SUPPORTED;
2139 		ha->device_type |= DT_FWI2;
2140 		ha->device_type |= DT_IIDMA;
2141 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2142 		break;
2143 	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2144 		ha->device_type |= DT_ISP5422;
2145 		ha->device_type |= DT_FWI2;
2146 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2147 		break;
2148 	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2149 		ha->device_type |= DT_ISP5432;
2150 		ha->device_type |= DT_FWI2;
2151 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2152 		break;
2153 	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2154 		ha->device_type |= DT_ISP2532;
2155 		ha->device_type |= DT_ZIO_SUPPORTED;
2156 		ha->device_type |= DT_FWI2;
2157 		ha->device_type |= DT_IIDMA;
2158 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2159 		break;
2160 	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2161 		ha->device_type |= DT_ISP8001;
2162 		ha->device_type |= DT_ZIO_SUPPORTED;
2163 		ha->device_type |= DT_FWI2;
2164 		ha->device_type |= DT_IIDMA;
2165 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2166 		break;
2167 	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2168 		ha->device_type |= DT_ISP8021;
2169 		ha->device_type |= DT_ZIO_SUPPORTED;
2170 		ha->device_type |= DT_FWI2;
2171 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 		/* Initialize 82XX ISP flags */
2173 		qla82xx_init_flags(ha);
2174 		break;
2175 	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2176 		ha->device_type |= DT_ISP8044;
2177 		ha->device_type |= DT_ZIO_SUPPORTED;
2178 		ha->device_type |= DT_FWI2;
2179 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2180 		/* Initialize 82XX ISP flags */
2181 		qla82xx_init_flags(ha);
2182 		break;
2183 	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2184 		ha->device_type |= DT_ISP2031;
2185 		ha->device_type |= DT_ZIO_SUPPORTED;
2186 		ha->device_type |= DT_FWI2;
2187 		ha->device_type |= DT_IIDMA;
2188 		ha->device_type |= DT_T10_PI;
2189 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2190 		break;
2191 	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2192 		ha->device_type |= DT_ISP8031;
2193 		ha->device_type |= DT_ZIO_SUPPORTED;
2194 		ha->device_type |= DT_FWI2;
2195 		ha->device_type |= DT_IIDMA;
2196 		ha->device_type |= DT_T10_PI;
2197 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2198 		break;
2199 	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2200 		ha->device_type |= DT_ISPFX00;
2201 		break;
2202 	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2203 		ha->device_type |= DT_ISP2071;
2204 		ha->device_type |= DT_ZIO_SUPPORTED;
2205 		ha->device_type |= DT_FWI2;
2206 		ha->device_type |= DT_IIDMA;
2207 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 		break;
2209 	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2210 		ha->device_type |= DT_ISP2271;
2211 		ha->device_type |= DT_ZIO_SUPPORTED;
2212 		ha->device_type |= DT_FWI2;
2213 		ha->device_type |= DT_IIDMA;
2214 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2215 		break;
2216 	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2217 		ha->device_type |= DT_ISP2261;
2218 		ha->device_type |= DT_ZIO_SUPPORTED;
2219 		ha->device_type |= DT_FWI2;
2220 		ha->device_type |= DT_IIDMA;
2221 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2222 		break;
2223 	}
2224 
2225 	if (IS_QLA82XX(ha))
2226 		ha->port_no = ha->portnum & 1;
2227 	else {
2228 		/* Get adapter physical port no from interrupt pin register. */
2229 		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2230 		if (IS_QLA27XX(ha))
2231 			ha->port_no--;
2232 		else
2233 			ha->port_no = !(ha->port_no & 1);
2234 	}
2235 
2236 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2237 	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2238 	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2239 }
2240 
2241 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2242 qla2xxx_scan_start(struct Scsi_Host *shost)
2243 {
2244 	scsi_qla_host_t *vha = shost_priv(shost);
2245 
2246 	if (vha->hw->flags.running_gold_fw)
2247 		return;
2248 
2249 	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2250 	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2251 	set_bit(RSCN_UPDATE, &vha->dpc_flags);
2252 	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2253 }
2254 
2255 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2256 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2257 {
2258 	scsi_qla_host_t *vha = shost_priv(shost);
2259 
2260 	if (!vha->host)
2261 		return 1;
2262 	if (time > vha->hw->loop_reset_delay * HZ)
2263 		return 1;
2264 
2265 	return atomic_read(&vha->loop_state) == LOOP_READY;
2266 }
2267 
2268 /*
2269  * PCI driver interface
2270  */
2271 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2272 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2273 {
2274 	int	ret = -ENODEV;
2275 	struct Scsi_Host *host;
2276 	scsi_qla_host_t *base_vha = NULL;
2277 	struct qla_hw_data *ha;
2278 	char pci_info[30];
2279 	char fw_str[30], wq_name[30];
2280 	struct scsi_host_template *sht;
2281 	int bars, mem_only = 0;
2282 	uint16_t req_length = 0, rsp_length = 0;
2283 	struct req_que *req = NULL;
2284 	struct rsp_que *rsp = NULL;
2285 	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2286 	sht = &qla2xxx_driver_template;
2287 	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2288 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2289 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2290 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2291 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2292 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2293 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2294 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2295 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2296 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2297 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2298 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2299 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2300 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2301 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2302 		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2303 		mem_only = 1;
2304 		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2305 		    "Mem only adapter.\n");
2306 	}
2307 	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2308 	    "Bars=%d.\n", bars);
2309 
2310 	if (mem_only) {
2311 		if (pci_enable_device_mem(pdev))
2312 			goto probe_out;
2313 	} else {
2314 		if (pci_enable_device(pdev))
2315 			goto probe_out;
2316 	}
2317 
2318 	/* This may fail but that's ok */
2319 	pci_enable_pcie_error_reporting(pdev);
2320 
2321 	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2322 	if (!ha) {
2323 		ql_log_pci(ql_log_fatal, pdev, 0x0009,
2324 		    "Unable to allocate memory for ha.\n");
2325 		goto probe_out;
2326 	}
2327 	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2328 	    "Memory allocated for ha=%p.\n", ha);
2329 	ha->pdev = pdev;
2330 	ha->tgt.enable_class_2 = ql2xenableclass2;
2331 	INIT_LIST_HEAD(&ha->tgt.q_full_list);
2332 	spin_lock_init(&ha->tgt.q_full_lock);
2333 
2334 	/* Clear our data area */
2335 	ha->bars = bars;
2336 	ha->mem_only = mem_only;
2337 	spin_lock_init(&ha->hardware_lock);
2338 	spin_lock_init(&ha->vport_slock);
2339 	mutex_init(&ha->selflogin_lock);
2340 	mutex_init(&ha->optrom_mutex);
2341 
2342 	/* Set ISP-type information. */
2343 	qla2x00_set_isp_flags(ha);
2344 
2345 	/* Set EEH reset type to fundamental if required by hba */
2346 	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2347 	    IS_QLA83XX(ha) || IS_QLA27XX(ha))
2348 		pdev->needs_freset = 1;
2349 
2350 	ha->prev_topology = 0;
2351 	ha->init_cb_size = sizeof(init_cb_t);
2352 	ha->link_data_rate = PORT_SPEED_UNKNOWN;
2353 	ha->optrom_size = OPTROM_SIZE_2300;
2354 
2355 	/* Assign ISP specific operations. */
2356 	if (IS_QLA2100(ha)) {
2357 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2358 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2359 		req_length = REQUEST_ENTRY_CNT_2100;
2360 		rsp_length = RESPONSE_ENTRY_CNT_2100;
2361 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2362 		ha->gid_list_info_size = 4;
2363 		ha->flash_conf_off = ~0;
2364 		ha->flash_data_off = ~0;
2365 		ha->nvram_conf_off = ~0;
2366 		ha->nvram_data_off = ~0;
2367 		ha->isp_ops = &qla2100_isp_ops;
2368 	} else if (IS_QLA2200(ha)) {
2369 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2370 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2371 		req_length = REQUEST_ENTRY_CNT_2200;
2372 		rsp_length = RESPONSE_ENTRY_CNT_2100;
2373 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2374 		ha->gid_list_info_size = 4;
2375 		ha->flash_conf_off = ~0;
2376 		ha->flash_data_off = ~0;
2377 		ha->nvram_conf_off = ~0;
2378 		ha->nvram_data_off = ~0;
2379 		ha->isp_ops = &qla2100_isp_ops;
2380 	} else if (IS_QLA23XX(ha)) {
2381 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2382 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2383 		req_length = REQUEST_ENTRY_CNT_2200;
2384 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2385 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2386 		ha->gid_list_info_size = 6;
2387 		if (IS_QLA2322(ha) || IS_QLA6322(ha))
2388 			ha->optrom_size = OPTROM_SIZE_2322;
2389 		ha->flash_conf_off = ~0;
2390 		ha->flash_data_off = ~0;
2391 		ha->nvram_conf_off = ~0;
2392 		ha->nvram_data_off = ~0;
2393 		ha->isp_ops = &qla2300_isp_ops;
2394 	} else if (IS_QLA24XX_TYPE(ha)) {
2395 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2396 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2397 		req_length = REQUEST_ENTRY_CNT_24XX;
2398 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2399 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2400 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2401 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2402 		ha->gid_list_info_size = 8;
2403 		ha->optrom_size = OPTROM_SIZE_24XX;
2404 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2405 		ha->isp_ops = &qla24xx_isp_ops;
2406 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2407 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2408 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2409 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2410 	} else if (IS_QLA25XX(ha)) {
2411 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2412 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2413 		req_length = REQUEST_ENTRY_CNT_24XX;
2414 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2415 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2416 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2417 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2418 		ha->gid_list_info_size = 8;
2419 		ha->optrom_size = OPTROM_SIZE_25XX;
2420 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2421 		ha->isp_ops = &qla25xx_isp_ops;
2422 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2423 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2424 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2425 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2426 	} else if (IS_QLA81XX(ha)) {
2427 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2428 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2429 		req_length = REQUEST_ENTRY_CNT_24XX;
2430 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2431 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2432 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2433 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2434 		ha->gid_list_info_size = 8;
2435 		ha->optrom_size = OPTROM_SIZE_81XX;
2436 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2437 		ha->isp_ops = &qla81xx_isp_ops;
2438 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2439 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2440 		ha->nvram_conf_off = ~0;
2441 		ha->nvram_data_off = ~0;
2442 	} else if (IS_QLA82XX(ha)) {
2443 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2444 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2445 		req_length = REQUEST_ENTRY_CNT_82XX;
2446 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
2447 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2448 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2449 		ha->gid_list_info_size = 8;
2450 		ha->optrom_size = OPTROM_SIZE_82XX;
2451 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2452 		ha->isp_ops = &qla82xx_isp_ops;
2453 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2454 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2455 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2456 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2457 	} else if (IS_QLA8044(ha)) {
2458 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2459 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2460 		req_length = REQUEST_ENTRY_CNT_82XX;
2461 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
2462 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2463 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2464 		ha->gid_list_info_size = 8;
2465 		ha->optrom_size = OPTROM_SIZE_83XX;
2466 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2467 		ha->isp_ops = &qla8044_isp_ops;
2468 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2469 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2470 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2471 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2472 	} else if (IS_QLA83XX(ha)) {
2473 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
2474 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2475 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2476 		req_length = REQUEST_ENTRY_CNT_83XX;
2477 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2478 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2479 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2480 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2481 		ha->gid_list_info_size = 8;
2482 		ha->optrom_size = OPTROM_SIZE_83XX;
2483 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2484 		ha->isp_ops = &qla83xx_isp_ops;
2485 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2486 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2487 		ha->nvram_conf_off = ~0;
2488 		ha->nvram_data_off = ~0;
2489 	}  else if (IS_QLAFX00(ha)) {
2490 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2491 		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2492 		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2493 		req_length = REQUEST_ENTRY_CNT_FX00;
2494 		rsp_length = RESPONSE_ENTRY_CNT_FX00;
2495 		ha->isp_ops = &qlafx00_isp_ops;
2496 		ha->port_down_retry_count = 30; /* default value */
2497 		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2498 		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2499 		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2500 		ha->mr.fw_hbt_en = 1;
2501 		ha->mr.host_info_resend = false;
2502 		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2503 	} else if (IS_QLA27XX(ha)) {
2504 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
2505 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2506 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
2507 		req_length = REQUEST_ENTRY_CNT_24XX;
2508 		rsp_length = RESPONSE_ENTRY_CNT_2300;
2509 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2510 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2511 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2512 		ha->gid_list_info_size = 8;
2513 		ha->optrom_size = OPTROM_SIZE_83XX;
2514 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2515 		ha->isp_ops = &qla27xx_isp_ops;
2516 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2517 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2518 		ha->nvram_conf_off = ~0;
2519 		ha->nvram_data_off = ~0;
2520 	}
2521 
2522 	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2523 	    "mbx_count=%d, req_length=%d, "
2524 	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2525 	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2526 	    "max_fibre_devices=%d.\n",
2527 	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2528 	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2529 	    ha->nvram_npiv_size, ha->max_fibre_devices);
2530 	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2531 	    "isp_ops=%p, flash_conf_off=%d, "
2532 	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2533 	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2534 	    ha->nvram_conf_off, ha->nvram_data_off);
2535 
2536 	/* Configure PCI I/O space */
2537 	ret = ha->isp_ops->iospace_config(ha);
2538 	if (ret)
2539 		goto iospace_config_failed;
2540 
2541 	ql_log_pci(ql_log_info, pdev, 0x001d,
2542 	    "Found an ISP%04X irq %d iobase 0x%p.\n",
2543 	    pdev->device, pdev->irq, ha->iobase);
2544 	mutex_init(&ha->vport_lock);
2545 	init_completion(&ha->mbx_cmd_comp);
2546 	complete(&ha->mbx_cmd_comp);
2547 	init_completion(&ha->mbx_intr_comp);
2548 	init_completion(&ha->dcbx_comp);
2549 	init_completion(&ha->lb_portup_comp);
2550 
2551 	set_bit(0, (unsigned long *) ha->vp_idx_map);
2552 
2553 	qla2x00_config_dma_addressing(ha);
2554 	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2555 	    "64 Bit addressing is %s.\n",
2556 	    ha->flags.enable_64bit_addressing ? "enable" :
2557 	    "disable");
2558 	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2559 	if (ret) {
2560 		ql_log_pci(ql_log_fatal, pdev, 0x0031,
2561 		    "Failed to allocate memory for adapter, aborting.\n");
2562 
2563 		goto probe_hw_failed;
2564 	}
2565 
2566 	req->max_q_depth = MAX_Q_DEPTH;
2567 	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2568 		req->max_q_depth = ql2xmaxqdepth;
2569 
2570 
2571 	base_vha = qla2x00_create_host(sht, ha);
2572 	if (!base_vha) {
2573 		ret = -ENOMEM;
2574 		qla2x00_mem_free(ha);
2575 		qla2x00_free_req_que(ha, req);
2576 		qla2x00_free_rsp_que(ha, rsp);
2577 		goto probe_hw_failed;
2578 	}
2579 
2580 	pci_set_drvdata(pdev, base_vha);
2581 	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2582 
2583 	host = base_vha->host;
2584 	base_vha->req = req;
2585 	if (IS_QLA2XXX_MIDTYPE(ha))
2586 		base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2587 	else
2588 		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2589 						base_vha->vp_idx;
2590 
2591 	/* Setup fcport template structure. */
2592 	ha->mr.fcport.vha = base_vha;
2593 	ha->mr.fcport.port_type = FCT_UNKNOWN;
2594 	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2595 	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2596 	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2597 	ha->mr.fcport.scan_state = 1;
2598 
2599 	/* Set the SG table size based on ISP type */
2600 	if (!IS_FWI2_CAPABLE(ha)) {
2601 		if (IS_QLA2100(ha))
2602 			host->sg_tablesize = 32;
2603 	} else {
2604 		if (!IS_QLA82XX(ha))
2605 			host->sg_tablesize = QLA_SG_ALL;
2606 	}
2607 	host->max_id = ha->max_fibre_devices;
2608 	host->cmd_per_lun = 3;
2609 	host->unique_id = host->host_no;
2610 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2611 		host->max_cmd_len = 32;
2612 	else
2613 		host->max_cmd_len = MAX_CMDSZ;
2614 	host->max_channel = MAX_BUSES - 1;
2615 	/* Older HBAs support only 16-bit LUNs */
2616 	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2617 	    ql2xmaxlun > 0xffff)
2618 		host->max_lun = 0xffff;
2619 	else
2620 		host->max_lun = ql2xmaxlun;
2621 	host->transportt = qla2xxx_transport_template;
2622 	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2623 
2624 	ql_dbg(ql_dbg_init, base_vha, 0x0033,
2625 	    "max_id=%d this_id=%d "
2626 	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2627 	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2628 	    host->this_id, host->cmd_per_lun, host->unique_id,
2629 	    host->max_cmd_len, host->max_channel, host->max_lun,
2630 	    host->transportt, sht->vendor_id);
2631 
2632 que_init:
2633 	/* Alloc arrays of request and response ring ptrs */
2634 	if (!qla2x00_alloc_queues(ha, req, rsp)) {
2635 		ql_log(ql_log_fatal, base_vha, 0x003d,
2636 		    "Failed to allocate memory for queue pointers..."
2637 		    "aborting.\n");
2638 		goto probe_init_failed;
2639 	}
2640 
2641 	qlt_probe_one_stage1(base_vha, ha);
2642 
2643 	/* Set up the irqs */
2644 	ret = qla2x00_request_irqs(ha, rsp);
2645 	if (ret)
2646 		goto probe_init_failed;
2647 
2648 	pci_save_state(pdev);
2649 
2650 	/* Assign back pointers */
2651 	rsp->req = req;
2652 	req->rsp = rsp;
2653 
2654 	if (IS_QLAFX00(ha)) {
2655 		ha->rsp_q_map[0] = rsp;
2656 		ha->req_q_map[0] = req;
2657 		set_bit(0, ha->req_qid_map);
2658 		set_bit(0, ha->rsp_qid_map);
2659 	}
2660 
2661 	/* FWI2-capable only. */
2662 	req->req_q_in = &ha->iobase->isp24.req_q_in;
2663 	req->req_q_out = &ha->iobase->isp24.req_q_out;
2664 	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2665 	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2666 	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2667 		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2668 		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2669 		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2670 		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
2671 	}
2672 
2673 	if (IS_QLAFX00(ha)) {
2674 		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2675 		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2676 		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2677 		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2678 	}
2679 
2680 	if (IS_P3P_TYPE(ha)) {
2681 		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2682 		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2683 		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2684 	}
2685 
2686 	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2687 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2688 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2689 	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2690 	    "req->req_q_in=%p req->req_q_out=%p "
2691 	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2692 	    req->req_q_in, req->req_q_out,
2693 	    rsp->rsp_q_in, rsp->rsp_q_out);
2694 	ql_dbg(ql_dbg_init, base_vha, 0x003e,
2695 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2696 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2697 	ql_dbg(ql_dbg_init, base_vha, 0x003f,
2698 	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2699 	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2700 
2701 	if (ha->isp_ops->initialize_adapter(base_vha)) {
2702 		ql_log(ql_log_fatal, base_vha, 0x00d6,
2703 		    "Failed to initialize adapter - Adapter flags %x.\n",
2704 		    base_vha->device_flags);
2705 
2706 		if (IS_QLA82XX(ha)) {
2707 			qla82xx_idc_lock(ha);
2708 			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2709 				QLA8XXX_DEV_FAILED);
2710 			qla82xx_idc_unlock(ha);
2711 			ql_log(ql_log_fatal, base_vha, 0x00d7,
2712 			    "HW State: FAILED.\n");
2713 		} else if (IS_QLA8044(ha)) {
2714 			qla8044_idc_lock(ha);
2715 			qla8044_wr_direct(base_vha,
2716 				QLA8044_CRB_DEV_STATE_INDEX,
2717 				QLA8XXX_DEV_FAILED);
2718 			qla8044_idc_unlock(ha);
2719 			ql_log(ql_log_fatal, base_vha, 0x0150,
2720 			    "HW State: FAILED.\n");
2721 		}
2722 
2723 		ret = -ENODEV;
2724 		goto probe_failed;
2725 	}
2726 
2727 	if (IS_QLAFX00(ha))
2728 		host->can_queue = QLAFX00_MAX_CANQUEUE;
2729 	else
2730 		host->can_queue = req->num_outstanding_cmds - 10;
2731 
2732 	ql_dbg(ql_dbg_init, base_vha, 0x0032,
2733 	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2734 	    host->can_queue, base_vha->req,
2735 	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2736 
2737 	if (ha->mqenable) {
2738 		if (qla25xx_setup_mode(base_vha)) {
2739 			ql_log(ql_log_warn, base_vha, 0x00ec,
2740 			    "Failed to create queues, falling back to single queue mode.\n");
2741 			goto que_init;
2742 		}
2743 	}
2744 
2745 	if (ha->flags.running_gold_fw)
2746 		goto skip_dpc;
2747 
2748 	/*
2749 	 * Startup the kernel thread for this host adapter
2750 	 */
2751 	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2752 	    "%s_dpc", base_vha->host_str);
2753 	if (IS_ERR(ha->dpc_thread)) {
2754 		ql_log(ql_log_fatal, base_vha, 0x00ed,
2755 		    "Failed to start DPC thread.\n");
2756 		ret = PTR_ERR(ha->dpc_thread);
2757 		goto probe_failed;
2758 	}
2759 	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2760 	    "DPC thread started successfully.\n");
2761 
2762 	/*
2763 	 * If we're not coming up in initiator mode, we might sit for
2764 	 * a while without waking up the dpc thread, which leads to a
2765 	 * stuck process warning.  So just kick the dpc once here and
2766 	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2767 	 */
2768 	qla2xxx_wake_dpc(base_vha);
2769 
2770 	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2771 
2772 	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2773 		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2774 		ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2775 		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2776 
2777 		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2778 		ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2779 		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2780 		INIT_WORK(&ha->idc_state_handler,
2781 		    qla83xx_idc_state_handler_work);
2782 		INIT_WORK(&ha->nic_core_unrecoverable,
2783 		    qla83xx_nic_core_unrecoverable_work);
2784 	}
2785 
2786 skip_dpc:
2787 	list_add_tail(&base_vha->list, &ha->vp_list);
2788 	base_vha->host->irq = ha->pdev->irq;
2789 
2790 	/* Initialized the timer */
2791 	qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2792 	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2793 	    "Started qla2x00_timer with "
2794 	    "interval=%d.\n", WATCH_INTERVAL);
2795 	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2796 	    "Detected hba at address=%p.\n",
2797 	    ha);
2798 
2799 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2800 		if (ha->fw_attributes & BIT_4) {
2801 			int prot = 0, guard;
2802 			base_vha->flags.difdix_supported = 1;
2803 			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2804 			    "Registering for DIF/DIX type 1 and 3 protection.\n");
2805 			if (ql2xenabledif == 1)
2806 				prot = SHOST_DIX_TYPE0_PROTECTION;
2807 			scsi_host_set_prot(host,
2808 			    prot | SHOST_DIF_TYPE1_PROTECTION
2809 			    | SHOST_DIF_TYPE2_PROTECTION
2810 			    | SHOST_DIF_TYPE3_PROTECTION
2811 			    | SHOST_DIX_TYPE1_PROTECTION
2812 			    | SHOST_DIX_TYPE2_PROTECTION
2813 			    | SHOST_DIX_TYPE3_PROTECTION);
2814 
2815 			guard = SHOST_DIX_GUARD_CRC;
2816 
2817 			if (IS_PI_IPGUARD_CAPABLE(ha) &&
2818 			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2819 				guard |= SHOST_DIX_GUARD_IP;
2820 
2821 			scsi_host_set_guard(host, guard);
2822 		} else
2823 			base_vha->flags.difdix_supported = 0;
2824 	}
2825 
2826 	ha->isp_ops->enable_intrs(ha);
2827 
2828 	if (IS_QLAFX00(ha)) {
2829 		ret = qlafx00_fx_disc(base_vha,
2830 			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2831 		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2832 		    QLA_SG_ALL : 128;
2833 	}
2834 
2835 	ret = scsi_add_host(host, &pdev->dev);
2836 	if (ret)
2837 		goto probe_failed;
2838 
2839 	base_vha->flags.init_done = 1;
2840 	base_vha->flags.online = 1;
2841 	ha->prev_minidump_failed = 0;
2842 
2843 	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2844 	    "Init done and hba is online.\n");
2845 
2846 	if (qla_ini_mode_enabled(base_vha))
2847 		scsi_scan_host(host);
2848 	else
2849 		ql_dbg(ql_dbg_init, base_vha, 0x0122,
2850 			"skipping scsi_scan_host() for non-initiator port\n");
2851 
2852 	qla2x00_alloc_sysfs_attr(base_vha);
2853 
2854 	if (IS_QLAFX00(ha)) {
2855 		ret = qlafx00_fx_disc(base_vha,
2856 			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2857 
2858 		/* Register system information */
2859 		ret =  qlafx00_fx_disc(base_vha,
2860 			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2861 	}
2862 
2863 	qla2x00_init_host_attr(base_vha);
2864 
2865 	qla2x00_dfs_setup(base_vha);
2866 
2867 	ql_log(ql_log_info, base_vha, 0x00fb,
2868 	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2869 	ql_log(ql_log_info, base_vha, 0x00fc,
2870 	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2871 	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2872 	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2873 	    base_vha->host_no,
2874 	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2875 
2876 	qlt_add_target(ha, base_vha);
2877 
2878 	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2879 	return 0;
2880 
2881 probe_init_failed:
2882 	qla2x00_free_req_que(ha, req);
2883 	ha->req_q_map[0] = NULL;
2884 	clear_bit(0, ha->req_qid_map);
2885 	qla2x00_free_rsp_que(ha, rsp);
2886 	ha->rsp_q_map[0] = NULL;
2887 	clear_bit(0, ha->rsp_qid_map);
2888 	ha->max_req_queues = ha->max_rsp_queues = 0;
2889 
2890 probe_failed:
2891 	if (base_vha->timer_active)
2892 		qla2x00_stop_timer(base_vha);
2893 	base_vha->flags.online = 0;
2894 	if (ha->dpc_thread) {
2895 		struct task_struct *t = ha->dpc_thread;
2896 
2897 		ha->dpc_thread = NULL;
2898 		kthread_stop(t);
2899 	}
2900 
2901 	qla2x00_free_device(base_vha);
2902 
2903 	scsi_host_put(base_vha->host);
2904 
2905 probe_hw_failed:
2906 	qla2x00_clear_drv_active(ha);
2907 
2908 iospace_config_failed:
2909 	if (IS_P3P_TYPE(ha)) {
2910 		if (!ha->nx_pcibase)
2911 			iounmap((device_reg_t *)ha->nx_pcibase);
2912 		if (!ql2xdbwr)
2913 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2914 	} else {
2915 		if (ha->iobase)
2916 			iounmap(ha->iobase);
2917 		if (ha->cregbase)
2918 			iounmap(ha->cregbase);
2919 	}
2920 	pci_release_selected_regions(ha->pdev, ha->bars);
2921 	kfree(ha);
2922 	ha = NULL;
2923 
2924 probe_out:
2925 	pci_disable_device(pdev);
2926 	return ret;
2927 }
2928 
2929 static void
qla2x00_shutdown(struct pci_dev * pdev)2930 qla2x00_shutdown(struct pci_dev *pdev)
2931 {
2932 	scsi_qla_host_t *vha;
2933 	struct qla_hw_data  *ha;
2934 
2935 	if (!atomic_read(&pdev->enable_cnt))
2936 		return;
2937 
2938 	vha = pci_get_drvdata(pdev);
2939 	ha = vha->hw;
2940 
2941 	/* Notify ISPFX00 firmware */
2942 	if (IS_QLAFX00(ha))
2943 		qlafx00_driver_shutdown(vha, 20);
2944 
2945 	/* Turn-off FCE trace */
2946 	if (ha->flags.fce_enabled) {
2947 		qla2x00_disable_fce_trace(vha, NULL, NULL);
2948 		ha->flags.fce_enabled = 0;
2949 	}
2950 
2951 	/* Turn-off EFT trace */
2952 	if (ha->eft)
2953 		qla2x00_disable_eft_trace(vha);
2954 
2955 	/* Stop currently executing firmware. */
2956 	qla2x00_try_to_stop_firmware(vha);
2957 
2958 	/* Turn adapter off line */
2959 	vha->flags.online = 0;
2960 
2961 	/* turn-off interrupts on the card */
2962 	if (ha->interrupts_on) {
2963 		vha->flags.init_done = 0;
2964 		ha->isp_ops->disable_intrs(ha);
2965 	}
2966 
2967 	qla2x00_free_irqs(vha);
2968 
2969 	qla2x00_free_fw_dump(ha);
2970 
2971 	pci_disable_pcie_error_reporting(pdev);
2972 	pci_disable_device(pdev);
2973 }
2974 
2975 /* Deletes all the virtual ports for a given ha */
2976 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)2977 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
2978 {
2979 	scsi_qla_host_t *vha;
2980 	unsigned long flags;
2981 
2982 	mutex_lock(&ha->vport_lock);
2983 	while (ha->cur_vport_count) {
2984 		spin_lock_irqsave(&ha->vport_slock, flags);
2985 
2986 		BUG_ON(base_vha->list.next == &ha->vp_list);
2987 		/* This assumes first entry in ha->vp_list is always base vha */
2988 		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2989 		scsi_host_get(vha->host);
2990 
2991 		spin_unlock_irqrestore(&ha->vport_slock, flags);
2992 		mutex_unlock(&ha->vport_lock);
2993 
2994 		fc_vport_terminate(vha->fc_vport);
2995 		scsi_host_put(vha->host);
2996 
2997 		mutex_lock(&ha->vport_lock);
2998 	}
2999 	mutex_unlock(&ha->vport_lock);
3000 }
3001 
3002 /* Stops all deferred work threads */
3003 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3004 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3005 {
3006 	/* Flush the work queue and remove it */
3007 	if (ha->wq) {
3008 		flush_workqueue(ha->wq);
3009 		destroy_workqueue(ha->wq);
3010 		ha->wq = NULL;
3011 	}
3012 
3013 	/* Cancel all work and destroy DPC workqueues */
3014 	if (ha->dpc_lp_wq) {
3015 		cancel_work_sync(&ha->idc_aen);
3016 		destroy_workqueue(ha->dpc_lp_wq);
3017 		ha->dpc_lp_wq = NULL;
3018 	}
3019 
3020 	if (ha->dpc_hp_wq) {
3021 		cancel_work_sync(&ha->nic_core_reset);
3022 		cancel_work_sync(&ha->idc_state_handler);
3023 		cancel_work_sync(&ha->nic_core_unrecoverable);
3024 		destroy_workqueue(ha->dpc_hp_wq);
3025 		ha->dpc_hp_wq = NULL;
3026 	}
3027 
3028 	/* Kill the kernel thread for this host */
3029 	if (ha->dpc_thread) {
3030 		struct task_struct *t = ha->dpc_thread;
3031 
3032 		/*
3033 		 * qla2xxx_wake_dpc checks for ->dpc_thread
3034 		 * so we need to zero it out.
3035 		 */
3036 		ha->dpc_thread = NULL;
3037 		kthread_stop(t);
3038 	}
3039 }
3040 
3041 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3042 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3043 {
3044 	if (IS_QLA82XX(ha)) {
3045 
3046 		iounmap((device_reg_t *)ha->nx_pcibase);
3047 		if (!ql2xdbwr)
3048 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3049 	} else {
3050 		if (ha->iobase)
3051 			iounmap(ha->iobase);
3052 
3053 		if (ha->cregbase)
3054 			iounmap(ha->cregbase);
3055 
3056 		if (ha->mqiobase)
3057 			iounmap(ha->mqiobase);
3058 
3059 		if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3060 			iounmap(ha->msixbase);
3061 	}
3062 }
3063 
3064 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3065 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3066 {
3067 	if (IS_QLA8044(ha)) {
3068 		qla8044_idc_lock(ha);
3069 		qla8044_clear_drv_active(ha);
3070 		qla8044_idc_unlock(ha);
3071 	} else if (IS_QLA82XX(ha)) {
3072 		qla82xx_idc_lock(ha);
3073 		qla82xx_clear_drv_active(ha);
3074 		qla82xx_idc_unlock(ha);
3075 	}
3076 }
3077 
3078 static void
qla2x00_remove_one(struct pci_dev * pdev)3079 qla2x00_remove_one(struct pci_dev *pdev)
3080 {
3081 	scsi_qla_host_t *base_vha;
3082 	struct qla_hw_data  *ha;
3083 
3084 	base_vha = pci_get_drvdata(pdev);
3085 	ha = base_vha->hw;
3086 
3087 	/* Indicate device removal to prevent future board_disable and wait
3088 	 * until any pending board_disable has completed. */
3089 	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3090 	cancel_work_sync(&ha->board_disable);
3091 
3092 	/*
3093 	 * If the PCI device is disabled then there was a PCI-disconnect and
3094 	 * qla2x00_disable_board_on_pci_error has taken care of most of the
3095 	 * resources.
3096 	 */
3097 	if (!atomic_read(&pdev->enable_cnt)) {
3098 		scsi_host_put(base_vha->host);
3099 		kfree(ha);
3100 		pci_set_drvdata(pdev, NULL);
3101 		return;
3102 	}
3103 
3104 	qla2x00_wait_for_hba_ready(base_vha);
3105 
3106 	set_bit(UNLOADING, &base_vha->dpc_flags);
3107 
3108 	if (IS_QLAFX00(ha))
3109 		qlafx00_driver_shutdown(base_vha, 20);
3110 
3111 	qla2x00_delete_all_vps(ha, base_vha);
3112 
3113 	if (IS_QLA8031(ha)) {
3114 		ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3115 		    "Clearing fcoe driver presence.\n");
3116 		if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3117 			ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3118 			    "Error while clearing DRV-Presence.\n");
3119 	}
3120 
3121 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3122 
3123 	qla2x00_dfs_remove(base_vha);
3124 
3125 	qla84xx_put_chip(base_vha);
3126 
3127 	/* Laser should be disabled only for ISP2031 */
3128 	if (IS_QLA2031(ha))
3129 		qla83xx_disable_laser(base_vha);
3130 
3131 	/* Disable timer */
3132 	if (base_vha->timer_active)
3133 		qla2x00_stop_timer(base_vha);
3134 
3135 	base_vha->flags.online = 0;
3136 
3137 	qla2x00_destroy_deferred_work(ha);
3138 
3139 	qlt_remove_target(ha, base_vha);
3140 
3141 	qla2x00_free_sysfs_attr(base_vha, true);
3142 
3143 	fc_remove_host(base_vha->host);
3144 
3145 	scsi_remove_host(base_vha->host);
3146 
3147 	qla2x00_free_device(base_vha);
3148 
3149 	qla2x00_clear_drv_active(ha);
3150 
3151 	scsi_host_put(base_vha->host);
3152 
3153 	qla2x00_unmap_iobases(ha);
3154 
3155 	pci_release_selected_regions(ha->pdev, ha->bars);
3156 	kfree(ha);
3157 	ha = NULL;
3158 
3159 	pci_disable_pcie_error_reporting(pdev);
3160 
3161 	pci_disable_device(pdev);
3162 }
3163 
3164 static void
qla2x00_free_device(scsi_qla_host_t * vha)3165 qla2x00_free_device(scsi_qla_host_t *vha)
3166 {
3167 	struct qla_hw_data *ha = vha->hw;
3168 
3169 	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3170 
3171 	/* Disable timer */
3172 	if (vha->timer_active)
3173 		qla2x00_stop_timer(vha);
3174 
3175 	qla25xx_delete_queues(vha);
3176 
3177 	if (ha->flags.fce_enabled)
3178 		qla2x00_disable_fce_trace(vha, NULL, NULL);
3179 
3180 	if (ha->eft)
3181 		qla2x00_disable_eft_trace(vha);
3182 
3183 	/* Stop currently executing firmware. */
3184 	qla2x00_try_to_stop_firmware(vha);
3185 
3186 	vha->flags.online = 0;
3187 
3188 	/* turn-off interrupts on the card */
3189 	if (ha->interrupts_on) {
3190 		vha->flags.init_done = 0;
3191 		ha->isp_ops->disable_intrs(ha);
3192 	}
3193 
3194 	qla2x00_free_irqs(vha);
3195 
3196 	qla2x00_free_fcports(vha);
3197 
3198 	qla2x00_mem_free(ha);
3199 
3200 	qla82xx_md_free(vha);
3201 
3202 	qla2x00_free_queues(ha);
3203 }
3204 
qla2x00_free_fcports(struct scsi_qla_host * vha)3205 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3206 {
3207 	fc_port_t *fcport, *tfcport;
3208 
3209 	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3210 		list_del(&fcport->list);
3211 		qla2x00_clear_loop_id(fcport);
3212 		kfree(fcport);
3213 		fcport = NULL;
3214 	}
3215 }
3216 
3217 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport,int defer)3218 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3219     int defer)
3220 {
3221 	struct fc_rport *rport;
3222 	scsi_qla_host_t *base_vha;
3223 	unsigned long flags;
3224 
3225 	if (!fcport->rport)
3226 		return;
3227 
3228 	rport = fcport->rport;
3229 	if (defer) {
3230 		base_vha = pci_get_drvdata(vha->hw->pdev);
3231 		spin_lock_irqsave(vha->host->host_lock, flags);
3232 		fcport->drport = rport;
3233 		spin_unlock_irqrestore(vha->host->host_lock, flags);
3234 		qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3235 		set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3236 		qla2xxx_wake_dpc(base_vha);
3237 	} else {
3238 		int now;
3239 		if (rport)
3240 			fc_remote_port_delete(rport);
3241 		qlt_do_generation_tick(vha, &now);
3242 		qlt_fc_port_deleted(vha, fcport, now);
3243 	}
3244 }
3245 
3246 /*
3247  * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3248  *
3249  * Input: ha = adapter block pointer.  fcport = port structure pointer.
3250  *
3251  * Return: None.
3252  *
3253  * Context:
3254  */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login,int defer)3255 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3256     int do_login, int defer)
3257 {
3258 	if (IS_QLAFX00(vha->hw)) {
3259 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3260 		qla2x00_schedule_rport_del(vha, fcport, defer);
3261 		return;
3262 	}
3263 
3264 	if (atomic_read(&fcport->state) == FCS_ONLINE &&
3265 	    vha->vp_idx == fcport->vha->vp_idx) {
3266 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3267 		qla2x00_schedule_rport_del(vha, fcport, defer);
3268 	}
3269 	/*
3270 	 * We may need to retry the login, so don't change the state of the
3271 	 * port but do the retries.
3272 	 */
3273 	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3274 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3275 
3276 	if (!do_login)
3277 		return;
3278 
3279 	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3280 
3281 	if (fcport->login_retry == 0) {
3282 		fcport->login_retry = vha->hw->login_retry_count;
3283 
3284 		ql_dbg(ql_dbg_disc, vha, 0x2067,
3285 		    "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3286 		    fcport->port_name, fcport->loop_id, fcport->login_retry);
3287 	}
3288 }
3289 
3290 /*
3291  * qla2x00_mark_all_devices_lost
3292  *	Updates fcport state when device goes offline.
3293  *
3294  * Input:
3295  *	ha = adapter block pointer.
3296  *	fcport = port structure pointer.
3297  *
3298  * Return:
3299  *	None.
3300  *
3301  * Context:
3302  */
3303 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha,int defer)3304 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3305 {
3306 	fc_port_t *fcport;
3307 
3308 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
3309 		if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3310 			continue;
3311 
3312 		/*
3313 		 * No point in marking the device as lost, if the device is
3314 		 * already DEAD.
3315 		 */
3316 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3317 			continue;
3318 		if (atomic_read(&fcport->state) == FCS_ONLINE) {
3319 			qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3320 			if (defer)
3321 				qla2x00_schedule_rport_del(vha, fcport, defer);
3322 			else if (vha->vp_idx == fcport->vha->vp_idx)
3323 				qla2x00_schedule_rport_del(vha, fcport, defer);
3324 		}
3325 	}
3326 }
3327 
3328 /*
3329 * qla2x00_mem_alloc
3330 *      Allocates adapter memory.
3331 *
3332 * Returns:
3333 *      0  = success.
3334 *      !0  = failure.
3335 */
3336 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)3337 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3338 	struct req_que **req, struct rsp_que **rsp)
3339 {
3340 	char	name[16];
3341 
3342 	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3343 		&ha->init_cb_dma, GFP_KERNEL);
3344 	if (!ha->init_cb)
3345 		goto fail;
3346 
3347 	if (qlt_mem_alloc(ha) < 0)
3348 		goto fail_free_init_cb;
3349 
3350 	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3351 		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3352 	if (!ha->gid_list)
3353 		goto fail_free_tgt_mem;
3354 
3355 	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3356 	if (!ha->srb_mempool)
3357 		goto fail_free_gid_list;
3358 
3359 	if (IS_P3P_TYPE(ha)) {
3360 		/* Allocate cache for CT6 Ctx. */
3361 		if (!ctx_cachep) {
3362 			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3363 				sizeof(struct ct6_dsd), 0,
3364 				SLAB_HWCACHE_ALIGN, NULL);
3365 			if (!ctx_cachep)
3366 				goto fail_free_gid_list;
3367 		}
3368 		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3369 			ctx_cachep);
3370 		if (!ha->ctx_mempool)
3371 			goto fail_free_srb_mempool;
3372 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3373 		    "ctx_cachep=%p ctx_mempool=%p.\n",
3374 		    ctx_cachep, ha->ctx_mempool);
3375 	}
3376 
3377 	/* Get memory for cached NVRAM */
3378 	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3379 	if (!ha->nvram)
3380 		goto fail_free_ctx_mempool;
3381 
3382 	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3383 		ha->pdev->device);
3384 	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3385 		DMA_POOL_SIZE, 8, 0);
3386 	if (!ha->s_dma_pool)
3387 		goto fail_free_nvram;
3388 
3389 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3390 	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3391 	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3392 
3393 	if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3394 		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3395 			DSD_LIST_DMA_POOL_SIZE, 8, 0);
3396 		if (!ha->dl_dma_pool) {
3397 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3398 			    "Failed to allocate memory for dl_dma_pool.\n");
3399 			goto fail_s_dma_pool;
3400 		}
3401 
3402 		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3403 			FCP_CMND_DMA_POOL_SIZE, 8, 0);
3404 		if (!ha->fcp_cmnd_dma_pool) {
3405 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3406 			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3407 			goto fail_dl_dma_pool;
3408 		}
3409 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3410 		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3411 		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3412 	}
3413 
3414 	/* Allocate memory for SNS commands */
3415 	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3416 	/* Get consistent memory allocated for SNS commands */
3417 		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3418 		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3419 		if (!ha->sns_cmd)
3420 			goto fail_dma_pool;
3421 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3422 		    "sns_cmd: %p.\n", ha->sns_cmd);
3423 	} else {
3424 	/* Get consistent memory allocated for MS IOCB */
3425 		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3426 			&ha->ms_iocb_dma);
3427 		if (!ha->ms_iocb)
3428 			goto fail_dma_pool;
3429 	/* Get consistent memory allocated for CT SNS commands */
3430 		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3431 			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3432 		if (!ha->ct_sns)
3433 			goto fail_free_ms_iocb;
3434 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3435 		    "ms_iocb=%p ct_sns=%p.\n",
3436 		    ha->ms_iocb, ha->ct_sns);
3437 	}
3438 
3439 	/* Allocate memory for request ring */
3440 	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3441 	if (!*req) {
3442 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3443 		    "Failed to allocate memory for req.\n");
3444 		goto fail_req;
3445 	}
3446 	(*req)->length = req_len;
3447 	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3448 		((*req)->length + 1) * sizeof(request_t),
3449 		&(*req)->dma, GFP_KERNEL);
3450 	if (!(*req)->ring) {
3451 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3452 		    "Failed to allocate memory for req_ring.\n");
3453 		goto fail_req_ring;
3454 	}
3455 	/* Allocate memory for response ring */
3456 	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3457 	if (!*rsp) {
3458 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3459 		    "Failed to allocate memory for rsp.\n");
3460 		goto fail_rsp;
3461 	}
3462 	(*rsp)->hw = ha;
3463 	(*rsp)->length = rsp_len;
3464 	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3465 		((*rsp)->length + 1) * sizeof(response_t),
3466 		&(*rsp)->dma, GFP_KERNEL);
3467 	if (!(*rsp)->ring) {
3468 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3469 		    "Failed to allocate memory for rsp_ring.\n");
3470 		goto fail_rsp_ring;
3471 	}
3472 	(*req)->rsp = *rsp;
3473 	(*rsp)->req = *req;
3474 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3475 	    "req=%p req->length=%d req->ring=%p rsp=%p "
3476 	    "rsp->length=%d rsp->ring=%p.\n",
3477 	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3478 	    (*rsp)->ring);
3479 	/* Allocate memory for NVRAM data for vports */
3480 	if (ha->nvram_npiv_size) {
3481 		ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3482 		    ha->nvram_npiv_size, GFP_KERNEL);
3483 		if (!ha->npiv_info) {
3484 			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3485 			    "Failed to allocate memory for npiv_info.\n");
3486 			goto fail_npiv_info;
3487 		}
3488 	} else
3489 		ha->npiv_info = NULL;
3490 
3491 	/* Get consistent memory allocated for EX-INIT-CB. */
3492 	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3493 		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3494 		    &ha->ex_init_cb_dma);
3495 		if (!ha->ex_init_cb)
3496 			goto fail_ex_init_cb;
3497 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3498 		    "ex_init_cb=%p.\n", ha->ex_init_cb);
3499 	}
3500 
3501 	INIT_LIST_HEAD(&ha->gbl_dsd_list);
3502 
3503 	/* Get consistent memory allocated for Async Port-Database. */
3504 	if (!IS_FWI2_CAPABLE(ha)) {
3505 		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3506 			&ha->async_pd_dma);
3507 		if (!ha->async_pd)
3508 			goto fail_async_pd;
3509 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3510 		    "async_pd=%p.\n", ha->async_pd);
3511 	}
3512 
3513 	INIT_LIST_HEAD(&ha->vp_list);
3514 
3515 	/* Allocate memory for our loop_id bitmap */
3516 	ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3517 	    GFP_KERNEL);
3518 	if (!ha->loop_id_map)
3519 		goto fail_async_pd;
3520 	else {
3521 		qla2x00_set_reserved_loop_ids(ha);
3522 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3523 		    "loop_id_map=%p.\n", ha->loop_id_map);
3524 	}
3525 
3526 	return 0;
3527 
3528 fail_async_pd:
3529 	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3530 fail_ex_init_cb:
3531 	kfree(ha->npiv_info);
3532 fail_npiv_info:
3533 	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3534 		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3535 	(*rsp)->ring = NULL;
3536 	(*rsp)->dma = 0;
3537 fail_rsp_ring:
3538 	kfree(*rsp);
3539 fail_rsp:
3540 	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3541 		sizeof(request_t), (*req)->ring, (*req)->dma);
3542 	(*req)->ring = NULL;
3543 	(*req)->dma = 0;
3544 fail_req_ring:
3545 	kfree(*req);
3546 fail_req:
3547 	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3548 		ha->ct_sns, ha->ct_sns_dma);
3549 	ha->ct_sns = NULL;
3550 	ha->ct_sns_dma = 0;
3551 fail_free_ms_iocb:
3552 	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3553 	ha->ms_iocb = NULL;
3554 	ha->ms_iocb_dma = 0;
3555 fail_dma_pool:
3556 	if (IS_QLA82XX(ha) || ql2xenabledif) {
3557 		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3558 		ha->fcp_cmnd_dma_pool = NULL;
3559 	}
3560 fail_dl_dma_pool:
3561 	if (IS_QLA82XX(ha) || ql2xenabledif) {
3562 		dma_pool_destroy(ha->dl_dma_pool);
3563 		ha->dl_dma_pool = NULL;
3564 	}
3565 fail_s_dma_pool:
3566 	dma_pool_destroy(ha->s_dma_pool);
3567 	ha->s_dma_pool = NULL;
3568 fail_free_nvram:
3569 	kfree(ha->nvram);
3570 	ha->nvram = NULL;
3571 fail_free_ctx_mempool:
3572 	mempool_destroy(ha->ctx_mempool);
3573 	ha->ctx_mempool = NULL;
3574 fail_free_srb_mempool:
3575 	mempool_destroy(ha->srb_mempool);
3576 	ha->srb_mempool = NULL;
3577 fail_free_gid_list:
3578 	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3579 	ha->gid_list,
3580 	ha->gid_list_dma);
3581 	ha->gid_list = NULL;
3582 	ha->gid_list_dma = 0;
3583 fail_free_tgt_mem:
3584 	qlt_mem_free(ha);
3585 fail_free_init_cb:
3586 	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3587 	ha->init_cb_dma);
3588 	ha->init_cb = NULL;
3589 	ha->init_cb_dma = 0;
3590 fail:
3591 	ql_log(ql_log_fatal, NULL, 0x0030,
3592 	    "Memory allocation failure.\n");
3593 	return -ENOMEM;
3594 }
3595 
3596 /*
3597 * qla2x00_free_fw_dump
3598 *	Frees fw dump stuff.
3599 *
3600 * Input:
3601 *	ha = adapter block pointer
3602 */
3603 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)3604 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3605 {
3606 	if (ha->fce)
3607 		dma_free_coherent(&ha->pdev->dev,
3608 		    FCE_SIZE, ha->fce, ha->fce_dma);
3609 
3610 	if (ha->eft)
3611 		dma_free_coherent(&ha->pdev->dev,
3612 		    EFT_SIZE, ha->eft, ha->eft_dma);
3613 
3614 	if (ha->fw_dump)
3615 		vfree(ha->fw_dump);
3616 	if (ha->fw_dump_template)
3617 		vfree(ha->fw_dump_template);
3618 
3619 	ha->fce = NULL;
3620 	ha->fce_dma = 0;
3621 	ha->eft = NULL;
3622 	ha->eft_dma = 0;
3623 	ha->fw_dumped = 0;
3624 	ha->fw_dump_cap_flags = 0;
3625 	ha->fw_dump_reading = 0;
3626 	ha->fw_dump = NULL;
3627 	ha->fw_dump_len = 0;
3628 	ha->fw_dump_template = NULL;
3629 	ha->fw_dump_template_len = 0;
3630 }
3631 
3632 /*
3633 * qla2x00_mem_free
3634 *      Frees all adapter allocated memory.
3635 *
3636 * Input:
3637 *      ha = adapter block pointer.
3638 */
3639 static void
qla2x00_mem_free(struct qla_hw_data * ha)3640 qla2x00_mem_free(struct qla_hw_data *ha)
3641 {
3642 	qla2x00_free_fw_dump(ha);
3643 
3644 	if (ha->mctp_dump)
3645 		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3646 		    ha->mctp_dump_dma);
3647 
3648 	if (ha->srb_mempool)
3649 		mempool_destroy(ha->srb_mempool);
3650 
3651 	if (ha->dcbx_tlv)
3652 		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3653 		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
3654 
3655 	if (ha->xgmac_data)
3656 		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3657 		    ha->xgmac_data, ha->xgmac_data_dma);
3658 
3659 	if (ha->sns_cmd)
3660 		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3661 		ha->sns_cmd, ha->sns_cmd_dma);
3662 
3663 	if (ha->ct_sns)
3664 		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3665 		ha->ct_sns, ha->ct_sns_dma);
3666 
3667 	if (ha->sfp_data)
3668 		dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3669 
3670 	if (ha->ms_iocb)
3671 		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3672 
3673 	if (ha->ex_init_cb)
3674 		dma_pool_free(ha->s_dma_pool,
3675 			ha->ex_init_cb, ha->ex_init_cb_dma);
3676 
3677 	if (ha->async_pd)
3678 		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3679 
3680 	if (ha->s_dma_pool)
3681 		dma_pool_destroy(ha->s_dma_pool);
3682 
3683 	if (ha->gid_list)
3684 		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3685 		ha->gid_list, ha->gid_list_dma);
3686 
3687 	if (IS_QLA82XX(ha)) {
3688 		if (!list_empty(&ha->gbl_dsd_list)) {
3689 			struct dsd_dma *dsd_ptr, *tdsd_ptr;
3690 
3691 			/* clean up allocated prev pool */
3692 			list_for_each_entry_safe(dsd_ptr,
3693 				tdsd_ptr, &ha->gbl_dsd_list, list) {
3694 				dma_pool_free(ha->dl_dma_pool,
3695 				dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3696 				list_del(&dsd_ptr->list);
3697 				kfree(dsd_ptr);
3698 			}
3699 		}
3700 	}
3701 
3702 	if (ha->dl_dma_pool)
3703 		dma_pool_destroy(ha->dl_dma_pool);
3704 
3705 	if (ha->fcp_cmnd_dma_pool)
3706 		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3707 
3708 	if (ha->ctx_mempool)
3709 		mempool_destroy(ha->ctx_mempool);
3710 
3711 	qlt_mem_free(ha);
3712 
3713 	if (ha->init_cb)
3714 		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3715 			ha->init_cb, ha->init_cb_dma);
3716 	vfree(ha->optrom_buffer);
3717 	kfree(ha->nvram);
3718 	kfree(ha->npiv_info);
3719 	kfree(ha->swl);
3720 	kfree(ha->loop_id_map);
3721 
3722 	ha->srb_mempool = NULL;
3723 	ha->ctx_mempool = NULL;
3724 	ha->sns_cmd = NULL;
3725 	ha->sns_cmd_dma = 0;
3726 	ha->ct_sns = NULL;
3727 	ha->ct_sns_dma = 0;
3728 	ha->ms_iocb = NULL;
3729 	ha->ms_iocb_dma = 0;
3730 	ha->init_cb = NULL;
3731 	ha->init_cb_dma = 0;
3732 	ha->ex_init_cb = NULL;
3733 	ha->ex_init_cb_dma = 0;
3734 	ha->async_pd = NULL;
3735 	ha->async_pd_dma = 0;
3736 
3737 	ha->s_dma_pool = NULL;
3738 	ha->dl_dma_pool = NULL;
3739 	ha->fcp_cmnd_dma_pool = NULL;
3740 
3741 	ha->gid_list = NULL;
3742 	ha->gid_list_dma = 0;
3743 
3744 	ha->tgt.atio_ring = NULL;
3745 	ha->tgt.atio_dma = 0;
3746 	ha->tgt.tgt_vp_map = NULL;
3747 }
3748 
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)3749 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3750 						struct qla_hw_data *ha)
3751 {
3752 	struct Scsi_Host *host;
3753 	struct scsi_qla_host *vha = NULL;
3754 
3755 	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3756 	if (host == NULL) {
3757 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3758 		    "Failed to allocate host from the scsi layer, aborting.\n");
3759 		goto fail;
3760 	}
3761 
3762 	/* Clear our data area */
3763 	vha = shost_priv(host);
3764 	memset(vha, 0, sizeof(scsi_qla_host_t));
3765 
3766 	vha->host = host;
3767 	vha->host_no = host->host_no;
3768 	vha->hw = ha;
3769 
3770 	INIT_LIST_HEAD(&vha->vp_fcports);
3771 	INIT_LIST_HEAD(&vha->work_list);
3772 	INIT_LIST_HEAD(&vha->list);
3773 	INIT_LIST_HEAD(&vha->qla_cmd_list);
3774 	INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
3775 
3776 	spin_lock_init(&vha->work_lock);
3777 	spin_lock_init(&vha->cmd_list_lock);
3778 
3779 	sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3780 	ql_dbg(ql_dbg_init, vha, 0x0041,
3781 	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3782 	    vha->host, vha->hw, vha,
3783 	    dev_name(&(ha->pdev->dev)));
3784 
3785 	return vha;
3786 
3787 fail:
3788 	return vha;
3789 }
3790 
3791 static struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)3792 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3793 {
3794 	struct qla_work_evt *e;
3795 	uint8_t bail;
3796 
3797 	QLA_VHA_MARK_BUSY(vha, bail);
3798 	if (bail)
3799 		return NULL;
3800 
3801 	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3802 	if (!e) {
3803 		QLA_VHA_MARK_NOT_BUSY(vha);
3804 		return NULL;
3805 	}
3806 
3807 	INIT_LIST_HEAD(&e->list);
3808 	e->type = type;
3809 	e->flags = QLA_EVT_FLAG_FREE;
3810 	return e;
3811 }
3812 
3813 static int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)3814 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3815 {
3816 	unsigned long flags;
3817 
3818 	spin_lock_irqsave(&vha->work_lock, flags);
3819 	list_add_tail(&e->list, &vha->work_list);
3820 	spin_unlock_irqrestore(&vha->work_lock, flags);
3821 	qla2xxx_wake_dpc(vha);
3822 
3823 	return QLA_SUCCESS;
3824 }
3825 
3826 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)3827 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3828     u32 data)
3829 {
3830 	struct qla_work_evt *e;
3831 
3832 	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3833 	if (!e)
3834 		return QLA_FUNCTION_FAILED;
3835 
3836 	e->u.aen.code = code;
3837 	e->u.aen.data = data;
3838 	return qla2x00_post_work(vha, e);
3839 }
3840 
3841 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)3842 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3843 {
3844 	struct qla_work_evt *e;
3845 
3846 	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3847 	if (!e)
3848 		return QLA_FUNCTION_FAILED;
3849 
3850 	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3851 	return qla2x00_post_work(vha, e);
3852 }
3853 
3854 #define qla2x00_post_async_work(name, type)	\
3855 int qla2x00_post_async_##name##_work(		\
3856     struct scsi_qla_host *vha,			\
3857     fc_port_t *fcport, uint16_t *data)		\
3858 {						\
3859 	struct qla_work_evt *e;			\
3860 						\
3861 	e = qla2x00_alloc_work(vha, type);	\
3862 	if (!e)					\
3863 		return QLA_FUNCTION_FAILED;	\
3864 						\
3865 	e->u.logio.fcport = fcport;		\
3866 	if (data) {				\
3867 		e->u.logio.data[0] = data[0];	\
3868 		e->u.logio.data[1] = data[1];	\
3869 	}					\
3870 	return qla2x00_post_work(vha, e);	\
3871 }
3872 
3873 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3874 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3875 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3876 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3877 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3878 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3879 
3880 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)3881 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3882 {
3883 	struct qla_work_evt *e;
3884 
3885 	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3886 	if (!e)
3887 		return QLA_FUNCTION_FAILED;
3888 
3889 	e->u.uevent.code = code;
3890 	return qla2x00_post_work(vha, e);
3891 }
3892 
3893 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)3894 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3895 {
3896 	char event_string[40];
3897 	char *envp[] = { event_string, NULL };
3898 
3899 	switch (code) {
3900 	case QLA_UEVENT_CODE_FW_DUMP:
3901 		snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3902 		    vha->host_no);
3903 		break;
3904 	default:
3905 		/* do nothing */
3906 		break;
3907 	}
3908 	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3909 }
3910 
3911 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)3912 qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
3913 			uint32_t *data, int cnt)
3914 {
3915 	struct qla_work_evt *e;
3916 
3917 	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3918 	if (!e)
3919 		return QLA_FUNCTION_FAILED;
3920 
3921 	e->u.aenfx.evtcode = evtcode;
3922 	e->u.aenfx.count = cnt;
3923 	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3924 	return qla2x00_post_work(vha, e);
3925 }
3926 
3927 void
qla2x00_do_work(struct scsi_qla_host * vha)3928 qla2x00_do_work(struct scsi_qla_host *vha)
3929 {
3930 	struct qla_work_evt *e, *tmp;
3931 	unsigned long flags;
3932 	LIST_HEAD(work);
3933 
3934 	spin_lock_irqsave(&vha->work_lock, flags);
3935 	list_splice_init(&vha->work_list, &work);
3936 	spin_unlock_irqrestore(&vha->work_lock, flags);
3937 
3938 	list_for_each_entry_safe(e, tmp, &work, list) {
3939 		list_del_init(&e->list);
3940 
3941 		switch (e->type) {
3942 		case QLA_EVT_AEN:
3943 			fc_host_post_event(vha->host, fc_get_event_number(),
3944 			    e->u.aen.code, e->u.aen.data);
3945 			break;
3946 		case QLA_EVT_IDC_ACK:
3947 			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3948 			break;
3949 		case QLA_EVT_ASYNC_LOGIN:
3950 			qla2x00_async_login(vha, e->u.logio.fcport,
3951 			    e->u.logio.data);
3952 			break;
3953 		case QLA_EVT_ASYNC_LOGIN_DONE:
3954 			qla2x00_async_login_done(vha, e->u.logio.fcport,
3955 			    e->u.logio.data);
3956 			break;
3957 		case QLA_EVT_ASYNC_LOGOUT:
3958 			qla2x00_async_logout(vha, e->u.logio.fcport);
3959 			break;
3960 		case QLA_EVT_ASYNC_LOGOUT_DONE:
3961 			qla2x00_async_logout_done(vha, e->u.logio.fcport,
3962 			    e->u.logio.data);
3963 			break;
3964 		case QLA_EVT_ASYNC_ADISC:
3965 			qla2x00_async_adisc(vha, e->u.logio.fcport,
3966 			    e->u.logio.data);
3967 			break;
3968 		case QLA_EVT_ASYNC_ADISC_DONE:
3969 			qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3970 			    e->u.logio.data);
3971 			break;
3972 		case QLA_EVT_UEVENT:
3973 			qla2x00_uevent_emit(vha, e->u.uevent.code);
3974 			break;
3975 		case QLA_EVT_AENFX:
3976 			qlafx00_process_aen(vha, e);
3977 			break;
3978 		}
3979 		if (e->flags & QLA_EVT_FLAG_FREE)
3980 			kfree(e);
3981 
3982 		/* For each work completed decrement vha ref count */
3983 		QLA_VHA_MARK_NOT_BUSY(vha);
3984 	}
3985 }
3986 
3987 /* Relogins all the fcports of a vport
3988  * Context: dpc thread
3989  */
qla2x00_relogin(struct scsi_qla_host * vha)3990 void qla2x00_relogin(struct scsi_qla_host *vha)
3991 {
3992 	fc_port_t       *fcport;
3993 	int status;
3994 	uint16_t        next_loopid = 0;
3995 	struct qla_hw_data *ha = vha->hw;
3996 	uint16_t data[2];
3997 
3998 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
3999 	/*
4000 	 * If the port is not ONLINE then try to login
4001 	 * to it if we haven't run out of retries.
4002 	 */
4003 		if (atomic_read(&fcport->state) != FCS_ONLINE &&
4004 		    fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4005 			fcport->login_retry--;
4006 			if (fcport->flags & FCF_FABRIC_DEVICE) {
4007 				if (fcport->flags & FCF_FCP2_DEVICE)
4008 					ha->isp_ops->fabric_logout(vha,
4009 							fcport->loop_id,
4010 							fcport->d_id.b.domain,
4011 							fcport->d_id.b.area,
4012 							fcport->d_id.b.al_pa);
4013 
4014 				if (fcport->loop_id == FC_NO_LOOP_ID) {
4015 					fcport->loop_id = next_loopid =
4016 					    ha->min_external_loopid;
4017 					status = qla2x00_find_new_loop_id(
4018 					    vha, fcport);
4019 					if (status != QLA_SUCCESS) {
4020 						/* Ran out of IDs to use */
4021 						break;
4022 					}
4023 				}
4024 
4025 				if (IS_ALOGIO_CAPABLE(ha)) {
4026 					fcport->flags |= FCF_ASYNC_SENT;
4027 					data[0] = 0;
4028 					data[1] = QLA_LOGIO_LOGIN_RETRIED;
4029 					status = qla2x00_post_async_login_work(
4030 					    vha, fcport, data);
4031 					if (status == QLA_SUCCESS)
4032 						continue;
4033 					/* Attempt a retry. */
4034 					status = 1;
4035 				} else {
4036 					status = qla2x00_fabric_login(vha,
4037 					    fcport, &next_loopid);
4038 					if (status ==  QLA_SUCCESS) {
4039 						int status2;
4040 						uint8_t opts;
4041 
4042 						opts = 0;
4043 						if (fcport->flags &
4044 						    FCF_FCP2_DEVICE)
4045 							opts |= BIT_1;
4046 						status2 =
4047 						    qla2x00_get_port_database(
4048 							vha, fcport, opts);
4049 						if (status2 != QLA_SUCCESS)
4050 							status = 1;
4051 					}
4052 				}
4053 			} else
4054 				status = qla2x00_local_device_login(vha,
4055 								fcport);
4056 
4057 			if (status == QLA_SUCCESS) {
4058 				fcport->old_loop_id = fcport->loop_id;
4059 
4060 				ql_dbg(ql_dbg_disc, vha, 0x2003,
4061 				    "Port login OK: logged in ID 0x%x.\n",
4062 				    fcport->loop_id);
4063 
4064 				qla2x00_update_fcport(vha, fcport);
4065 
4066 			} else if (status == 1) {
4067 				set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4068 				/* retry the login again */
4069 				ql_dbg(ql_dbg_disc, vha, 0x2007,
4070 				    "Retrying %d login again loop_id 0x%x.\n",
4071 				    fcport->login_retry, fcport->loop_id);
4072 			} else {
4073 				fcport->login_retry = 0;
4074 			}
4075 
4076 			if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4077 				qla2x00_clear_loop_id(fcport);
4078 		}
4079 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4080 			break;
4081 	}
4082 }
4083 
4084 /* Schedule work on any of the dpc-workqueues */
4085 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)4086 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4087 {
4088 	struct qla_hw_data *ha = base_vha->hw;
4089 
4090 	switch (work_code) {
4091 	case MBA_IDC_AEN: /* 0x8200 */
4092 		if (ha->dpc_lp_wq)
4093 			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4094 		break;
4095 
4096 	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4097 		if (!ha->flags.nic_core_reset_hdlr_active) {
4098 			if (ha->dpc_hp_wq)
4099 				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4100 		} else
4101 			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4102 			    "NIC Core reset is already active. Skip "
4103 			    "scheduling it again.\n");
4104 		break;
4105 	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4106 		if (ha->dpc_hp_wq)
4107 			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4108 		break;
4109 	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4110 		if (ha->dpc_hp_wq)
4111 			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4112 		break;
4113 	default:
4114 		ql_log(ql_log_warn, base_vha, 0xb05f,
4115 		    "Unknown work-code=0x%x.\n", work_code);
4116 	}
4117 
4118 	return;
4119 }
4120 
4121 /* Work: Perform NIC Core Unrecoverable state handling */
4122 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)4123 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4124 {
4125 	struct qla_hw_data *ha =
4126 		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4127 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4128 	uint32_t dev_state = 0;
4129 
4130 	qla83xx_idc_lock(base_vha, 0);
4131 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4132 	qla83xx_reset_ownership(base_vha);
4133 	if (ha->flags.nic_core_reset_owner) {
4134 		ha->flags.nic_core_reset_owner = 0;
4135 		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4136 		    QLA8XXX_DEV_FAILED);
4137 		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4138 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4139 	}
4140 	qla83xx_idc_unlock(base_vha, 0);
4141 }
4142 
4143 /* Work: Execute IDC state handler */
4144 void
qla83xx_idc_state_handler_work(struct work_struct * work)4145 qla83xx_idc_state_handler_work(struct work_struct *work)
4146 {
4147 	struct qla_hw_data *ha =
4148 		container_of(work, struct qla_hw_data, idc_state_handler);
4149 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4150 	uint32_t dev_state = 0;
4151 
4152 	qla83xx_idc_lock(base_vha, 0);
4153 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4154 	if (dev_state == QLA8XXX_DEV_FAILED ||
4155 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4156 		qla83xx_idc_state_handler(base_vha);
4157 	qla83xx_idc_unlock(base_vha, 0);
4158 }
4159 
4160 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)4161 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4162 {
4163 	int rval = QLA_SUCCESS;
4164 	unsigned long heart_beat_wait = jiffies + (1 * HZ);
4165 	uint32_t heart_beat_counter1, heart_beat_counter2;
4166 
4167 	do {
4168 		if (time_after(jiffies, heart_beat_wait)) {
4169 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4170 			    "Nic Core f/w is not alive.\n");
4171 			rval = QLA_FUNCTION_FAILED;
4172 			break;
4173 		}
4174 
4175 		qla83xx_idc_lock(base_vha, 0);
4176 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4177 		    &heart_beat_counter1);
4178 		qla83xx_idc_unlock(base_vha, 0);
4179 		msleep(100);
4180 		qla83xx_idc_lock(base_vha, 0);
4181 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4182 		    &heart_beat_counter2);
4183 		qla83xx_idc_unlock(base_vha, 0);
4184 	} while (heart_beat_counter1 == heart_beat_counter2);
4185 
4186 	return rval;
4187 }
4188 
4189 /* Work: Perform NIC Core Reset handling */
4190 void
qla83xx_nic_core_reset_work(struct work_struct * work)4191 qla83xx_nic_core_reset_work(struct work_struct *work)
4192 {
4193 	struct qla_hw_data *ha =
4194 		container_of(work, struct qla_hw_data, nic_core_reset);
4195 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4196 	uint32_t dev_state = 0;
4197 
4198 	if (IS_QLA2031(ha)) {
4199 		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4200 			ql_log(ql_log_warn, base_vha, 0xb081,
4201 			    "Failed to dump mctp\n");
4202 		return;
4203 	}
4204 
4205 	if (!ha->flags.nic_core_reset_hdlr_active) {
4206 		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4207 			qla83xx_idc_lock(base_vha, 0);
4208 			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4209 			    &dev_state);
4210 			qla83xx_idc_unlock(base_vha, 0);
4211 			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4212 				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4213 				    "Nic Core f/w is alive.\n");
4214 				return;
4215 			}
4216 		}
4217 
4218 		ha->flags.nic_core_reset_hdlr_active = 1;
4219 		if (qla83xx_nic_core_reset(base_vha)) {
4220 			/* NIC Core reset failed. */
4221 			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4222 			    "NIC Core reset failed.\n");
4223 		}
4224 		ha->flags.nic_core_reset_hdlr_active = 0;
4225 	}
4226 }
4227 
4228 /* Work: Handle 8200 IDC aens */
4229 void
qla83xx_service_idc_aen(struct work_struct * work)4230 qla83xx_service_idc_aen(struct work_struct *work)
4231 {
4232 	struct qla_hw_data *ha =
4233 		container_of(work, struct qla_hw_data, idc_aen);
4234 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4235 	uint32_t dev_state, idc_control;
4236 
4237 	qla83xx_idc_lock(base_vha, 0);
4238 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4239 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4240 	qla83xx_idc_unlock(base_vha, 0);
4241 	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4242 		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4243 			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4244 			    "Application requested NIC Core Reset.\n");
4245 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4246 		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4247 		    QLA_SUCCESS) {
4248 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4249 			    "Other protocol driver requested NIC Core Reset.\n");
4250 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4251 		}
4252 	} else if (dev_state == QLA8XXX_DEV_FAILED ||
4253 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4254 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4255 	}
4256 }
4257 
4258 static void
qla83xx_wait_logic(void)4259 qla83xx_wait_logic(void)
4260 {
4261 	int i;
4262 
4263 	/* Yield CPU */
4264 	if (!in_interrupt()) {
4265 		/*
4266 		 * Wait about 200ms before retrying again.
4267 		 * This controls the number of retries for single
4268 		 * lock operation.
4269 		 */
4270 		msleep(100);
4271 		schedule();
4272 	} else {
4273 		for (i = 0; i < 20; i++)
4274 			cpu_relax(); /* This a nop instr on i386 */
4275 	}
4276 }
4277 
4278 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)4279 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4280 {
4281 	int rval;
4282 	uint32_t data;
4283 	uint32_t idc_lck_rcvry_stage_mask = 0x3;
4284 	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4285 	struct qla_hw_data *ha = base_vha->hw;
4286 	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4287 	    "Trying force recovery of the IDC lock.\n");
4288 
4289 	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4290 	if (rval)
4291 		return rval;
4292 
4293 	if ((data & idc_lck_rcvry_stage_mask) > 0) {
4294 		return QLA_SUCCESS;
4295 	} else {
4296 		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4297 		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4298 		    data);
4299 		if (rval)
4300 			return rval;
4301 
4302 		msleep(200);
4303 
4304 		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4305 		    &data);
4306 		if (rval)
4307 			return rval;
4308 
4309 		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4310 			data &= (IDC_LOCK_RECOVERY_STAGE2 |
4311 					~(idc_lck_rcvry_stage_mask));
4312 			rval = qla83xx_wr_reg(base_vha,
4313 			    QLA83XX_IDC_LOCK_RECOVERY, data);
4314 			if (rval)
4315 				return rval;
4316 
4317 			/* Forcefully perform IDC UnLock */
4318 			rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4319 			    &data);
4320 			if (rval)
4321 				return rval;
4322 			/* Clear lock-id by setting 0xff */
4323 			rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4324 			    0xff);
4325 			if (rval)
4326 				return rval;
4327 			/* Clear lock-recovery by setting 0x0 */
4328 			rval = qla83xx_wr_reg(base_vha,
4329 			    QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4330 			if (rval)
4331 				return rval;
4332 		} else
4333 			return QLA_SUCCESS;
4334 	}
4335 
4336 	return rval;
4337 }
4338 
4339 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)4340 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4341 {
4342 	int rval = QLA_SUCCESS;
4343 	uint32_t o_drv_lockid, n_drv_lockid;
4344 	unsigned long lock_recovery_timeout;
4345 
4346 	lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4347 retry_lockid:
4348 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4349 	if (rval)
4350 		goto exit;
4351 
4352 	/* MAX wait time before forcing IDC Lock recovery = 2 secs */
4353 	if (time_after_eq(jiffies, lock_recovery_timeout)) {
4354 		if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4355 			return QLA_SUCCESS;
4356 		else
4357 			return QLA_FUNCTION_FAILED;
4358 	}
4359 
4360 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4361 	if (rval)
4362 		goto exit;
4363 
4364 	if (o_drv_lockid == n_drv_lockid) {
4365 		qla83xx_wait_logic();
4366 		goto retry_lockid;
4367 	} else
4368 		return QLA_SUCCESS;
4369 
4370 exit:
4371 	return rval;
4372 }
4373 
4374 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)4375 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4376 {
4377 	uint16_t options = (requester_id << 15) | BIT_6;
4378 	uint32_t data;
4379 	uint32_t lock_owner;
4380 	struct qla_hw_data *ha = base_vha->hw;
4381 
4382 	/* IDC-lock implementation using driver-lock/lock-id remote registers */
4383 retry_lock:
4384 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4385 	    == QLA_SUCCESS) {
4386 		if (data) {
4387 			/* Setting lock-id to our function-number */
4388 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4389 			    ha->portnum);
4390 		} else {
4391 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4392 			    &lock_owner);
4393 			ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4394 			    "Failed to acquire IDC lock, acquired by %d, "
4395 			    "retrying...\n", lock_owner);
4396 
4397 			/* Retry/Perform IDC-Lock recovery */
4398 			if (qla83xx_idc_lock_recovery(base_vha)
4399 			    == QLA_SUCCESS) {
4400 				qla83xx_wait_logic();
4401 				goto retry_lock;
4402 			} else
4403 				ql_log(ql_log_warn, base_vha, 0xb075,
4404 				    "IDC Lock recovery FAILED.\n");
4405 		}
4406 
4407 	}
4408 
4409 	return;
4410 
4411 	/* XXX: IDC-lock implementation using access-control mbx */
4412 retry_lock2:
4413 	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4414 		ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4415 		    "Failed to acquire IDC lock. retrying...\n");
4416 		/* Retry/Perform IDC-Lock recovery */
4417 		if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4418 			qla83xx_wait_logic();
4419 			goto retry_lock2;
4420 		} else
4421 			ql_log(ql_log_warn, base_vha, 0xb076,
4422 			    "IDC Lock recovery FAILED.\n");
4423 	}
4424 
4425 	return;
4426 }
4427 
4428 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)4429 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4430 {
4431 #if 0
4432 	uint16_t options = (requester_id << 15) | BIT_7;
4433 #endif
4434 	uint16_t retry;
4435 	uint32_t data;
4436 	struct qla_hw_data *ha = base_vha->hw;
4437 
4438 	/* IDC-unlock implementation using driver-unlock/lock-id
4439 	 * remote registers
4440 	 */
4441 	retry = 0;
4442 retry_unlock:
4443 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4444 	    == QLA_SUCCESS) {
4445 		if (data == ha->portnum) {
4446 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4447 			/* Clearing lock-id by setting 0xff */
4448 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4449 		} else if (retry < 10) {
4450 			/* SV: XXX: IDC unlock retrying needed here? */
4451 
4452 			/* Retry for IDC-unlock */
4453 			qla83xx_wait_logic();
4454 			retry++;
4455 			ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4456 			    "Failed to release IDC lock, retyring=%d\n", retry);
4457 			goto retry_unlock;
4458 		}
4459 	} else if (retry < 10) {
4460 		/* Retry for IDC-unlock */
4461 		qla83xx_wait_logic();
4462 		retry++;
4463 		ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4464 		    "Failed to read drv-lockid, retyring=%d\n", retry);
4465 		goto retry_unlock;
4466 	}
4467 
4468 	return;
4469 
4470 #if 0
4471 	/* XXX: IDC-unlock implementation using access-control mbx */
4472 	retry = 0;
4473 retry_unlock2:
4474 	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4475 		if (retry < 10) {
4476 			/* Retry for IDC-unlock */
4477 			qla83xx_wait_logic();
4478 			retry++;
4479 			ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4480 			    "Failed to release IDC lock, retyring=%d\n", retry);
4481 			goto retry_unlock2;
4482 		}
4483 	}
4484 
4485 	return;
4486 #endif
4487 }
4488 
4489 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)4490 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4491 {
4492 	int rval = QLA_SUCCESS;
4493 	struct qla_hw_data *ha = vha->hw;
4494 	uint32_t drv_presence;
4495 
4496 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4497 	if (rval == QLA_SUCCESS) {
4498 		drv_presence |= (1 << ha->portnum);
4499 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4500 		    drv_presence);
4501 	}
4502 
4503 	return rval;
4504 }
4505 
4506 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)4507 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4508 {
4509 	int rval = QLA_SUCCESS;
4510 
4511 	qla83xx_idc_lock(vha, 0);
4512 	rval = __qla83xx_set_drv_presence(vha);
4513 	qla83xx_idc_unlock(vha, 0);
4514 
4515 	return rval;
4516 }
4517 
4518 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)4519 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4520 {
4521 	int rval = QLA_SUCCESS;
4522 	struct qla_hw_data *ha = vha->hw;
4523 	uint32_t drv_presence;
4524 
4525 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4526 	if (rval == QLA_SUCCESS) {
4527 		drv_presence &= ~(1 << ha->portnum);
4528 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4529 		    drv_presence);
4530 	}
4531 
4532 	return rval;
4533 }
4534 
4535 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)4536 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4537 {
4538 	int rval = QLA_SUCCESS;
4539 
4540 	qla83xx_idc_lock(vha, 0);
4541 	rval = __qla83xx_clear_drv_presence(vha);
4542 	qla83xx_idc_unlock(vha, 0);
4543 
4544 	return rval;
4545 }
4546 
4547 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)4548 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4549 {
4550 	struct qla_hw_data *ha = vha->hw;
4551 	uint32_t drv_ack, drv_presence;
4552 	unsigned long ack_timeout;
4553 
4554 	/* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4555 	ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4556 	while (1) {
4557 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4558 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4559 		if ((drv_ack & drv_presence) == drv_presence)
4560 			break;
4561 
4562 		if (time_after_eq(jiffies, ack_timeout)) {
4563 			ql_log(ql_log_warn, vha, 0xb067,
4564 			    "RESET ACK TIMEOUT! drv_presence=0x%x "
4565 			    "drv_ack=0x%x\n", drv_presence, drv_ack);
4566 			/*
4567 			 * The function(s) which did not ack in time are forced
4568 			 * to withdraw any further participation in the IDC
4569 			 * reset.
4570 			 */
4571 			if (drv_ack != drv_presence)
4572 				qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4573 				    drv_ack);
4574 			break;
4575 		}
4576 
4577 		qla83xx_idc_unlock(vha, 0);
4578 		msleep(1000);
4579 		qla83xx_idc_lock(vha, 0);
4580 	}
4581 
4582 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4583 	ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4584 }
4585 
4586 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)4587 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4588 {
4589 	int rval = QLA_SUCCESS;
4590 	uint32_t idc_control;
4591 
4592 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4593 	ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4594 
4595 	/* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4596 	__qla83xx_get_idc_control(vha, &idc_control);
4597 	idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4598 	__qla83xx_set_idc_control(vha, 0);
4599 
4600 	qla83xx_idc_unlock(vha, 0);
4601 	rval = qla83xx_restart_nic_firmware(vha);
4602 	qla83xx_idc_lock(vha, 0);
4603 
4604 	if (rval != QLA_SUCCESS) {
4605 		ql_log(ql_log_fatal, vha, 0xb06a,
4606 		    "Failed to restart NIC f/w.\n");
4607 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4608 		ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4609 	} else {
4610 		ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4611 		    "Success in restarting nic f/w.\n");
4612 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4613 		ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4614 	}
4615 
4616 	return rval;
4617 }
4618 
4619 /* Assumes idc_lock always held on entry */
4620 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)4621 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4622 {
4623 	struct qla_hw_data *ha = base_vha->hw;
4624 	int rval = QLA_SUCCESS;
4625 	unsigned long dev_init_timeout;
4626 	uint32_t dev_state;
4627 
4628 	/* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4629 	dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4630 
4631 	while (1) {
4632 
4633 		if (time_after_eq(jiffies, dev_init_timeout)) {
4634 			ql_log(ql_log_warn, base_vha, 0xb06e,
4635 			    "Initialization TIMEOUT!\n");
4636 			/* Init timeout. Disable further NIC Core
4637 			 * communication.
4638 			 */
4639 			qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4640 				QLA8XXX_DEV_FAILED);
4641 			ql_log(ql_log_info, base_vha, 0xb06f,
4642 			    "HW State: FAILED.\n");
4643 		}
4644 
4645 		qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4646 		switch (dev_state) {
4647 		case QLA8XXX_DEV_READY:
4648 			if (ha->flags.nic_core_reset_owner)
4649 				qla83xx_idc_audit(base_vha,
4650 				    IDC_AUDIT_COMPLETION);
4651 			ha->flags.nic_core_reset_owner = 0;
4652 			ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4653 			    "Reset_owner reset by 0x%x.\n",
4654 			    ha->portnum);
4655 			goto exit;
4656 		case QLA8XXX_DEV_COLD:
4657 			if (ha->flags.nic_core_reset_owner)
4658 				rval = qla83xx_device_bootstrap(base_vha);
4659 			else {
4660 			/* Wait for AEN to change device-state */
4661 				qla83xx_idc_unlock(base_vha, 0);
4662 				msleep(1000);
4663 				qla83xx_idc_lock(base_vha, 0);
4664 			}
4665 			break;
4666 		case QLA8XXX_DEV_INITIALIZING:
4667 			/* Wait for AEN to change device-state */
4668 			qla83xx_idc_unlock(base_vha, 0);
4669 			msleep(1000);
4670 			qla83xx_idc_lock(base_vha, 0);
4671 			break;
4672 		case QLA8XXX_DEV_NEED_RESET:
4673 			if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4674 				qla83xx_need_reset_handler(base_vha);
4675 			else {
4676 				/* Wait for AEN to change device-state */
4677 				qla83xx_idc_unlock(base_vha, 0);
4678 				msleep(1000);
4679 				qla83xx_idc_lock(base_vha, 0);
4680 			}
4681 			/* reset timeout value after need reset handler */
4682 			dev_init_timeout = jiffies +
4683 			    (ha->fcoe_dev_init_timeout * HZ);
4684 			break;
4685 		case QLA8XXX_DEV_NEED_QUIESCENT:
4686 			/* XXX: DEBUG for now */
4687 			qla83xx_idc_unlock(base_vha, 0);
4688 			msleep(1000);
4689 			qla83xx_idc_lock(base_vha, 0);
4690 			break;
4691 		case QLA8XXX_DEV_QUIESCENT:
4692 			/* XXX: DEBUG for now */
4693 			if (ha->flags.quiesce_owner)
4694 				goto exit;
4695 
4696 			qla83xx_idc_unlock(base_vha, 0);
4697 			msleep(1000);
4698 			qla83xx_idc_lock(base_vha, 0);
4699 			dev_init_timeout = jiffies +
4700 			    (ha->fcoe_dev_init_timeout * HZ);
4701 			break;
4702 		case QLA8XXX_DEV_FAILED:
4703 			if (ha->flags.nic_core_reset_owner)
4704 				qla83xx_idc_audit(base_vha,
4705 				    IDC_AUDIT_COMPLETION);
4706 			ha->flags.nic_core_reset_owner = 0;
4707 			__qla83xx_clear_drv_presence(base_vha);
4708 			qla83xx_idc_unlock(base_vha, 0);
4709 			qla8xxx_dev_failed_handler(base_vha);
4710 			rval = QLA_FUNCTION_FAILED;
4711 			qla83xx_idc_lock(base_vha, 0);
4712 			goto exit;
4713 		case QLA8XXX_BAD_VALUE:
4714 			qla83xx_idc_unlock(base_vha, 0);
4715 			msleep(1000);
4716 			qla83xx_idc_lock(base_vha, 0);
4717 			break;
4718 		default:
4719 			ql_log(ql_log_warn, base_vha, 0xb071,
4720 			    "Unknown Device State: %x.\n", dev_state);
4721 			qla83xx_idc_unlock(base_vha, 0);
4722 			qla8xxx_dev_failed_handler(base_vha);
4723 			rval = QLA_FUNCTION_FAILED;
4724 			qla83xx_idc_lock(base_vha, 0);
4725 			goto exit;
4726 		}
4727 	}
4728 
4729 exit:
4730 	return rval;
4731 }
4732 
4733 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)4734 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4735 {
4736 	struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4737 	    board_disable);
4738 	struct pci_dev *pdev = ha->pdev;
4739 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4740 
4741 	ql_log(ql_log_warn, base_vha, 0x015b,
4742 	    "Disabling adapter.\n");
4743 
4744 	set_bit(UNLOADING, &base_vha->dpc_flags);
4745 
4746 	qla2x00_delete_all_vps(ha, base_vha);
4747 
4748 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4749 
4750 	qla2x00_dfs_remove(base_vha);
4751 
4752 	qla84xx_put_chip(base_vha);
4753 
4754 	if (base_vha->timer_active)
4755 		qla2x00_stop_timer(base_vha);
4756 
4757 	base_vha->flags.online = 0;
4758 
4759 	qla2x00_destroy_deferred_work(ha);
4760 
4761 	/*
4762 	 * Do not try to stop beacon blink as it will issue a mailbox
4763 	 * command.
4764 	 */
4765 	qla2x00_free_sysfs_attr(base_vha, false);
4766 
4767 	fc_remove_host(base_vha->host);
4768 
4769 	scsi_remove_host(base_vha->host);
4770 
4771 	base_vha->flags.init_done = 0;
4772 	qla25xx_delete_queues(base_vha);
4773 	qla2x00_free_irqs(base_vha);
4774 	qla2x00_free_fcports(base_vha);
4775 	qla2x00_mem_free(ha);
4776 	qla82xx_md_free(base_vha);
4777 	qla2x00_free_queues(ha);
4778 
4779 	qla2x00_unmap_iobases(ha);
4780 
4781 	pci_release_selected_regions(ha->pdev, ha->bars);
4782 	pci_disable_pcie_error_reporting(pdev);
4783 	pci_disable_device(pdev);
4784 
4785 	/*
4786 	 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4787 	 */
4788 }
4789 
4790 /**************************************************************************
4791 * qla2x00_do_dpc
4792 *   This kernel thread is a task that is schedule by the interrupt handler
4793 *   to perform the background processing for interrupts.
4794 *
4795 * Notes:
4796 * This task always run in the context of a kernel thread.  It
4797 * is kick-off by the driver's detect code and starts up
4798 * up one per adapter. It immediately goes to sleep and waits for
4799 * some fibre event.  When either the interrupt handler or
4800 * the timer routine detects a event it will one of the task
4801 * bits then wake us up.
4802 **************************************************************************/
4803 static int
qla2x00_do_dpc(void * data)4804 qla2x00_do_dpc(void *data)
4805 {
4806 	scsi_qla_host_t *base_vha;
4807 	struct qla_hw_data *ha;
4808 
4809 	ha = (struct qla_hw_data *)data;
4810 	base_vha = pci_get_drvdata(ha->pdev);
4811 
4812 	set_user_nice(current, MIN_NICE);
4813 
4814 	set_current_state(TASK_INTERRUPTIBLE);
4815 	while (!kthread_should_stop()) {
4816 		ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4817 		    "DPC handler sleeping.\n");
4818 
4819 		schedule();
4820 
4821 		if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4822 			goto end_loop;
4823 
4824 		if (ha->flags.eeh_busy) {
4825 			ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4826 			    "eeh_busy=%d.\n", ha->flags.eeh_busy);
4827 			goto end_loop;
4828 		}
4829 
4830 		ha->dpc_active = 1;
4831 
4832 		ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4833 		    "DPC handler waking up, dpc_flags=0x%lx.\n",
4834 		    base_vha->dpc_flags);
4835 
4836 		qla2x00_do_work(base_vha);
4837 
4838 		if (IS_P3P_TYPE(ha)) {
4839 			if (IS_QLA8044(ha)) {
4840 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
4841 					&base_vha->dpc_flags)) {
4842 					qla8044_idc_lock(ha);
4843 					qla8044_wr_direct(base_vha,
4844 						QLA8044_CRB_DEV_STATE_INDEX,
4845 						QLA8XXX_DEV_FAILED);
4846 					qla8044_idc_unlock(ha);
4847 					ql_log(ql_log_info, base_vha, 0x4004,
4848 						"HW State: FAILED.\n");
4849 					qla8044_device_state_handler(base_vha);
4850 					continue;
4851 				}
4852 
4853 			} else {
4854 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
4855 					&base_vha->dpc_flags)) {
4856 					qla82xx_idc_lock(ha);
4857 					qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4858 						QLA8XXX_DEV_FAILED);
4859 					qla82xx_idc_unlock(ha);
4860 					ql_log(ql_log_info, base_vha, 0x0151,
4861 						"HW State: FAILED.\n");
4862 					qla82xx_device_state_handler(base_vha);
4863 					continue;
4864 				}
4865 			}
4866 
4867 			if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4868 				&base_vha->dpc_flags)) {
4869 
4870 				ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4871 				    "FCoE context reset scheduled.\n");
4872 				if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4873 					&base_vha->dpc_flags))) {
4874 					if (qla82xx_fcoe_ctx_reset(base_vha)) {
4875 						/* FCoE-ctx reset failed.
4876 						 * Escalate to chip-reset
4877 						 */
4878 						set_bit(ISP_ABORT_NEEDED,
4879 							&base_vha->dpc_flags);
4880 					}
4881 					clear_bit(ABORT_ISP_ACTIVE,
4882 						&base_vha->dpc_flags);
4883 				}
4884 
4885 				ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4886 				    "FCoE context reset end.\n");
4887 			}
4888 		} else if (IS_QLAFX00(ha)) {
4889 			if (test_and_clear_bit(ISP_UNRECOVERABLE,
4890 				&base_vha->dpc_flags)) {
4891 				ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4892 				    "Firmware Reset Recovery\n");
4893 				if (qlafx00_reset_initialize(base_vha)) {
4894 					/* Failed. Abort isp later. */
4895 					if (!test_bit(UNLOADING,
4896 					    &base_vha->dpc_flags)) {
4897 						set_bit(ISP_UNRECOVERABLE,
4898 						    &base_vha->dpc_flags);
4899 						ql_dbg(ql_dbg_dpc, base_vha,
4900 						    0x4021,
4901 						    "Reset Recovery Failed\n");
4902 					}
4903 				}
4904 			}
4905 
4906 			if (test_and_clear_bit(FX00_TARGET_SCAN,
4907 				&base_vha->dpc_flags)) {
4908 				ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4909 				    "ISPFx00 Target Scan scheduled\n");
4910 				if (qlafx00_rescan_isp(base_vha)) {
4911 					if (!test_bit(UNLOADING,
4912 					    &base_vha->dpc_flags))
4913 						set_bit(ISP_UNRECOVERABLE,
4914 						    &base_vha->dpc_flags);
4915 					ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4916 					    "ISPFx00 Target Scan Failed\n");
4917 				}
4918 				ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4919 				    "ISPFx00 Target Scan End\n");
4920 			}
4921 			if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4922 				&base_vha->dpc_flags)) {
4923 				ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4924 				    "ISPFx00 Host Info resend scheduled\n");
4925 				qlafx00_fx_disc(base_vha,
4926 				    &base_vha->hw->mr.fcport,
4927 				    FXDISC_REG_HOST_INFO);
4928 			}
4929 		}
4930 
4931 		if (test_and_clear_bit(ISP_ABORT_NEEDED,
4932 						&base_vha->dpc_flags)) {
4933 
4934 			ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4935 			    "ISP abort scheduled.\n");
4936 			if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4937 			    &base_vha->dpc_flags))) {
4938 
4939 				if (ha->isp_ops->abort_isp(base_vha)) {
4940 					/* failed. retry later */
4941 					set_bit(ISP_ABORT_NEEDED,
4942 					    &base_vha->dpc_flags);
4943 				}
4944 				clear_bit(ABORT_ISP_ACTIVE,
4945 						&base_vha->dpc_flags);
4946 			}
4947 
4948 			ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4949 			    "ISP abort end.\n");
4950 		}
4951 
4952 		if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4953 		    &base_vha->dpc_flags)) {
4954 			qla2x00_update_fcports(base_vha);
4955 		}
4956 
4957 		if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4958 			int ret;
4959 			ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4960 			if (ret != QLA_SUCCESS)
4961 				ql_log(ql_log_warn, base_vha, 0x121,
4962 				    "Failed to enable receiving of RSCN "
4963 				    "requests: 0x%x.\n", ret);
4964 			clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4965 		}
4966 
4967 		if (IS_QLAFX00(ha))
4968 			goto loop_resync_check;
4969 
4970 		if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4971 			ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4972 			    "Quiescence mode scheduled.\n");
4973 			if (IS_P3P_TYPE(ha)) {
4974 				if (IS_QLA82XX(ha))
4975 					qla82xx_device_state_handler(base_vha);
4976 				if (IS_QLA8044(ha))
4977 					qla8044_device_state_handler(base_vha);
4978 				clear_bit(ISP_QUIESCE_NEEDED,
4979 				    &base_vha->dpc_flags);
4980 				if (!ha->flags.quiesce_owner) {
4981 					qla2x00_perform_loop_resync(base_vha);
4982 					if (IS_QLA82XX(ha)) {
4983 						qla82xx_idc_lock(ha);
4984 						qla82xx_clear_qsnt_ready(
4985 						    base_vha);
4986 						qla82xx_idc_unlock(ha);
4987 					} else if (IS_QLA8044(ha)) {
4988 						qla8044_idc_lock(ha);
4989 						qla8044_clear_qsnt_ready(
4990 						    base_vha);
4991 						qla8044_idc_unlock(ha);
4992 					}
4993 				}
4994 			} else {
4995 				clear_bit(ISP_QUIESCE_NEEDED,
4996 				    &base_vha->dpc_flags);
4997 				qla2x00_quiesce_io(base_vha);
4998 			}
4999 			ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5000 			    "Quiescence mode end.\n");
5001 		}
5002 
5003 		if (test_and_clear_bit(RESET_MARKER_NEEDED,
5004 				&base_vha->dpc_flags) &&
5005 		    (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5006 
5007 			ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5008 			    "Reset marker scheduled.\n");
5009 			qla2x00_rst_aen(base_vha);
5010 			clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5011 			ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5012 			    "Reset marker end.\n");
5013 		}
5014 
5015 		/* Retry each device up to login retry count */
5016 		if ((test_and_clear_bit(RELOGIN_NEEDED,
5017 						&base_vha->dpc_flags)) &&
5018 		    !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5019 		    atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5020 
5021 			ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5022 			    "Relogin scheduled.\n");
5023 			qla2x00_relogin(base_vha);
5024 			ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5025 			    "Relogin end.\n");
5026 		}
5027 loop_resync_check:
5028 		if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5029 		    &base_vha->dpc_flags)) {
5030 
5031 			ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5032 			    "Loop resync scheduled.\n");
5033 
5034 			if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5035 			    &base_vha->dpc_flags))) {
5036 
5037 				qla2x00_loop_resync(base_vha);
5038 
5039 				clear_bit(LOOP_RESYNC_ACTIVE,
5040 						&base_vha->dpc_flags);
5041 			}
5042 
5043 			ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5044 			    "Loop resync end.\n");
5045 		}
5046 
5047 		if (IS_QLAFX00(ha))
5048 			goto intr_on_check;
5049 
5050 		if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5051 		    atomic_read(&base_vha->loop_state) == LOOP_READY) {
5052 			clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5053 			qla2xxx_flash_npiv_conf(base_vha);
5054 		}
5055 
5056 intr_on_check:
5057 		if (!ha->interrupts_on)
5058 			ha->isp_ops->enable_intrs(ha);
5059 
5060 		if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5061 					&base_vha->dpc_flags)) {
5062 			if (ha->beacon_blink_led == 1)
5063 				ha->isp_ops->beacon_blink(base_vha);
5064 		}
5065 
5066 		if (!IS_QLAFX00(ha))
5067 			qla2x00_do_dpc_all_vps(base_vha);
5068 
5069 		ha->dpc_active = 0;
5070 end_loop:
5071 		set_current_state(TASK_INTERRUPTIBLE);
5072 	} /* End of while(1) */
5073 	__set_current_state(TASK_RUNNING);
5074 
5075 	ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5076 	    "DPC handler exiting.\n");
5077 
5078 	/*
5079 	 * Make sure that nobody tries to wake us up again.
5080 	 */
5081 	ha->dpc_active = 0;
5082 
5083 	/* Cleanup any residual CTX SRBs. */
5084 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5085 
5086 	return 0;
5087 }
5088 
5089 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)5090 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5091 {
5092 	struct qla_hw_data *ha = vha->hw;
5093 	struct task_struct *t = ha->dpc_thread;
5094 
5095 	if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5096 		wake_up_process(t);
5097 }
5098 
5099 /*
5100 *  qla2x00_rst_aen
5101 *      Processes asynchronous reset.
5102 *
5103 * Input:
5104 *      ha  = adapter block pointer.
5105 */
5106 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)5107 qla2x00_rst_aen(scsi_qla_host_t *vha)
5108 {
5109 	if (vha->flags.online && !vha->flags.reset_active &&
5110 	    !atomic_read(&vha->loop_down_timer) &&
5111 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5112 		do {
5113 			clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5114 
5115 			/*
5116 			 * Issue marker command only when we are going to start
5117 			 * the I/O.
5118 			 */
5119 			vha->marker_needed = 1;
5120 		} while (!atomic_read(&vha->loop_down_timer) &&
5121 		    (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5122 	}
5123 }
5124 
5125 /**************************************************************************
5126 *   qla2x00_timer
5127 *
5128 * Description:
5129 *   One second timer
5130 *
5131 * Context: Interrupt
5132 ***************************************************************************/
5133 void
qla2x00_timer(scsi_qla_host_t * vha)5134 qla2x00_timer(scsi_qla_host_t *vha)
5135 {
5136 	unsigned long	cpu_flags = 0;
5137 	int		start_dpc = 0;
5138 	int		index;
5139 	srb_t		*sp;
5140 	uint16_t        w;
5141 	struct qla_hw_data *ha = vha->hw;
5142 	struct req_que *req;
5143 
5144 	if (ha->flags.eeh_busy) {
5145 		ql_dbg(ql_dbg_timer, vha, 0x6000,
5146 		    "EEH = %d, restarting timer.\n",
5147 		    ha->flags.eeh_busy);
5148 		qla2x00_restart_timer(vha, WATCH_INTERVAL);
5149 		return;
5150 	}
5151 
5152 	/*
5153 	 * Hardware read to raise pending EEH errors during mailbox waits. If
5154 	 * the read returns -1 then disable the board.
5155 	 */
5156 	if (!pci_channel_offline(ha->pdev)) {
5157 		pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5158 		qla2x00_check_reg16_for_disconnect(vha, w);
5159 	}
5160 
5161 	/* Make sure qla82xx_watchdog is run only for physical port */
5162 	if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5163 		if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5164 			start_dpc++;
5165 		if (IS_QLA82XX(ha))
5166 			qla82xx_watchdog(vha);
5167 		else if (IS_QLA8044(ha))
5168 			qla8044_watchdog(vha);
5169 	}
5170 
5171 	if (!vha->vp_idx && IS_QLAFX00(ha))
5172 		qlafx00_timer_routine(vha);
5173 
5174 	/* Loop down handler. */
5175 	if (atomic_read(&vha->loop_down_timer) > 0 &&
5176 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5177 	    !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5178 		&& vha->flags.online) {
5179 
5180 		if (atomic_read(&vha->loop_down_timer) ==
5181 		    vha->loop_down_abort_time) {
5182 
5183 			ql_log(ql_log_info, vha, 0x6008,
5184 			    "Loop down - aborting the queues before time expires.\n");
5185 
5186 			if (!IS_QLA2100(ha) && vha->link_down_timeout)
5187 				atomic_set(&vha->loop_state, LOOP_DEAD);
5188 
5189 			/*
5190 			 * Schedule an ISP abort to return any FCP2-device
5191 			 * commands.
5192 			 */
5193 			/* NPIV - scan physical port only */
5194 			if (!vha->vp_idx) {
5195 				spin_lock_irqsave(&ha->hardware_lock,
5196 				    cpu_flags);
5197 				req = ha->req_q_map[0];
5198 				for (index = 1;
5199 				    index < req->num_outstanding_cmds;
5200 				    index++) {
5201 					fc_port_t *sfcp;
5202 
5203 					sp = req->outstanding_cmds[index];
5204 					if (!sp)
5205 						continue;
5206 					if (sp->type != SRB_SCSI_CMD)
5207 						continue;
5208 					sfcp = sp->fcport;
5209 					if (!(sfcp->flags & FCF_FCP2_DEVICE))
5210 						continue;
5211 
5212 					if (IS_QLA82XX(ha))
5213 						set_bit(FCOE_CTX_RESET_NEEDED,
5214 							&vha->dpc_flags);
5215 					else
5216 						set_bit(ISP_ABORT_NEEDED,
5217 							&vha->dpc_flags);
5218 					break;
5219 				}
5220 				spin_unlock_irqrestore(&ha->hardware_lock,
5221 								cpu_flags);
5222 			}
5223 			start_dpc++;
5224 		}
5225 
5226 		/* if the loop has been down for 4 minutes, reinit adapter */
5227 		if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5228 			if (!(vha->device_flags & DFLG_NO_CABLE)) {
5229 				ql_log(ql_log_warn, vha, 0x6009,
5230 				    "Loop down - aborting ISP.\n");
5231 
5232 				if (IS_QLA82XX(ha))
5233 					set_bit(FCOE_CTX_RESET_NEEDED,
5234 						&vha->dpc_flags);
5235 				else
5236 					set_bit(ISP_ABORT_NEEDED,
5237 						&vha->dpc_flags);
5238 			}
5239 		}
5240 		ql_dbg(ql_dbg_timer, vha, 0x600a,
5241 		    "Loop down - seconds remaining %d.\n",
5242 		    atomic_read(&vha->loop_down_timer));
5243 	}
5244 	/* Check if beacon LED needs to be blinked for physical host only */
5245 	if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5246 		/* There is no beacon_blink function for ISP82xx */
5247 		if (!IS_P3P_TYPE(ha)) {
5248 			set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5249 			start_dpc++;
5250 		}
5251 	}
5252 
5253 	/* Process any deferred work. */
5254 	if (!list_empty(&vha->work_list))
5255 		start_dpc++;
5256 
5257 	/* Schedule the DPC routine if needed */
5258 	if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5259 	    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5260 	    test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5261 	    start_dpc ||
5262 	    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5263 	    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5264 	    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5265 	    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5266 	    test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5267 	    test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5268 		ql_dbg(ql_dbg_timer, vha, 0x600b,
5269 		    "isp_abort_needed=%d loop_resync_needed=%d "
5270 		    "fcport_update_needed=%d start_dpc=%d "
5271 		    "reset_marker_needed=%d",
5272 		    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5273 		    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5274 		    test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5275 		    start_dpc,
5276 		    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5277 		ql_dbg(ql_dbg_timer, vha, 0x600c,
5278 		    "beacon_blink_needed=%d isp_unrecoverable=%d "
5279 		    "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5280 		    "relogin_needed=%d.\n",
5281 		    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5282 		    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5283 		    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5284 		    test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5285 		    test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5286 		qla2xxx_wake_dpc(vha);
5287 	}
5288 
5289 	qla2x00_restart_timer(vha, WATCH_INTERVAL);
5290 }
5291 
5292 /* Firmware interface routines. */
5293 
5294 #define FW_BLOBS	11
5295 #define FW_ISP21XX	0
5296 #define FW_ISP22XX	1
5297 #define FW_ISP2300	2
5298 #define FW_ISP2322	3
5299 #define FW_ISP24XX	4
5300 #define FW_ISP25XX	5
5301 #define FW_ISP81XX	6
5302 #define FW_ISP82XX	7
5303 #define FW_ISP2031	8
5304 #define FW_ISP8031	9
5305 #define FW_ISP27XX	10
5306 
5307 #define FW_FILE_ISP21XX	"ql2100_fw.bin"
5308 #define FW_FILE_ISP22XX	"ql2200_fw.bin"
5309 #define FW_FILE_ISP2300	"ql2300_fw.bin"
5310 #define FW_FILE_ISP2322	"ql2322_fw.bin"
5311 #define FW_FILE_ISP24XX	"ql2400_fw.bin"
5312 #define FW_FILE_ISP25XX	"ql2500_fw.bin"
5313 #define FW_FILE_ISP81XX	"ql8100_fw.bin"
5314 #define FW_FILE_ISP82XX	"ql8200_fw.bin"
5315 #define FW_FILE_ISP2031	"ql2600_fw.bin"
5316 #define FW_FILE_ISP8031	"ql8300_fw.bin"
5317 #define FW_FILE_ISP27XX	"ql2700_fw.bin"
5318 
5319 
5320 static DEFINE_MUTEX(qla_fw_lock);
5321 
5322 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5323 	{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5324 	{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5325 	{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5326 	{ .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5327 	{ .name = FW_FILE_ISP24XX, },
5328 	{ .name = FW_FILE_ISP25XX, },
5329 	{ .name = FW_FILE_ISP81XX, },
5330 	{ .name = FW_FILE_ISP82XX, },
5331 	{ .name = FW_FILE_ISP2031, },
5332 	{ .name = FW_FILE_ISP8031, },
5333 	{ .name = FW_FILE_ISP27XX, },
5334 };
5335 
5336 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)5337 qla2x00_request_firmware(scsi_qla_host_t *vha)
5338 {
5339 	struct qla_hw_data *ha = vha->hw;
5340 	struct fw_blob *blob;
5341 
5342 	if (IS_QLA2100(ha)) {
5343 		blob = &qla_fw_blobs[FW_ISP21XX];
5344 	} else if (IS_QLA2200(ha)) {
5345 		blob = &qla_fw_blobs[FW_ISP22XX];
5346 	} else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5347 		blob = &qla_fw_blobs[FW_ISP2300];
5348 	} else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5349 		blob = &qla_fw_blobs[FW_ISP2322];
5350 	} else if (IS_QLA24XX_TYPE(ha)) {
5351 		blob = &qla_fw_blobs[FW_ISP24XX];
5352 	} else if (IS_QLA25XX(ha)) {
5353 		blob = &qla_fw_blobs[FW_ISP25XX];
5354 	} else if (IS_QLA81XX(ha)) {
5355 		blob = &qla_fw_blobs[FW_ISP81XX];
5356 	} else if (IS_QLA82XX(ha)) {
5357 		blob = &qla_fw_blobs[FW_ISP82XX];
5358 	} else if (IS_QLA2031(ha)) {
5359 		blob = &qla_fw_blobs[FW_ISP2031];
5360 	} else if (IS_QLA8031(ha)) {
5361 		blob = &qla_fw_blobs[FW_ISP8031];
5362 	} else if (IS_QLA27XX(ha)) {
5363 		blob = &qla_fw_blobs[FW_ISP27XX];
5364 	} else {
5365 		return NULL;
5366 	}
5367 
5368 	mutex_lock(&qla_fw_lock);
5369 	if (blob->fw)
5370 		goto out;
5371 
5372 	if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5373 		ql_log(ql_log_warn, vha, 0x0063,
5374 		    "Failed to load firmware image (%s).\n", blob->name);
5375 		blob->fw = NULL;
5376 		blob = NULL;
5377 		goto out;
5378 	}
5379 
5380 out:
5381 	mutex_unlock(&qla_fw_lock);
5382 	return blob;
5383 }
5384 
5385 static void
qla2x00_release_firmware(void)5386 qla2x00_release_firmware(void)
5387 {
5388 	int idx;
5389 
5390 	mutex_lock(&qla_fw_lock);
5391 	for (idx = 0; idx < FW_BLOBS; idx++)
5392 		release_firmware(qla_fw_blobs[idx].fw);
5393 	mutex_unlock(&qla_fw_lock);
5394 }
5395 
5396 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)5397 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5398 {
5399 	scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5400 	struct qla_hw_data *ha = vha->hw;
5401 
5402 	ql_dbg(ql_dbg_aer, vha, 0x9000,
5403 	    "PCI error detected, state %x.\n", state);
5404 
5405 	switch (state) {
5406 	case pci_channel_io_normal:
5407 		ha->flags.eeh_busy = 0;
5408 		return PCI_ERS_RESULT_CAN_RECOVER;
5409 	case pci_channel_io_frozen:
5410 		ha->flags.eeh_busy = 1;
5411 		/* For ISP82XX complete any pending mailbox cmd */
5412 		if (IS_QLA82XX(ha)) {
5413 			ha->flags.isp82xx_fw_hung = 1;
5414 			ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5415 			qla82xx_clear_pending_mbx(vha);
5416 		}
5417 		qla2x00_free_irqs(vha);
5418 		pci_disable_device(pdev);
5419 		/* Return back all IOs */
5420 		qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5421 		return PCI_ERS_RESULT_NEED_RESET;
5422 	case pci_channel_io_perm_failure:
5423 		ha->flags.pci_channel_io_perm_failure = 1;
5424 		qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5425 		return PCI_ERS_RESULT_DISCONNECT;
5426 	}
5427 	return PCI_ERS_RESULT_NEED_RESET;
5428 }
5429 
5430 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)5431 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5432 {
5433 	int risc_paused = 0;
5434 	uint32_t stat;
5435 	unsigned long flags;
5436 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5437 	struct qla_hw_data *ha = base_vha->hw;
5438 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5439 	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5440 
5441 	if (IS_QLA82XX(ha))
5442 		return PCI_ERS_RESULT_RECOVERED;
5443 
5444 	spin_lock_irqsave(&ha->hardware_lock, flags);
5445 	if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5446 		stat = RD_REG_DWORD(&reg->hccr);
5447 		if (stat & HCCR_RISC_PAUSE)
5448 			risc_paused = 1;
5449 	} else if (IS_QLA23XX(ha)) {
5450 		stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5451 		if (stat & HSR_RISC_PAUSED)
5452 			risc_paused = 1;
5453 	} else if (IS_FWI2_CAPABLE(ha)) {
5454 		stat = RD_REG_DWORD(&reg24->host_status);
5455 		if (stat & HSRX_RISC_PAUSED)
5456 			risc_paused = 1;
5457 	}
5458 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
5459 
5460 	if (risc_paused) {
5461 		ql_log(ql_log_info, base_vha, 0x9003,
5462 		    "RISC paused -- mmio_enabled, Dumping firmware.\n");
5463 		ha->isp_ops->fw_dump(base_vha, 0);
5464 
5465 		return PCI_ERS_RESULT_NEED_RESET;
5466 	} else
5467 		return PCI_ERS_RESULT_RECOVERED;
5468 }
5469 
5470 static uint32_t
qla82xx_error_recovery(scsi_qla_host_t * base_vha)5471 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5472 {
5473 	uint32_t rval = QLA_FUNCTION_FAILED;
5474 	uint32_t drv_active = 0;
5475 	struct qla_hw_data *ha = base_vha->hw;
5476 	int fn;
5477 	struct pci_dev *other_pdev = NULL;
5478 
5479 	ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5480 	    "Entered %s.\n", __func__);
5481 
5482 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5483 
5484 	if (base_vha->flags.online) {
5485 		/* Abort all outstanding commands,
5486 		 * so as to be requeued later */
5487 		qla2x00_abort_isp_cleanup(base_vha);
5488 	}
5489 
5490 
5491 	fn = PCI_FUNC(ha->pdev->devfn);
5492 	while (fn > 0) {
5493 		fn--;
5494 		ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5495 		    "Finding pci device at function = 0x%x.\n", fn);
5496 		other_pdev =
5497 		    pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5498 		    ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5499 		    fn));
5500 
5501 		if (!other_pdev)
5502 			continue;
5503 		if (atomic_read(&other_pdev->enable_cnt)) {
5504 			ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5505 			    "Found PCI func available and enable at 0x%x.\n",
5506 			    fn);
5507 			pci_dev_put(other_pdev);
5508 			break;
5509 		}
5510 		pci_dev_put(other_pdev);
5511 	}
5512 
5513 	if (!fn) {
5514 		/* Reset owner */
5515 		ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5516 		    "This devfn is reset owner = 0x%x.\n",
5517 		    ha->pdev->devfn);
5518 		qla82xx_idc_lock(ha);
5519 
5520 		qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5521 		    QLA8XXX_DEV_INITIALIZING);
5522 
5523 		qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5524 		    QLA82XX_IDC_VERSION);
5525 
5526 		drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5527 		ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5528 		    "drv_active = 0x%x.\n", drv_active);
5529 
5530 		qla82xx_idc_unlock(ha);
5531 		/* Reset if device is not already reset
5532 		 * drv_active would be 0 if a reset has already been done
5533 		 */
5534 		if (drv_active)
5535 			rval = qla82xx_start_firmware(base_vha);
5536 		else
5537 			rval = QLA_SUCCESS;
5538 		qla82xx_idc_lock(ha);
5539 
5540 		if (rval != QLA_SUCCESS) {
5541 			ql_log(ql_log_info, base_vha, 0x900b,
5542 			    "HW State: FAILED.\n");
5543 			qla82xx_clear_drv_active(ha);
5544 			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5545 			    QLA8XXX_DEV_FAILED);
5546 		} else {
5547 			ql_log(ql_log_info, base_vha, 0x900c,
5548 			    "HW State: READY.\n");
5549 			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5550 			    QLA8XXX_DEV_READY);
5551 			qla82xx_idc_unlock(ha);
5552 			ha->flags.isp82xx_fw_hung = 0;
5553 			rval = qla82xx_restart_isp(base_vha);
5554 			qla82xx_idc_lock(ha);
5555 			/* Clear driver state register */
5556 			qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5557 			qla82xx_set_drv_active(base_vha);
5558 		}
5559 		qla82xx_idc_unlock(ha);
5560 	} else {
5561 		ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5562 		    "This devfn is not reset owner = 0x%x.\n",
5563 		    ha->pdev->devfn);
5564 		if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5565 		    QLA8XXX_DEV_READY)) {
5566 			ha->flags.isp82xx_fw_hung = 0;
5567 			rval = qla82xx_restart_isp(base_vha);
5568 			qla82xx_idc_lock(ha);
5569 			qla82xx_set_drv_active(base_vha);
5570 			qla82xx_idc_unlock(ha);
5571 		}
5572 	}
5573 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5574 
5575 	return rval;
5576 }
5577 
5578 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)5579 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5580 {
5581 	pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5582 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5583 	struct qla_hw_data *ha = base_vha->hw;
5584 	struct rsp_que *rsp;
5585 	int rc, retries = 10;
5586 
5587 	ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5588 	    "Slot Reset.\n");
5589 
5590 	/* Workaround: qla2xxx driver which access hardware earlier
5591 	 * needs error state to be pci_channel_io_online.
5592 	 * Otherwise mailbox command timesout.
5593 	 */
5594 	pdev->error_state = pci_channel_io_normal;
5595 
5596 	pci_restore_state(pdev);
5597 
5598 	/* pci_restore_state() clears the saved_state flag of the device
5599 	 * save restored state which resets saved_state flag
5600 	 */
5601 	pci_save_state(pdev);
5602 
5603 	if (ha->mem_only)
5604 		rc = pci_enable_device_mem(pdev);
5605 	else
5606 		rc = pci_enable_device(pdev);
5607 
5608 	if (rc) {
5609 		ql_log(ql_log_warn, base_vha, 0x9005,
5610 		    "Can't re-enable PCI device after reset.\n");
5611 		goto exit_slot_reset;
5612 	}
5613 
5614 	rsp = ha->rsp_q_map[0];
5615 	if (qla2x00_request_irqs(ha, rsp))
5616 		goto exit_slot_reset;
5617 
5618 	if (ha->isp_ops->pci_config(base_vha))
5619 		goto exit_slot_reset;
5620 
5621 	if (IS_QLA82XX(ha)) {
5622 		if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5623 			ret = PCI_ERS_RESULT_RECOVERED;
5624 			goto exit_slot_reset;
5625 		} else
5626 			goto exit_slot_reset;
5627 	}
5628 
5629 	while (ha->flags.mbox_busy && retries--)
5630 		msleep(1000);
5631 
5632 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5633 	if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5634 		ret =  PCI_ERS_RESULT_RECOVERED;
5635 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5636 
5637 
5638 exit_slot_reset:
5639 	ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5640 	    "slot_reset return %x.\n", ret);
5641 
5642 	return ret;
5643 }
5644 
5645 static void
qla2xxx_pci_resume(struct pci_dev * pdev)5646 qla2xxx_pci_resume(struct pci_dev *pdev)
5647 {
5648 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5649 	struct qla_hw_data *ha = base_vha->hw;
5650 	int ret;
5651 
5652 	ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5653 	    "pci_resume.\n");
5654 
5655 	ret = qla2x00_wait_for_hba_online(base_vha);
5656 	if (ret != QLA_SUCCESS) {
5657 		ql_log(ql_log_fatal, base_vha, 0x9002,
5658 		    "The device failed to resume I/O from slot/link_reset.\n");
5659 	}
5660 
5661 	pci_cleanup_aer_uncorrect_error_status(pdev);
5662 
5663 	ha->flags.eeh_busy = 0;
5664 }
5665 
5666 static void
qla83xx_disable_laser(scsi_qla_host_t * vha)5667 qla83xx_disable_laser(scsi_qla_host_t *vha)
5668 {
5669 	uint32_t reg, data, fn;
5670 	struct qla_hw_data *ha = vha->hw;
5671 	struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5672 
5673 	/* pci func #/port # */
5674 	ql_dbg(ql_dbg_init, vha, 0x004b,
5675 	    "Disabling Laser for hba: %p\n", vha);
5676 
5677 	fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5678 		(BIT_15|BIT_14|BIT_13|BIT_12));
5679 
5680 	fn = (fn >> 12);
5681 
5682 	if (fn & 1)
5683 		reg = PORT_1_2031;
5684 	else
5685 		reg = PORT_0_2031;
5686 
5687 	data = LASER_OFF_2031;
5688 
5689 	qla83xx_wr_reg(vha, reg, data);
5690 }
5691 
5692 static const struct pci_error_handlers qla2xxx_err_handler = {
5693 	.error_detected = qla2xxx_pci_error_detected,
5694 	.mmio_enabled = qla2xxx_pci_mmio_enabled,
5695 	.slot_reset = qla2xxx_pci_slot_reset,
5696 	.resume = qla2xxx_pci_resume,
5697 };
5698 
5699 static struct pci_device_id qla2xxx_pci_tbl[] = {
5700 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5701 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5702 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5703 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5704 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5705 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5706 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5707 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5708 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5709 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5710 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5711 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5712 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5713 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5714 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5715 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5716 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5717 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5718 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5719 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5720 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5721 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5722 	{ 0 },
5723 };
5724 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5725 
5726 static struct pci_driver qla2xxx_pci_driver = {
5727 	.name		= QLA2XXX_DRIVER_NAME,
5728 	.driver		= {
5729 		.owner		= THIS_MODULE,
5730 	},
5731 	.id_table	= qla2xxx_pci_tbl,
5732 	.probe		= qla2x00_probe_one,
5733 	.remove		= qla2x00_remove_one,
5734 	.shutdown	= qla2x00_shutdown,
5735 	.err_handler	= &qla2xxx_err_handler,
5736 };
5737 
5738 static const struct file_operations apidev_fops = {
5739 	.owner = THIS_MODULE,
5740 	.llseek = noop_llseek,
5741 };
5742 
5743 /**
5744  * qla2x00_module_init - Module initialization.
5745  **/
5746 static int __init
qla2x00_module_init(void)5747 qla2x00_module_init(void)
5748 {
5749 	int ret = 0;
5750 
5751 	/* Allocate cache for SRBs. */
5752 	srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5753 	    SLAB_HWCACHE_ALIGN, NULL);
5754 	if (srb_cachep == NULL) {
5755 		ql_log(ql_log_fatal, NULL, 0x0001,
5756 		    "Unable to allocate SRB cache...Failing load!.\n");
5757 		return -ENOMEM;
5758 	}
5759 
5760 	/* Initialize target kmem_cache and mem_pools */
5761 	ret = qlt_init();
5762 	if (ret < 0) {
5763 		kmem_cache_destroy(srb_cachep);
5764 		return ret;
5765 	} else if (ret > 0) {
5766 		/*
5767 		 * If initiator mode is explictly disabled by qlt_init(),
5768 		 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5769 		 * performing scsi_scan_target() during LOOP UP event.
5770 		 */
5771 		qla2xxx_transport_functions.disable_target_scan = 1;
5772 		qla2xxx_transport_vport_functions.disable_target_scan = 1;
5773 	}
5774 
5775 	/* Derive version string. */
5776 	strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5777 	if (ql2xextended_error_logging)
5778 		strcat(qla2x00_version_str, "-debug");
5779 
5780 	qla2xxx_transport_template =
5781 	    fc_attach_transport(&qla2xxx_transport_functions);
5782 	if (!qla2xxx_transport_template) {
5783 		kmem_cache_destroy(srb_cachep);
5784 		ql_log(ql_log_fatal, NULL, 0x0002,
5785 		    "fc_attach_transport failed...Failing load!.\n");
5786 		qlt_exit();
5787 		return -ENODEV;
5788 	}
5789 
5790 	apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5791 	if (apidev_major < 0) {
5792 		ql_log(ql_log_fatal, NULL, 0x0003,
5793 		    "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5794 	}
5795 
5796 	qla2xxx_transport_vport_template =
5797 	    fc_attach_transport(&qla2xxx_transport_vport_functions);
5798 	if (!qla2xxx_transport_vport_template) {
5799 		kmem_cache_destroy(srb_cachep);
5800 		qlt_exit();
5801 		fc_release_transport(qla2xxx_transport_template);
5802 		ql_log(ql_log_fatal, NULL, 0x0004,
5803 		    "fc_attach_transport vport failed...Failing load!.\n");
5804 		return -ENODEV;
5805 	}
5806 	ql_log(ql_log_info, NULL, 0x0005,
5807 	    "QLogic Fibre Channel HBA Driver: %s.\n",
5808 	    qla2x00_version_str);
5809 	ret = pci_register_driver(&qla2xxx_pci_driver);
5810 	if (ret) {
5811 		kmem_cache_destroy(srb_cachep);
5812 		qlt_exit();
5813 		fc_release_transport(qla2xxx_transport_template);
5814 		fc_release_transport(qla2xxx_transport_vport_template);
5815 		ql_log(ql_log_fatal, NULL, 0x0006,
5816 		    "pci_register_driver failed...ret=%d Failing load!.\n",
5817 		    ret);
5818 	}
5819 	return ret;
5820 }
5821 
5822 /**
5823  * qla2x00_module_exit - Module cleanup.
5824  **/
5825 static void __exit
qla2x00_module_exit(void)5826 qla2x00_module_exit(void)
5827 {
5828 	unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5829 	pci_unregister_driver(&qla2xxx_pci_driver);
5830 	qla2x00_release_firmware();
5831 	kmem_cache_destroy(srb_cachep);
5832 	qlt_exit();
5833 	if (ctx_cachep)
5834 		kmem_cache_destroy(ctx_cachep);
5835 	fc_release_transport(qla2xxx_transport_template);
5836 	fc_release_transport(qla2xxx_transport_vport_template);
5837 }
5838 
5839 module_init(qla2x00_module_init);
5840 module_exit(qla2x00_module_exit);
5841 
5842 MODULE_AUTHOR("QLogic Corporation");
5843 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5844 MODULE_LICENSE("GPL");
5845 MODULE_VERSION(QLA2XXX_VERSION);
5846 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5847 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5848 MODULE_FIRMWARE(FW_FILE_ISP2300);
5849 MODULE_FIRMWARE(FW_FILE_ISP2322);
5850 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5851 MODULE_FIRMWARE(FW_FILE_ISP25XX);
5852 MODULE_FIRMWARE(FW_FILE_ISP2031);
5853 MODULE_FIRMWARE(FW_FILE_ISP8031);
5854 MODULE_FIRMWARE(FW_FILE_ISP27XX);
5855