1 /*
2 * arch/arm/mach-pxa/time.c
3 *
4 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
6 *
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/clk.h>
19 #include <linux/clockchips.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/sched_clock.h>
23
24 #include <asm/div64.h>
25
26 #define OSMR0 0x00 /* OS Timer 0 Match Register */
27 #define OSMR1 0x04 /* OS Timer 1 Match Register */
28 #define OSMR2 0x08 /* OS Timer 2 Match Register */
29 #define OSMR3 0x0C /* OS Timer 3 Match Register */
30
31 #define OSCR 0x10 /* OS Timer Counter Register */
32 #define OSSR 0x14 /* OS Timer Status Register */
33 #define OWER 0x18 /* OS Timer Watchdog Enable Register */
34 #define OIER 0x1C /* OS Timer Interrupt Enable Register */
35
36 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
37 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
38 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
39 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
40
41 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
42
43 /*
44 * This is PXA's sched_clock implementation. This has a resolution
45 * of at least 308 ns and a maximum value of 208 days.
46 *
47 * The return value is guaranteed to be monotonic in that range as
48 * long as there is always less than 582 seconds between successive
49 * calls to sched_clock() which should always be the case in practice.
50 */
51
52 #define timer_readl(reg) readl_relaxed(timer_base + (reg))
53 #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
54
55 static void __iomem *timer_base;
56
pxa_read_sched_clock(void)57 static u64 notrace pxa_read_sched_clock(void)
58 {
59 return timer_readl(OSCR);
60 }
61
62
63 #define MIN_OSCR_DELTA 16
64
65 static irqreturn_t
pxa_ost0_interrupt(int irq,void * dev_id)66 pxa_ost0_interrupt(int irq, void *dev_id)
67 {
68 struct clock_event_device *c = dev_id;
69
70 /* Disarm the compare/match, signal the event. */
71 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
72 timer_writel(OSSR_M0, OSSR);
73 c->event_handler(c);
74
75 return IRQ_HANDLED;
76 }
77
78 static int
pxa_osmr0_set_next_event(unsigned long delta,struct clock_event_device * dev)79 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
80 {
81 unsigned long next, oscr;
82
83 timer_writel(timer_readl(OIER) | OIER_E0, OIER);
84 next = timer_readl(OSCR) + delta;
85 timer_writel(next, OSMR0);
86 oscr = timer_readl(OSCR);
87
88 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
89 }
90
91 static void
pxa_osmr0_set_mode(enum clock_event_mode mode,struct clock_event_device * dev)92 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
93 {
94 switch (mode) {
95 case CLOCK_EVT_MODE_ONESHOT:
96 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
97 timer_writel(OSSR_M0, OSSR);
98 break;
99
100 case CLOCK_EVT_MODE_UNUSED:
101 case CLOCK_EVT_MODE_SHUTDOWN:
102 /* initializing, released, or preparing for suspend */
103 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
104 timer_writel(OSSR_M0, OSSR);
105 break;
106
107 case CLOCK_EVT_MODE_RESUME:
108 case CLOCK_EVT_MODE_PERIODIC:
109 break;
110 }
111 }
112
113 #ifdef CONFIG_PM
114 static unsigned long osmr[4], oier, oscr;
115
pxa_timer_suspend(struct clock_event_device * cedev)116 static void pxa_timer_suspend(struct clock_event_device *cedev)
117 {
118 osmr[0] = timer_readl(OSMR0);
119 osmr[1] = timer_readl(OSMR1);
120 osmr[2] = timer_readl(OSMR2);
121 osmr[3] = timer_readl(OSMR3);
122 oier = timer_readl(OIER);
123 oscr = timer_readl(OSCR);
124 }
125
pxa_timer_resume(struct clock_event_device * cedev)126 static void pxa_timer_resume(struct clock_event_device *cedev)
127 {
128 /*
129 * Ensure that we have at least MIN_OSCR_DELTA between match
130 * register 0 and the OSCR, to guarantee that we will receive
131 * the one-shot timer interrupt. We adjust OSMR0 in preference
132 * to OSCR to guarantee that OSCR is monotonically incrementing.
133 */
134 if (osmr[0] - oscr < MIN_OSCR_DELTA)
135 osmr[0] += MIN_OSCR_DELTA;
136
137 timer_writel(osmr[0], OSMR0);
138 timer_writel(osmr[1], OSMR1);
139 timer_writel(osmr[2], OSMR2);
140 timer_writel(osmr[3], OSMR3);
141 timer_writel(oier, OIER);
142 timer_writel(oscr, OSCR);
143 }
144 #else
145 #define pxa_timer_suspend NULL
146 #define pxa_timer_resume NULL
147 #endif
148
149 static struct clock_event_device ckevt_pxa_osmr0 = {
150 .name = "osmr0",
151 .features = CLOCK_EVT_FEAT_ONESHOT,
152 .rating = 200,
153 .set_next_event = pxa_osmr0_set_next_event,
154 .set_mode = pxa_osmr0_set_mode,
155 .suspend = pxa_timer_suspend,
156 .resume = pxa_timer_resume,
157 };
158
159 static struct irqaction pxa_ost0_irq = {
160 .name = "ost0",
161 .flags = IRQF_TIMER | IRQF_IRQPOLL,
162 .handler = pxa_ost0_interrupt,
163 .dev_id = &ckevt_pxa_osmr0,
164 };
165
pxa_timer_common_init(int irq,unsigned long clock_tick_rate)166 static void __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
167 {
168 timer_writel(0, OIER);
169 timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
170
171 sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
172
173 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
174
175 setup_irq(irq, &pxa_ost0_irq);
176
177 clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
178 32, clocksource_mmio_readl_up);
179 clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
180 MIN_OSCR_DELTA * 2, 0x7fffffff);
181 }
182
pxa_timer_dt_init(struct device_node * np)183 static void __init pxa_timer_dt_init(struct device_node *np)
184 {
185 struct clk *clk;
186 int irq;
187
188 /* timer registers are shared with watchdog timer */
189 timer_base = of_iomap(np, 0);
190 if (!timer_base)
191 panic("%s: unable to map resource\n", np->name);
192
193 clk = of_clk_get(np, 0);
194 if (IS_ERR(clk)) {
195 pr_crit("%s: unable to get clk\n", np->name);
196 return;
197 }
198 clk_prepare_enable(clk);
199
200 /* we are only interested in OS-timer0 irq */
201 irq = irq_of_parse_and_map(np, 0);
202 if (irq <= 0) {
203 pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
204 return;
205 }
206
207 pxa_timer_common_init(irq, clk_get_rate(clk));
208 }
209 CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
210
211 /*
212 * Legacy timer init for non device-tree boards.
213 */
pxa_timer_nodt_init(int irq,void __iomem * base,unsigned long clock_tick_rate)214 void __init pxa_timer_nodt_init(int irq, void __iomem *base,
215 unsigned long clock_tick_rate)
216 {
217 struct clk *clk;
218
219 timer_base = base;
220 clk = clk_get(NULL, "OSTIMER0");
221 if (clk && !IS_ERR(clk))
222 clk_prepare_enable(clk);
223 else
224 pr_crit("%s: unable to get clk\n", __func__);
225
226 pxa_timer_common_init(irq, clock_tick_rate);
227 }
228