1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17 #ifndef __HALDMOUTSRC_H__ 18 #define __HALDMOUTSRC_H__ 19 20 /* */ 21 /* Definition */ 22 /* */ 23 /* */ 24 /* 2011/09/22 MH Define all team supprt ability. */ 25 /* */ 26 27 /* */ 28 /* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ 29 /* */ 30 /* define DM_ODM_SUPPORT_AP 0 */ 31 /* define DM_ODM_SUPPORT_ADSL 0 */ 32 /* define DM_ODM_SUPPORT_CE 0 */ 33 /* define DM_ODM_SUPPORT_MP 1 */ 34 35 #define TP_MODE 0 36 #define RSSI_MODE 1 37 #define TRAFFIC_LOW 0 38 #define TRAFFIC_HIGH 1 39 40 41 /* */ 42 /* 3 Tx Power Tracking */ 43 /* 3============================================================ */ 44 #define DPK_DELTA_MAPPING_NUM 13 45 #define index_mapping_HP_NUM 15 46 47 48 /* */ 49 /* 3 PSD Handler */ 50 /* 3============================================================ */ 51 52 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 53 #define MODE_40M 0 /* 0:20M, 1:40M */ 54 #define PSD_TH2 3 55 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 56 #define SIR_STEP_SIZE 3 57 #define Smooth_Size_1 5 58 #define Smooth_TH_1 3 59 #define Smooth_Size_2 10 60 #define Smooth_TH_2 4 61 #define Smooth_Size_3 20 62 #define Smooth_TH_3 4 63 #define Smooth_Step_Size 5 64 #define Adaptive_SIR 1 65 #define PSD_RESCAN 4 66 #define PSD_SCAN_INTERVAL 700 /* ms */ 67 68 /* 8723A High Power IGI Setting */ 69 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 70 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 71 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 72 73 /* LPS define */ 74 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 75 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 76 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 77 #define RSSI_OFFSET_DIG 0x05; 78 79 /* ANT Test */ 80 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 81 #define ANTTESTA 0x01 /* Ant A will be Testing */ 82 #define ANTTESTB 0x02 /* Ant B will be testing */ 83 84 85 /* */ 86 /* structure and define */ 87 /* */ 88 89 struct dig_t { 90 u8 Dig_Enable_Flag; 91 u8 Dig_Ext_Port_Stage; 92 93 int RssiLowThresh; 94 int RssiHighThresh; 95 96 u32 FALowThresh; 97 u32 FAHighThresh; 98 99 u8 CurSTAConnectState; 100 u8 PreSTAConnectState; 101 u8 CurMultiSTAConnectState; 102 103 u8 PreIGValue; 104 u8 CurIGValue; 105 u8 BackupIGValue; 106 107 s8 BackoffVal; 108 s8 BackoffVal_range_max; 109 s8 BackoffVal_range_min; 110 u8 rx_gain_range_max; 111 u8 rx_gain_range_min; 112 u8 Rssi_val_min; 113 114 u8 PreCCK_CCAThres; 115 u8 CurCCK_CCAThres; 116 u8 PreCCKPDState; 117 u8 CurCCKPDState; 118 119 u8 LargeFAHit; 120 u8 ForbiddenIGI; 121 u32 Recover_cnt; 122 123 u8 DIG_Dynamic_MIN_0; 124 u8 DIG_Dynamic_MIN_1; 125 bool bMediaConnect_0; 126 bool bMediaConnect_1; 127 128 u32 RSSI_max; 129 }; 130 131 struct dynamic_pwr_sav { 132 u8 PreCCAState; 133 u8 CurCCAState; 134 135 u8 PreRFState; 136 u8 CurRFState; 137 138 int Rssi_val_min; 139 140 u8 initialize; 141 u32 Reg874, RegC70, Reg85C, RegA74; 142 }; 143 144 struct false_alarm_stats { 145 u32 Cnt_Parity_Fail; 146 u32 Cnt_Rate_Illegal; 147 u32 Cnt_Crc8_fail; 148 u32 Cnt_Mcs_fail; 149 u32 Cnt_Ofdm_fail; 150 u32 Cnt_Cck_fail; 151 u32 Cnt_all; 152 u32 Cnt_Fast_Fsync; 153 u32 Cnt_SB_Search_fail; 154 u32 Cnt_OFDM_CCA; 155 u32 Cnt_CCK_CCA; 156 u32 Cnt_CCA_all; 157 u32 Cnt_BW_USC; /* Gary */ 158 u32 Cnt_BW_LSC; /* Gary */ 159 }; 160 161 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 162 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 163 164 /* This indicates two different the steps. */ 165 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 166 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 167 /* with original RSSI to determine if it is necessary to switch antenna. */ 168 #define SWAW_STEP_PEAK 0 169 #define SWAW_STEP_DETERMINE 1 170 171 #define TP_MODE 0 172 #define RSSI_MODE 1 173 #define TRAFFIC_LOW 0 174 #define TRAFFIC_HIGH 1 175 176 struct sw_ant_sw { 177 u8 try_flag; 178 s32 PreRSSI; 179 u8 CurAntenna; 180 u8 PreAntenna; 181 u8 RSSI_Trying; 182 u8 TestMode; 183 u8 bTriggerAntennaSwitch; 184 u8 SelectAntennaMap; 185 u8 RSSI_target; 186 187 /* Before link Antenna Switch check */ 188 u8 SWAS_NoLink_State; 189 u32 SWAS_NoLink_BK_Reg860; 190 bool ANTA_ON; /* To indicate Ant A is or not */ 191 bool ANTB_ON; /* To indicate Ant B is on or not */ 192 193 s32 RSSI_sum_A; 194 s32 RSSI_sum_B; 195 s32 RSSI_cnt_A; 196 s32 RSSI_cnt_B; 197 198 u64 lastTxOkCnt; 199 u64 lastRxOkCnt; 200 u64 TXByteCnt_A; 201 u64 TXByteCnt_B; 202 u64 RXByteCnt_A; 203 u64 RXByteCnt_B; 204 u8 TrafficLoad; 205 }; 206 207 struct edca_turbo { 208 bool bCurrentTurboEDCA; 209 u32 prv_traffic_idx; /* edca turbo */ 210 }; 211 212 struct odm_rate_adapt { 213 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 214 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 215 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 216 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 217 u32 LastRATR; /* RATR Register Content */ 218 }; 219 220 #define IQK_MAC_REG_NUM 4 221 #define IQK_ADDA_REG_NUM 16 222 #define IQK_BB_REG_NUM_MAX 10 223 #define IQK_BB_REG_NUM 9 224 #define HP_THERMAL_NUM 8 225 226 #define AVG_THERMAL_NUM 8 227 #define IQK_Matrix_REG_NUM 8 228 #define IQK_Matrix_Settings_NUM 1+24+21 229 230 #define DM_Type_ByFW 0 231 #define DM_Type_ByDriver 1 232 233 /* Declare for common info */ 234 235 struct odm_phy_dbg_info { 236 /* ODM Write,debug info */ 237 s8 RxSNRdB[RF_PATH_MAX]; 238 u64 NumQryPhyStatus; 239 u64 NumQryPhyStatusCCK; 240 u64 NumQryPhyStatusOFDM; 241 /* Others */ 242 s32 RxEVM[RF_PATH_MAX]; 243 244 }; 245 246 struct odm_packet_info { 247 u8 Rate; 248 u8 StationID; 249 bool bPacketMatchBSSID; 250 bool bPacketToSelf; 251 bool bPacketBeacon; 252 }; 253 254 255 enum { 256 /* BB Team */ 257 ODM_DIG = 0x00000001, 258 ODM_HIGH_POWER = 0x00000002, 259 ODM_CCK_CCA_TH = 0x00000004, 260 ODM_FA_STATISTICS = 0x00000008, 261 ODM_RAMASK = 0x00000010, 262 ODM_RSSI_MONITOR = 0x00000020, 263 ODM_SW_ANTDIV = 0x00000040, 264 ODM_HW_ANTDIV = 0x00000080, 265 ODM_BB_PWRSV = 0x00000100, 266 ODM_2TPATHDIV = 0x00000200, 267 ODM_1TPATHDIV = 0x00000400, 268 ODM_PSD2AFH = 0x00000800 269 }; 270 271 /* */ 272 /* 2011/10/20 MH Define Common info enum for all team. */ 273 /* */ 274 275 enum odm_cmninfo { 276 /* Fixed value: */ 277 /* */ 278 279 ODM_CMNINFO_MP_TEST_CHIP = 2, 280 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ 281 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ 282 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ 283 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ 284 ODM_CMNINFO_EXT_LNA, /* true */ 285 ODM_CMNINFO_EXT_PA, 286 ODM_CMNINFO_EXT_TRSW, 287 ODM_CMNINFO_BINHCT_TEST, 288 ODM_CMNINFO_BWIFI_TEST, 289 ODM_CMNINFO_SMART_CONCURRENT, 290 291 292 /* */ 293 /* Dynamic value: */ 294 /* */ 295 ODM_CMNINFO_MP_MODE, 296 297 ODM_CMNINFO_WIFI_DIRECT, 298 ODM_CMNINFO_WIFI_DISPLAY, 299 ODM_CMNINFO_LINK, 300 ODM_CMNINFO_RSSI_MIN, 301 ODM_CMNINFO_DBG_COMP, /* u64 */ 302 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 303 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 304 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 305 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 306 ODM_CMNINFO_BT_DISABLED, 307 ODM_CMNINFO_BT_OPERATION, 308 ODM_CMNINFO_BT_DIG, 309 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 310 ODM_CMNINFO_BT_DISABLE_EDCA, 311 312 /* */ 313 /* Dynamic ptr array hook itms. */ 314 /* */ 315 ODM_CMNINFO_STA_STATUS, 316 ODM_CMNINFO_PHY_STATUS, 317 ODM_CMNINFO_MAC_STATUS, 318 319 ODM_CMNINFO_MAX, 320 }; 321 322 /* Define ODM support ability. ODM_CMNINFO_ABILITY */ 323 enum { 324 /* BB ODM section BIT 0-15 */ 325 ODM_BB_ANT_DIV = BIT(6), 326 }; 327 328 /* ODM_CMNINFO_INTERFACE */ 329 enum odm_interface_def { 330 ODM_ITRF_PCIE = 0x1, 331 ODM_ITRF_USB = 0x2, 332 ODM_ITRF_SDIO = 0x4, 333 ODM_ITRF_ALL = 0x7, 334 }; 335 336 /* ODM_CMNINFO_IC_TYPE */ 337 enum odm_ic_type_def { 338 ODM_RTL8192S = BIT(0), 339 ODM_RTL8192C = BIT(1), 340 ODM_RTL8192D = BIT(2), 341 ODM_RTL8723A = BIT(3), 342 ODM_RTL8188E = BIT(4), 343 ODM_RTL8812 = BIT(5), 344 ODM_RTL8821 = BIT(6), 345 }; 346 347 /* ODM_CMNINFO_CUT_VER */ 348 enum odm_cut_version { 349 ODM_CUT_A = 1, 350 ODM_CUT_B = 2, 351 ODM_CUT_C = 3, 352 ODM_CUT_D = 4, 353 ODM_CUT_E = 5, 354 ODM_CUT_F = 6, 355 ODM_CUT_TEST = 7, 356 }; 357 358 /* ODM_CMNINFO_FAB_VER */ 359 enum odm_fab_version { 360 ODM_TSMC = 0, 361 ODM_UMC = 1, 362 }; 363 364 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 365 enum rf_path_def { 366 ODM_RF_TX_A = BIT(0), 367 ODM_RF_TX_B = BIT(1), 368 ODM_RF_TX_C = BIT(2), 369 ODM_RF_TX_D = BIT(3), 370 ODM_RF_RX_A = BIT(4), 371 ODM_RF_RX_B = BIT(5), 372 ODM_RF_RX_C = BIT(6), 373 ODM_RF_RX_D = BIT(7), 374 }; 375 376 /* ODM Dynamic common info value definition */ 377 378 enum odm_mac_phy_mode { 379 ODM_SMSP = 0, 380 ODM_DMSP = 1, 381 ODM_DMDP = 2, 382 }; 383 384 385 enum odm_bt_coexist { 386 ODM_BT_BUSY = 1, 387 ODM_BT_ON = 2, 388 ODM_BT_OFF = 3, 389 ODM_BT_NONE = 4, 390 }; 391 392 /* ODM_CMNINFO_OP_MODE */ 393 enum odm_operation_mode { 394 ODM_NO_LINK = BIT(0), 395 ODM_LINK = BIT(1), 396 ODM_SCAN = BIT(2), 397 ODM_POWERSAVE = BIT(3), 398 ODM_AP_MODE = BIT(4), 399 ODM_CLIENT_MODE = BIT(5), 400 ODM_AD_HOC = BIT(6), 401 ODM_WIFI_DIRECT = BIT(7), 402 ODM_WIFI_DISPLAY = BIT(8), 403 }; 404 405 /* ODM_CMNINFO_WM_MODE */ 406 enum odm_wireless_mode { 407 ODM_WM_UNKNOW = 0x0, 408 ODM_WM_B = BIT(0), 409 ODM_WM_G = BIT(1), 410 ODM_WM_A = BIT(2), 411 ODM_WM_N24G = BIT(3), 412 ODM_WM_N5G = BIT(4), 413 ODM_WM_AUTO = BIT(5), 414 ODM_WM_AC = BIT(6), 415 }; 416 417 /* ODM_CMNINFO_BAND */ 418 enum odm_band_type { 419 ODM_BAND_2_4G = BIT(0), 420 ODM_BAND_5G = BIT(1), 421 422 }; 423 424 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 425 enum odm_sec_chnl_offset { 426 ODM_DONT_CARE = 0, 427 ODM_BELOW = 1, 428 ODM_ABOVE = 2 429 }; 430 431 /* ODM_CMNINFO_CHNL */ 432 433 /* ODM_CMNINFO_BOARD_TYPE */ 434 enum odm_board_type { 435 ODM_BOARD_NORMAL = 0, 436 ODM_BOARD_HIGHPWR = 1, 437 ODM_BOARD_MINICARD = 2, 438 ODM_BOARD_SLIM = 3, 439 ODM_BOARD_COMBO = 4, 440 441 }; 442 443 /* ODM_CMNINFO_ONE_PATH_CCA */ 444 enum odm_cca_path { 445 ODM_CCA_2R = 0, 446 ODM_CCA_1R_A = 1, 447 ODM_CCA_1R_B = 2, 448 }; 449 450 struct iqk_matrix_regs_set { 451 bool bIQKDone; 452 s32 Value[1][IQK_Matrix_REG_NUM]; 453 }; 454 455 struct odm_rf_cal_t { 456 /* for tx power tracking */ 457 458 u32 RegA24; /* for TempCCK */ 459 s32 RegE94; 460 s32 RegE9C; 461 s32 RegEB4; 462 s32 RegEBC; 463 464 /* u8 bTXPowerTracking; */ 465 u8 TXPowercount; 466 bool bTXPowerTrackingInit; 467 bool bTXPowerTracking; 468 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 469 u8 TM_Trigger; 470 u8 InternalPA5G[2]; /* pathA / pathB */ 471 472 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 473 u8 ThermalValue; 474 u8 ThermalValue_LCK; 475 u8 ThermalValue_IQK; 476 u8 ThermalValue_DPK; 477 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 478 u8 ThermalValue_AVG_index; 479 u8 ThermalValue_RxGain; 480 u8 ThermalValue_Crystal; 481 u8 ThermalValue_DPKstore; 482 u8 ThermalValue_DPKtrack; 483 bool TxPowerTrackingInProgress; 484 bool bDPKenable; 485 486 bool bReloadtxpowerindex; 487 u8 bRfPiEnable; 488 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 489 490 u8 bCCKinCH14; 491 u8 CCK_index; 492 u8 OFDM_index[2]; 493 bool bDoneTxpower; 494 495 u8 ThermalValue_HP[HP_THERMAL_NUM]; 496 u8 ThermalValue_HP_index; 497 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 498 499 u8 Delta_IQK; 500 u8 Delta_LCK; 501 502 /* for IQK */ 503 u32 RegC04; 504 u32 Reg874; 505 u32 RegC08; 506 u32 RegB68; 507 u32 RegB6C; 508 u32 Reg870; 509 u32 Reg860; 510 u32 Reg864; 511 512 bool bIQKInitialized; 513 bool bLCKInProgress; 514 bool bAntennaDetected; 515 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 516 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 517 u32 IQK_BB_backup_recover[9]; 518 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 519 520 /* for APK */ 521 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 522 u8 bAPKdone; 523 u8 bAPKThermalMeterIgnore; 524 u8 bDPdone; 525 u8 bDPPathAOK; 526 u8 bDPPathBOK; 527 }; 528 529 enum ant_dif_type { 530 NO_ANTDIV = 0xFF, 531 CG_TRX_HW_ANTDIV = 0x01, 532 CGCS_RX_HW_ANTDIV = 0x02, 533 FIXED_HW_ANTDIV = 0x03, 534 CG_TRX_SMART_ANTDIV = 0x04, 535 CGCS_RX_SW_ANTDIV = 0x05, 536 }; 537 538 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 539 struct dm_odm_t { 540 /* */ 541 /* Add for different team use temporarily */ 542 /* */ 543 struct rtw_adapter *Adapter; /* For CE/NIC team */ 544 545 u64 DebugComponents; 546 u32 DebugLevel; 547 548 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 549 bool bCckHighPower; 550 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 551 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 552 553 /* 1 COMMON INFORMATION */ 554 555 /* Init Value */ 556 /* HOOK BEFORE REG INIT----------- */ 557 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 558 u32 SupportAbility; 559 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 560 u32 SupportICType; 561 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 562 u8 CutVersion; 563 /* Fab Version TSMC/UMC = 0/1 */ 564 u8 FabVersion; 565 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 566 u8 BoardType; 567 /* with external LNA NO/Yes = 0/1 */ 568 u8 ExtLNA; 569 /* with external PA NO/Yes = 0/1 */ 570 u8 ExtPA; 571 /* with external TRSW NO/Yes = 0/1 */ 572 u8 ExtTRSW; 573 bool bInHctTest; 574 bool bWIFITest; 575 576 bool bDualMacSmartConcurrent; 577 u32 BK_SupportAbility; 578 /* HOOK BEFORE REG INIT----------- */ 579 580 /* */ 581 /* Dynamic Value */ 582 /* */ 583 /* POINTER REFERENCE----------- */ 584 585 u8 u8_temp; 586 bool bool_temp; 587 struct rtw_adapter *PADAPTER_temp; 588 589 /* POINTER REFERENCE----------- */ 590 /* */ 591 /* CALL BY VALUE------------- */ 592 bool bWIFI_Direct; 593 bool bWIFI_Display; 594 bool bLinked; 595 u8 RSSI_Min; 596 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 597 bool bIsMPChip; 598 bool bOneEntryOnly; 599 /* Common info for BTDM */ 600 bool bBtDisabled; /* BT is disabled */ 601 bool bBtHsOperation; /* BT HS mode is under progress */ 602 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 603 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 604 bool bBtBusy; /* BT is busy. */ 605 /* CALL BY VALUE------------- */ 606 607 /* 2 Define STA info. */ 608 /* _ODM_STA_INFO */ 609 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 610 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 611 612 /* Latest packet phy info (ODM write) */ 613 struct odm_phy_dbg_info PhyDbgInfo; 614 /* PHY_INFO_88E PhyInfo; */ 615 616 /* Latest packet phy info (ODM write) */ 617 /* MAC_INFO_88E MacInfo; */ 618 619 /* Different Team independt structure?? */ 620 621 /* */ 622 /* TX_RTP_CMN TX_retrpo; */ 623 /* TX_RTP_88E TX_retrpo; */ 624 /* TX_RTP_8195 TX_retrpo; */ 625 626 /* */ 627 /* ODM Structure */ 628 /* */ 629 struct dig_t DM_DigTable; 630 struct dynamic_pwr_sav DM_PSTable; 631 struct false_alarm_stats FalseAlmCnt; 632 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 633 struct sw_ant_sw DM_SWAT_Table; 634 635 struct edca_turbo DM_EDCA_Table; 636 u32 WMMEDCA_BE; 637 /* Copy from SD4 structure */ 638 /* */ 639 /* ================================================== */ 640 /* */ 641 642 /* PSD */ 643 u8 RSSI_BT; /* come from BT */ 644 struct odm_rate_adapt RateAdaptive; 645 646 647 struct odm_rf_cal_t RFCalibrateInfo; 648 }; /* DM_Dynamic_Mechanism_Structure */ 649 650 enum odm_rf_content { 651 odm_radioa_txt = 0x1000, 652 odm_radiob_txt = 0x1001, 653 odm_radioc_txt = 0x1002, 654 odm_radiod_txt = 0x1003 655 }; 656 657 /* Status code */ 658 enum rt_status { 659 RT_STATUS_SUCCESS, 660 RT_STATUS_FAILURE, 661 RT_STATUS_PENDING, 662 RT_STATUS_RESOURCE, 663 RT_STATUS_INVALID_CONTEXT, 664 RT_STATUS_INVALID_PARAMETER, 665 RT_STATUS_NOT_SUPPORT, 666 RT_STATUS_OS_API_FAILED, 667 }; 668 669 /* include "odm_function.h" */ 670 671 /* 3=========================================================== */ 672 /* 3 DIG */ 673 /* 3=========================================================== */ 674 675 enum dm_dig_op { 676 DIG_TYPE_THRESH_HIGH = 0, 677 DIG_TYPE_THRESH_LOW = 1, 678 DIG_TYPE_BACKOFF = 2, 679 DIG_TYPE_RX_GAIN_MIN = 3, 680 DIG_TYPE_RX_GAIN_MAX = 4, 681 DIG_TYPE_ENABLE = 5, 682 DIG_TYPE_DISABLE = 6, 683 DIG_OP_TYPE_MAX 684 }; 685 686 #define DM_DIG_THRESH_HIGH 40 687 #define DM_DIG_THRESH_LOW 35 688 689 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 690 691 692 #define DM_FALSEALARM_THRESH_LOW 400 693 #define DM_FALSEALARM_THRESH_HIGH 1000 694 695 #define DM_DIG_MAX_NIC 0x4e 696 #define DM_DIG_MIN_NIC 0x1e 697 698 #define DM_DIG_MAX_AP 0x32 699 #define DM_DIG_MIN_AP 0x20 700 701 #define DM_DIG_MAX_NIC_HP 0x46 702 #define DM_DIG_MIN_NIC_HP 0x2e 703 704 #define DM_DIG_MAX_AP_HP 0x42 705 #define DM_DIG_MIN_AP_HP 0x30 706 707 /* vivi 92c&92d has different definition, 20110504 */ 708 /* this is for 92c */ 709 #define DM_DIG_FA_TH0 0x200 710 #define DM_DIG_FA_TH1 0x300 711 #define DM_DIG_FA_TH2 0x400 712 /* this is for 92d */ 713 #define DM_DIG_FA_TH0_92D 0x100 714 #define DM_DIG_FA_TH1_92D 0x400 715 #define DM_DIG_FA_TH2_92D 0x600 716 717 #define DM_DIG_BACKOFF_MAX 12 718 #define DM_DIG_BACKOFF_MIN -4 719 #define DM_DIG_BACKOFF_DEFAULT 10 720 721 /* 3=========================================================== */ 722 /* 3 AGC RX High Power Mode */ 723 /* 3=========================================================== */ 724 #define LNA_Low_Gain_1 0x64 725 #define LNA_Low_Gain_2 0x5A 726 #define LNA_Low_Gain_3 0x58 727 728 #define FA_RXHP_TH1 5000 729 #define FA_RXHP_TH2 1500 730 #define FA_RXHP_TH3 800 731 #define FA_RXHP_TH4 600 732 #define FA_RXHP_TH5 500 733 734 /* 3=========================================================== */ 735 /* 3 EDCA */ 736 /* 3=========================================================== */ 737 738 /* 3=========================================================== */ 739 /* 3 Dynamic Tx Power */ 740 /* 3=========================================================== */ 741 /* Dynamic Tx Power Control Threshold */ 742 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 743 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 744 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 745 746 #define TxHighPwrLevel_Normal 0 747 #define TxHighPwrLevel_Level1 1 748 #define TxHighPwrLevel_Level2 2 749 #define TxHighPwrLevel_BT1 3 750 #define TxHighPwrLevel_BT2 4 751 #define TxHighPwrLevel_15 5 752 #define TxHighPwrLevel_35 6 753 #define TxHighPwrLevel_50 7 754 #define TxHighPwrLevel_70 8 755 #define TxHighPwrLevel_100 9 756 757 /* 3=========================================================== */ 758 /* 3 Rate Adaptive */ 759 /* 3=========================================================== */ 760 #define DM_RATR_STA_INIT 0 761 #define DM_RATR_STA_HIGH 1 762 #define DM_RATR_STA_MIDDLE 2 763 #define DM_RATR_STA_LOW 3 764 765 /* 3=========================================================== */ 766 /* 3 BB Power Save */ 767 /* 3=========================================================== */ 768 769 770 enum dm_1r_cca { 771 CCA_1R =0, 772 CCA_2R = 1, 773 CCA_MAX = 2, 774 }; 775 776 enum dm_rf_def { 777 RF_Save =0, 778 RF_Normal = 1, 779 RF_MAX = 2, 780 }; 781 782 /* 3=========================================================== */ 783 /* 3 Antenna Diversity */ 784 /* 3=========================================================== */ 785 enum dm_swas { 786 Antenna_A = 1, 787 Antenna_B = 2, 788 Antenna_MAX = 3, 789 }; 790 791 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 792 #define MAX_ANTENNA_DETECTION_CNT 10 793 794 /* */ 795 /* Extern Global Variables. */ 796 /* */ 797 #define OFDM_TABLE_SIZE_92C 37 798 #define OFDM_TABLE_SIZE_92D 43 799 #define CCK_TABLE_SIZE 33 800 801 extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; 802 extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; 803 extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; 804 805 806 807 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 808 /* This indicates two different the steps. */ 809 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 810 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 811 /* with original RSSI to determine if it is necessary to switch antenna. */ 812 #define SWAW_STEP_PEAK 0 813 #define SWAW_STEP_DETERMINE 1 814 815 struct hal_data_8723a; 816 817 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); 818 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); 819 820 void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); 821 822 823 #define dm_RF_Saving ODM_RF_Saving23a 824 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); 825 826 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a 827 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); 828 829 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, 830 u8 *pRATRState); 831 832 833 u32 ConvertTo_dB23a(u32 Value); 834 835 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); 836 837 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); 838 839 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid, u32 ra_mask, u8 rssi_level); 840 841 842 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); 843 844 void ODM_DMWatchdog23a(struct rtw_adapter *adapter); 845 846 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); 847 848 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); 849 850 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 851 852 void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); 853 854 void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); 855 856 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); 857 858 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); 859 860 #endif 861