1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25
26 #include <subdev/timer.h>
27
28 void
nvkm_pmu_pgob(struct nvkm_pmu * pmu,bool enable)29 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
30 {
31 const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu);
32 if (impl->pgob)
33 impl->pgob(pmu, enable);
34 }
35
36 static int
nvkm_pmu_send(struct nvkm_pmu * pmu,u32 reply[2],u32 process,u32 message,u32 data0,u32 data1)37 nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
38 u32 process, u32 message, u32 data0, u32 data1)
39 {
40 struct nvkm_subdev *subdev = nv_subdev(pmu);
41 u32 addr;
42
43 /* wait for a free slot in the fifo */
44 addr = nv_rd32(pmu, 0x10a4a0);
45 if (!nv_wait_ne(pmu, 0x10a4b0, 0xffffffff, addr ^ 8))
46 return -EBUSY;
47
48 /* we currently only support a single process at a time waiting
49 * on a synchronous reply, take the PMU mutex and tell the
50 * receive handler what we're waiting for
51 */
52 if (reply) {
53 mutex_lock(&subdev->mutex);
54 pmu->recv.message = message;
55 pmu->recv.process = process;
56 }
57
58 /* acquire data segment access */
59 do {
60 nv_wr32(pmu, 0x10a580, 0x00000001);
61 } while (nv_rd32(pmu, 0x10a580) != 0x00000001);
62
63 /* write the packet */
64 nv_wr32(pmu, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
65 pmu->send.base));
66 nv_wr32(pmu, 0x10a1c4, process);
67 nv_wr32(pmu, 0x10a1c4, message);
68 nv_wr32(pmu, 0x10a1c4, data0);
69 nv_wr32(pmu, 0x10a1c4, data1);
70 nv_wr32(pmu, 0x10a4a0, (addr + 1) & 0x0f);
71
72 /* release data segment access */
73 nv_wr32(pmu, 0x10a580, 0x00000000);
74
75 /* wait for reply, if requested */
76 if (reply) {
77 wait_event(pmu->recv.wait, (pmu->recv.process == 0));
78 reply[0] = pmu->recv.data[0];
79 reply[1] = pmu->recv.data[1];
80 mutex_unlock(&subdev->mutex);
81 }
82
83 return 0;
84 }
85
86 static void
nvkm_pmu_recv(struct work_struct * work)87 nvkm_pmu_recv(struct work_struct *work)
88 {
89 struct nvkm_pmu *pmu = container_of(work, struct nvkm_pmu, recv.work);
90 u32 process, message, data0, data1;
91
92 /* nothing to do if GET == PUT */
93 u32 addr = nv_rd32(pmu, 0x10a4cc);
94 if (addr == nv_rd32(pmu, 0x10a4c8))
95 return;
96
97 /* acquire data segment access */
98 do {
99 nv_wr32(pmu, 0x10a580, 0x00000002);
100 } while (nv_rd32(pmu, 0x10a580) != 0x00000002);
101
102 /* read the packet */
103 nv_wr32(pmu, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
104 pmu->recv.base));
105 process = nv_rd32(pmu, 0x10a1c4);
106 message = nv_rd32(pmu, 0x10a1c4);
107 data0 = nv_rd32(pmu, 0x10a1c4);
108 data1 = nv_rd32(pmu, 0x10a1c4);
109 nv_wr32(pmu, 0x10a4cc, (addr + 1) & 0x0f);
110
111 /* release data segment access */
112 nv_wr32(pmu, 0x10a580, 0x00000000);
113
114 /* wake process if it's waiting on a synchronous reply */
115 if (pmu->recv.process) {
116 if (process == pmu->recv.process &&
117 message == pmu->recv.message) {
118 pmu->recv.data[0] = data0;
119 pmu->recv.data[1] = data1;
120 pmu->recv.process = 0;
121 wake_up(&pmu->recv.wait);
122 return;
123 }
124 }
125
126 /* right now there's no other expected responses from the engine,
127 * so assume that any unexpected message is an error.
128 */
129 nv_warn(pmu, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
130 (char)((process & 0x000000ff) >> 0),
131 (char)((process & 0x0000ff00) >> 8),
132 (char)((process & 0x00ff0000) >> 16),
133 (char)((process & 0xff000000) >> 24),
134 process, message, data0, data1);
135 }
136
137 static void
nvkm_pmu_intr(struct nvkm_subdev * subdev)138 nvkm_pmu_intr(struct nvkm_subdev *subdev)
139 {
140 struct nvkm_pmu *pmu = (void *)subdev;
141 u32 disp = nv_rd32(pmu, 0x10a01c);
142 u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16);
143
144 if (intr & 0x00000020) {
145 u32 stat = nv_rd32(pmu, 0x10a16c);
146 if (stat & 0x80000000) {
147 nv_error(pmu, "UAS fault at 0x%06x addr 0x%08x\n",
148 stat & 0x00ffffff, nv_rd32(pmu, 0x10a168));
149 nv_wr32(pmu, 0x10a16c, 0x00000000);
150 intr &= ~0x00000020;
151 }
152 }
153
154 if (intr & 0x00000040) {
155 schedule_work(&pmu->recv.work);
156 nv_wr32(pmu, 0x10a004, 0x00000040);
157 intr &= ~0x00000040;
158 }
159
160 if (intr & 0x00000080) {
161 nv_info(pmu, "wr32 0x%06x 0x%08x\n", nv_rd32(pmu, 0x10a7a0),
162 nv_rd32(pmu, 0x10a7a4));
163 nv_wr32(pmu, 0x10a004, 0x00000080);
164 intr &= ~0x00000080;
165 }
166
167 if (intr) {
168 nv_error(pmu, "intr 0x%08x\n", intr);
169 nv_wr32(pmu, 0x10a004, intr);
170 }
171 }
172
173 int
_nvkm_pmu_fini(struct nvkm_object * object,bool suspend)174 _nvkm_pmu_fini(struct nvkm_object *object, bool suspend)
175 {
176 struct nvkm_pmu *pmu = (void *)object;
177
178 nv_wr32(pmu, 0x10a014, 0x00000060);
179 flush_work(&pmu->recv.work);
180
181 return nvkm_subdev_fini(&pmu->base, suspend);
182 }
183
184 int
_nvkm_pmu_init(struct nvkm_object * object)185 _nvkm_pmu_init(struct nvkm_object *object)
186 {
187 const struct nvkm_pmu_impl *impl = (void *)object->oclass;
188 struct nvkm_pmu *pmu = (void *)object;
189 int ret, i;
190
191 ret = nvkm_subdev_init(&pmu->base);
192 if (ret)
193 return ret;
194
195 nv_subdev(pmu)->intr = nvkm_pmu_intr;
196 pmu->message = nvkm_pmu_send;
197 pmu->pgob = nvkm_pmu_pgob;
198
199 /* prevent previous ucode from running, wait for idle, reset */
200 nv_wr32(pmu, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
201 nv_wait(pmu, 0x10a04c, 0xffffffff, 0x00000000);
202 nv_mask(pmu, 0x000200, 0x00002000, 0x00000000);
203 nv_mask(pmu, 0x000200, 0x00002000, 0x00002000);
204 nv_rd32(pmu, 0x000200);
205 nv_wait(pmu, 0x10a10c, 0x00000006, 0x00000000);
206
207 /* upload data segment */
208 nv_wr32(pmu, 0x10a1c0, 0x01000000);
209 for (i = 0; i < impl->data.size / 4; i++)
210 nv_wr32(pmu, 0x10a1c4, impl->data.data[i]);
211
212 /* upload code segment */
213 nv_wr32(pmu, 0x10a180, 0x01000000);
214 for (i = 0; i < impl->code.size / 4; i++) {
215 if ((i & 0x3f) == 0)
216 nv_wr32(pmu, 0x10a188, i >> 6);
217 nv_wr32(pmu, 0x10a184, impl->code.data[i]);
218 }
219
220 /* start it running */
221 nv_wr32(pmu, 0x10a10c, 0x00000000);
222 nv_wr32(pmu, 0x10a104, 0x00000000);
223 nv_wr32(pmu, 0x10a100, 0x00000002);
224
225 /* wait for valid host->pmu ring configuration */
226 if (!nv_wait_ne(pmu, 0x10a4d0, 0xffffffff, 0x00000000))
227 return -EBUSY;
228 pmu->send.base = nv_rd32(pmu, 0x10a4d0) & 0x0000ffff;
229 pmu->send.size = nv_rd32(pmu, 0x10a4d0) >> 16;
230
231 /* wait for valid pmu->host ring configuration */
232 if (!nv_wait_ne(pmu, 0x10a4dc, 0xffffffff, 0x00000000))
233 return -EBUSY;
234 pmu->recv.base = nv_rd32(pmu, 0x10a4dc) & 0x0000ffff;
235 pmu->recv.size = nv_rd32(pmu, 0x10a4dc) >> 16;
236
237 nv_wr32(pmu, 0x10a010, 0x000000e0);
238 return 0;
239 }
240
241 int
nvkm_pmu_create_(struct nvkm_object * parent,struct nvkm_object * engine,struct nvkm_oclass * oclass,int length,void ** pobject)242 nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine,
243 struct nvkm_oclass *oclass, int length, void **pobject)
244 {
245 struct nvkm_pmu *pmu;
246 int ret;
247
248 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU",
249 "pmu", length, pobject);
250 pmu = *pobject;
251 if (ret)
252 return ret;
253
254 INIT_WORK(&pmu->recv.work, nvkm_pmu_recv);
255 init_waitqueue_head(&pmu->recv.wait);
256 return 0;
257 }
258
259 int
_nvkm_pmu_ctor(struct nvkm_object * parent,struct nvkm_object * engine,struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)260 _nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
261 struct nvkm_oclass *oclass, void *data, u32 size,
262 struct nvkm_object **pobject)
263 {
264 struct nvkm_pmu *pmu;
265 int ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
266 *pobject = nv_object(pmu);
267 return ret;
268 }
269