1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25
26 void
nv50_gpio_reset(struct nvkm_gpio * gpio,u8 match)27 nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
28 {
29 struct nvkm_bios *bios = nvkm_bios(gpio);
30 u8 ver, len;
31 u16 entry;
32 int ent = -1;
33
34 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
35 static const u32 regs[] = { 0xe100, 0xe28c };
36 u32 data = nv_ro32(bios, entry);
37 u8 line = (data & 0x0000001f);
38 u8 func = (data & 0x0000ff00) >> 8;
39 u8 defs = !!(data & 0x01000000);
40 u8 unk0 = !!(data & 0x02000000);
41 u8 unk1 = !!(data & 0x04000000);
42 u32 val = (unk1 << 16) | unk0;
43 u32 reg = regs[line >> 4];
44 u32 lsh = line & 0x0f;
45
46 if ( func == DCB_GPIO_UNUSED ||
47 (match != DCB_GPIO_UNUSED && match != func))
48 continue;
49
50 gpio->set(gpio, 0, func, line, defs);
51
52 nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh);
53 }
54 }
55
56 int
nv50_gpio_location(int line,u32 * reg,u32 * shift)57 nv50_gpio_location(int line, u32 *reg, u32 *shift)
58 {
59 const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
60
61 if (line >= 32)
62 return -EINVAL;
63
64 *reg = nv50_gpio_reg[line >> 3];
65 *shift = (line & 7) << 2;
66 return 0;
67 }
68
69 int
nv50_gpio_drive(struct nvkm_gpio * gpio,int line,int dir,int out)70 nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
71 {
72 u32 reg, shift;
73
74 if (nv50_gpio_location(line, ®, &shift))
75 return -EINVAL;
76
77 nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);
78 return 0;
79 }
80
81 int
nv50_gpio_sense(struct nvkm_gpio * gpio,int line)82 nv50_gpio_sense(struct nvkm_gpio *gpio, int line)
83 {
84 u32 reg, shift;
85
86 if (nv50_gpio_location(line, ®, &shift))
87 return -EINVAL;
88
89 return !!(nv_rd32(gpio, reg) & (4 << shift));
90 }
91
92 static void
nv50_gpio_intr_stat(struct nvkm_gpio * gpio,u32 * hi,u32 * lo)93 nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
94 {
95 u32 intr = nv_rd32(gpio, 0x00e054);
96 u32 stat = nv_rd32(gpio, 0x00e050) & intr;
97 *lo = (stat & 0xffff0000) >> 16;
98 *hi = (stat & 0x0000ffff);
99 nv_wr32(gpio, 0x00e054, intr);
100 }
101
102 static void
nv50_gpio_intr_mask(struct nvkm_gpio * gpio,u32 type,u32 mask,u32 data)103 nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
104 {
105 u32 inte = nv_rd32(gpio, 0x00e050);
106 if (type & NVKM_GPIO_LO)
107 inte = (inte & ~(mask << 16)) | (data << 16);
108 if (type & NVKM_GPIO_HI)
109 inte = (inte & ~mask) | data;
110 nv_wr32(gpio, 0x00e050, inte);
111 }
112
113 struct nvkm_oclass *
114 nv50_gpio_oclass = &(struct nvkm_gpio_impl) {
115 .base.handle = NV_SUBDEV(GPIO, 0x50),
116 .base.ofuncs = &(struct nvkm_ofuncs) {
117 .ctor = _nvkm_gpio_ctor,
118 .dtor = _nvkm_gpio_dtor,
119 .init = _nvkm_gpio_init,
120 .fini = _nvkm_gpio_fini,
121 },
122 .lines = 16,
123 .intr_stat = nv50_gpio_intr_stat,
124 .intr_mask = nv50_gpio_intr_mask,
125 .drive = nv50_gpio_drive,
126 .sense = nv50_gpio_sense,
127 .reset = nv50_gpio_reset,
128 }.base;
129