1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv04.h"
25
26 #include <core/device.h>
27 #include <core/gpuobj.h>
28 #include <core/option.h>
29 #include <subdev/timer.h>
30
31 #define NV41_GART_SIZE (512 * 1024 * 1024)
32 #define NV41_GART_PAGE ( 4 * 1024)
33
34 /*******************************************************************************
35 * VM map/unmap callbacks
36 ******************************************************************************/
37
38 static void
nv41_vm_map_sg(struct nvkm_vma * vma,struct nvkm_gpuobj * pgt,struct nvkm_mem * mem,u32 pte,u32 cnt,dma_addr_t * list)39 nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
40 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
41 {
42 pte = pte * 4;
43 while (cnt) {
44 u32 page = PAGE_SIZE / NV41_GART_PAGE;
45 u64 phys = (u64)*list++;
46 while (cnt && page--) {
47 nv_wo32(pgt, pte, (phys >> 7) | 1);
48 phys += NV41_GART_PAGE;
49 pte += 4;
50 cnt -= 1;
51 }
52 }
53 }
54
55 static void
nv41_vm_unmap(struct nvkm_gpuobj * pgt,u32 pte,u32 cnt)56 nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
57 {
58 pte = pte * 4;
59 while (cnt--) {
60 nv_wo32(pgt, pte, 0x00000000);
61 pte += 4;
62 }
63 }
64
65 static void
nv41_vm_flush(struct nvkm_vm * vm)66 nv41_vm_flush(struct nvkm_vm *vm)
67 {
68 struct nv04_mmu_priv *priv = (void *)vm->mmu;
69
70 mutex_lock(&nv_subdev(priv)->mutex);
71 nv_wr32(priv, 0x100810, 0x00000022);
72 if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) {
73 nv_warn(priv, "flush timeout, 0x%08x\n",
74 nv_rd32(priv, 0x100810));
75 }
76 nv_wr32(priv, 0x100810, 0x00000000);
77 mutex_unlock(&nv_subdev(priv)->mutex);
78 }
79
80 /*******************************************************************************
81 * MMU subdev
82 ******************************************************************************/
83
84 static int
nv41_mmu_ctor(struct nvkm_object * parent,struct nvkm_object * engine,struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)85 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
86 struct nvkm_oclass *oclass, void *data, u32 size,
87 struct nvkm_object **pobject)
88 {
89 struct nvkm_device *device = nv_device(parent);
90 struct nv04_mmu_priv *priv;
91 int ret;
92
93 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
94 !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
95 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
96 data, size, pobject);
97 }
98
99 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
100 "pciegart", &priv);
101 *pobject = nv_object(priv);
102 if (ret)
103 return ret;
104
105 priv->base.create = nv04_vm_create;
106 priv->base.limit = NV41_GART_SIZE;
107 priv->base.dma_bits = 39;
108 priv->base.pgt_bits = 32 - 12;
109 priv->base.spg_shift = 12;
110 priv->base.lpg_shift = 12;
111 priv->base.map_sg = nv41_vm_map_sg;
112 priv->base.unmap = nv41_vm_unmap;
113 priv->base.flush = nv41_vm_flush;
114
115 ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
116 &priv->vm);
117 if (ret)
118 return ret;
119
120 ret = nvkm_gpuobj_new(nv_object(priv), NULL,
121 (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
122 NVOBJ_FLAG_ZERO_ALLOC,
123 &priv->vm->pgt[0].obj[0]);
124 priv->vm->pgt[0].refcount[0] = 1;
125 if (ret)
126 return ret;
127
128 return 0;
129 }
130
131 static int
nv41_mmu_init(struct nvkm_object * object)132 nv41_mmu_init(struct nvkm_object *object)
133 {
134 struct nv04_mmu_priv *priv = (void *)object;
135 struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0];
136 int ret;
137
138 ret = nvkm_mmu_init(&priv->base);
139 if (ret)
140 return ret;
141
142 nv_wr32(priv, 0x100800, dma->addr | 0x00000002);
143 nv_mask(priv, 0x10008c, 0x00000100, 0x00000100);
144 nv_wr32(priv, 0x100820, 0x00000000);
145 return 0;
146 }
147
148 struct nvkm_oclass
149 nv41_mmu_oclass = {
150 .handle = NV_SUBDEV(MMU, 0x41),
151 .ofuncs = &(struct nvkm_ofuncs) {
152 .ctor = nv41_mmu_ctor,
153 .dtor = nv04_mmu_dtor,
154 .init = nv41_mmu_init,
155 .fini = _nvkm_mmu_fini,
156 },
157 };
158