1 /*
2   comedi/drivers/ni_tiocmd.c
3   Command support for NI general purpose counters
4 
5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
6 
7   This program is free software; you can redistribute it and/or modify
8   it under the terms of the GNU General Public License as published by
9   the Free Software Foundation; either version 2 of the License, or
10   (at your option) any later version.
11 
12   This program is distributed in the hope that it will be useful,
13   but WITHOUT ANY WARRANTY; without even the implied warranty of
14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15   GNU General Public License for more details.
16 */
17 
18 /*
19  * Module: ni_tiocmd
20  * Description: National Instruments general purpose counters command support
21  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
22  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
23  *         Wim.Meeussen@mech.kuleuven.ac.be,
24  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
25  *         Frank Mori Hess <fmhess@users.sourceforge.net>
26  * Updated: Fri, 11 Apr 2008 12:32:35 +0100
27  * Status: works
28  *
29  * This module is not used directly by end-users.  Rather, it
30  * is used by other drivers (for example ni_660x and ni_pcimio)
31  * to provide command support for NI's general purpose counters.
32  * It was originally split out of ni_tio.c to stop the 'ni_tio'
33  * module depending on the 'mite' module.
34  *
35  * References:
36  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
37  * DAQ 6601/6602 User Manual (NI 322137B-01)
38  * 340934b.pdf  DAQ-STC reference manual
39  */
40 
41 /*
42 TODO:
43 	Support use of both banks X and Y
44 */
45 
46 #include <linux/module.h>
47 #include "ni_tio_internal.h"
48 #include "mite.h"
49 
ni_tio_configure_dma(struct ni_gpct * counter,bool enable,bool read)50 static void ni_tio_configure_dma(struct ni_gpct *counter,
51 				 bool enable, bool read)
52 {
53 	struct ni_gpct_device *counter_dev = counter->counter_dev;
54 	unsigned cidx = counter->counter_index;
55 	unsigned mask;
56 	unsigned bits;
57 
58 	mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
59 	bits = 0;
60 
61 	if (enable) {
62 		if (read)
63 			bits |= GI_READ_ACKS_IRQ;
64 		else
65 			bits |= GI_WRITE_ACKS_IRQ;
66 	}
67 	ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
68 
69 	switch (counter_dev->variant) {
70 	case ni_gpct_variant_e_series:
71 		break;
72 	case ni_gpct_variant_m_series:
73 	case ni_gpct_variant_660x:
74 		mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
75 		bits = 0;
76 
77 		if (enable)
78 			bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
79 		if (!read)
80 			bits |= GI_DMA_WRITE;
81 		ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
82 		break;
83 	}
84 }
85 
ni_tio_input_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)86 static int ni_tio_input_inttrig(struct comedi_device *dev,
87 				struct comedi_subdevice *s,
88 				unsigned int trig_num)
89 {
90 	struct ni_gpct *counter = s->private;
91 	struct comedi_cmd *cmd = &s->async->cmd;
92 	unsigned long flags;
93 	int ret = 0;
94 
95 	if (trig_num != cmd->start_arg)
96 		return -EINVAL;
97 
98 	spin_lock_irqsave(&counter->lock, flags);
99 	if (counter->mite_chan)
100 		mite_dma_arm(counter->mite_chan);
101 	else
102 		ret = -EIO;
103 	spin_unlock_irqrestore(&counter->lock, flags);
104 	if (ret < 0)
105 		return ret;
106 	ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
107 	s->async->inttrig = NULL;
108 
109 	return ret;
110 }
111 
ni_tio_input_cmd(struct comedi_subdevice * s)112 static int ni_tio_input_cmd(struct comedi_subdevice *s)
113 {
114 	struct ni_gpct *counter = s->private;
115 	struct ni_gpct_device *counter_dev = counter->counter_dev;
116 	unsigned cidx = counter->counter_index;
117 	struct comedi_async *async = s->async;
118 	struct comedi_cmd *cmd = &async->cmd;
119 	int ret = 0;
120 
121 	/* write alloc the entire buffer */
122 	comedi_buf_write_alloc(s, async->prealloc_bufsz);
123 	counter->mite_chan->dir = COMEDI_INPUT;
124 	switch (counter_dev->variant) {
125 	case ni_gpct_variant_m_series:
126 	case ni_gpct_variant_660x:
127 		mite_prep_dma(counter->mite_chan, 32, 32);
128 		break;
129 	case ni_gpct_variant_e_series:
130 		mite_prep_dma(counter->mite_chan, 16, 32);
131 		break;
132 	default:
133 		BUG();
134 		break;
135 	}
136 	ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
137 	ni_tio_configure_dma(counter, true, true);
138 
139 	if (cmd->start_src == TRIG_INT) {
140 		async->inttrig = &ni_tio_input_inttrig;
141 	} else {	/* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
142 		async->inttrig = NULL;
143 		mite_dma_arm(counter->mite_chan);
144 
145 		if (cmd->start_src == TRIG_NOW)
146 			ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
147 		else if (cmd->start_src == TRIG_EXT)
148 			ret = ni_tio_arm(counter, 1, cmd->start_arg);
149 	}
150 	return ret;
151 }
152 
ni_tio_output_cmd(struct comedi_subdevice * s)153 static int ni_tio_output_cmd(struct comedi_subdevice *s)
154 {
155 	struct ni_gpct *counter = s->private;
156 
157 	dev_err(counter->counter_dev->dev->class_dev,
158 		"output commands not yet implemented.\n");
159 	return -ENOTSUPP;
160 }
161 
ni_tio_cmd_setup(struct comedi_subdevice * s)162 static int ni_tio_cmd_setup(struct comedi_subdevice *s)
163 {
164 	struct comedi_cmd *cmd = &s->async->cmd;
165 	struct ni_gpct *counter = s->private;
166 	unsigned cidx = counter->counter_index;
167 	int set_gate_source = 0;
168 	unsigned gate_source;
169 	int retval = 0;
170 
171 	if (cmd->scan_begin_src == TRIG_EXT) {
172 		set_gate_source = 1;
173 		gate_source = cmd->scan_begin_arg;
174 	} else if (cmd->convert_src == TRIG_EXT) {
175 		set_gate_source = 1;
176 		gate_source = cmd->convert_arg;
177 	}
178 	if (set_gate_source)
179 		retval = ni_tio_set_gate_src(counter, 0, gate_source);
180 	if (cmd->flags & CMDF_WAKE_EOS) {
181 		ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
182 				GI_GATE_INTERRUPT_ENABLE(cidx),
183 				GI_GATE_INTERRUPT_ENABLE(cidx));
184 	}
185 	return retval;
186 }
187 
ni_tio_cmd(struct comedi_device * dev,struct comedi_subdevice * s)188 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
189 {
190 	struct ni_gpct *counter = s->private;
191 	struct comedi_async *async = s->async;
192 	struct comedi_cmd *cmd = &async->cmd;
193 	int retval = 0;
194 	unsigned long flags;
195 
196 	spin_lock_irqsave(&counter->lock, flags);
197 	if (!counter->mite_chan) {
198 		dev_err(counter->counter_dev->dev->class_dev,
199 			"commands only supported with DMA.  ");
200 		dev_err(counter->counter_dev->dev->class_dev,
201 			"Interrupt-driven commands not yet implemented.\n");
202 		retval = -EIO;
203 	} else {
204 		retval = ni_tio_cmd_setup(s);
205 		if (retval == 0) {
206 			if (cmd->flags & CMDF_WRITE)
207 				retval = ni_tio_output_cmd(s);
208 			else
209 				retval = ni_tio_input_cmd(s);
210 		}
211 	}
212 	spin_unlock_irqrestore(&counter->lock, flags);
213 	return retval;
214 }
215 EXPORT_SYMBOL_GPL(ni_tio_cmd);
216 
ni_tio_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)217 int ni_tio_cmdtest(struct comedi_device *dev,
218 		   struct comedi_subdevice *s,
219 		   struct comedi_cmd *cmd)
220 {
221 	struct ni_gpct *counter = s->private;
222 	int err = 0;
223 	unsigned int sources;
224 
225 	/* Step 1 : check if triggers are trivially valid */
226 
227 	sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
228 	if (ni_tio_counting_mode_registers_present(counter->counter_dev))
229 		sources |= TRIG_EXT;
230 	err |= comedi_check_trigger_src(&cmd->start_src, sources);
231 
232 	err |= comedi_check_trigger_src(&cmd->scan_begin_src,
233 					TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
234 	err |= comedi_check_trigger_src(&cmd->convert_src,
235 					TRIG_NOW | TRIG_EXT | TRIG_OTHER);
236 	err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
237 	err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
238 
239 	if (err)
240 		return 1;
241 
242 	/* Step 2a : make sure trigger sources are unique */
243 
244 	err |= comedi_check_trigger_is_unique(cmd->start_src);
245 	err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
246 	err |= comedi_check_trigger_is_unique(cmd->convert_src);
247 
248 	/* Step 2b : and mutually compatible */
249 
250 	if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
251 		err |= -EINVAL;
252 
253 	if (err)
254 		return 2;
255 
256 	/* Step 3: check if arguments are trivially valid */
257 
258 	switch (cmd->start_src) {
259 	case TRIG_NOW:
260 	case TRIG_INT:
261 	case TRIG_OTHER:
262 		err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
263 		break;
264 	case TRIG_EXT:
265 		/* start_arg is the start_trigger passed to ni_tio_arm() */
266 		break;
267 	}
268 
269 	if (cmd->scan_begin_src != TRIG_EXT)
270 		err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
271 
272 	if (cmd->convert_src != TRIG_EXT)
273 		err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
274 
275 	err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
276 					   cmd->chanlist_len);
277 	err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
278 
279 	if (err)
280 		return 3;
281 
282 	/* Step 4: fix up any arguments */
283 
284 	/* Step 5: check channel list if it exists */
285 
286 	return 0;
287 }
288 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
289 
ni_tio_cancel(struct ni_gpct * counter)290 int ni_tio_cancel(struct ni_gpct *counter)
291 {
292 	unsigned cidx = counter->counter_index;
293 	unsigned long flags;
294 
295 	ni_tio_arm(counter, 0, 0);
296 	spin_lock_irqsave(&counter->lock, flags);
297 	if (counter->mite_chan)
298 		mite_dma_disarm(counter->mite_chan);
299 	spin_unlock_irqrestore(&counter->lock, flags);
300 	ni_tio_configure_dma(counter, false, false);
301 
302 	ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
303 			GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
304 	return 0;
305 }
306 EXPORT_SYMBOL_GPL(ni_tio_cancel);
307 
308 	/* During buffered input counter operation for e-series, the gate
309 	   interrupt is acked automatically by the dma controller, due to the
310 	   Gi_Read/Write_Acknowledges_IRQ bits in the input select register.  */
should_ack_gate(struct ni_gpct * counter)311 static int should_ack_gate(struct ni_gpct *counter)
312 {
313 	unsigned long flags;
314 	int retval = 0;
315 
316 	switch (counter->counter_dev->variant) {
317 	case ni_gpct_variant_m_series:
318 	/*  not sure if 660x really supports gate
319 	    interrupts (the bits are not listed
320 	    in register-level manual) */
321 	case ni_gpct_variant_660x:
322 		return 1;
323 	case ni_gpct_variant_e_series:
324 		spin_lock_irqsave(&counter->lock, flags);
325 		{
326 			if (!counter->mite_chan ||
327 			    counter->mite_chan->dir != COMEDI_INPUT ||
328 			    (mite_done(counter->mite_chan))) {
329 				retval = 1;
330 			}
331 		}
332 		spin_unlock_irqrestore(&counter->lock, flags);
333 		break;
334 	}
335 	return retval;
336 }
337 
ni_tio_acknowledge_and_confirm(struct ni_gpct * counter,int * gate_error,int * tc_error,int * perm_stale_data,int * stale_data)338 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
339 					   int *gate_error,
340 					   int *tc_error,
341 					   int *perm_stale_data,
342 					   int *stale_data)
343 {
344 	unsigned cidx = counter->counter_index;
345 	const unsigned short gxx_status = read_register(counter,
346 						NITIO_SHARED_STATUS_REG(cidx));
347 	const unsigned short gi_status = read_register(counter,
348 						NITIO_STATUS_REG(cidx));
349 	unsigned ack = 0;
350 
351 	if (gate_error)
352 		*gate_error = 0;
353 	if (tc_error)
354 		*tc_error = 0;
355 	if (perm_stale_data)
356 		*perm_stale_data = 0;
357 	if (stale_data)
358 		*stale_data = 0;
359 
360 	if (gxx_status & GI_GATE_ERROR(cidx)) {
361 		ack |= GI_GATE_ERROR_CONFIRM(cidx);
362 		if (gate_error) {
363 			/*660x don't support automatic acknowledgment
364 			  of gate interrupt via dma read/write
365 			   and report bogus gate errors */
366 			if (counter->counter_dev->variant !=
367 			    ni_gpct_variant_660x)
368 				*gate_error = 1;
369 		}
370 	}
371 	if (gxx_status & GI_TC_ERROR(cidx)) {
372 		ack |= GI_TC_ERROR_CONFIRM(cidx);
373 		if (tc_error)
374 			*tc_error = 1;
375 	}
376 	if (gi_status & GI_TC)
377 		ack |= GI_TC_INTERRUPT_ACK;
378 	if (gi_status & GI_GATE_INTERRUPT) {
379 		if (should_ack_gate(counter))
380 			ack |= GI_GATE_INTERRUPT_ACK;
381 	}
382 	if (ack)
383 		write_register(counter, ack, NITIO_INT_ACK_REG(cidx));
384 	if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
385 	    GI_LOADING_ON_GATE) {
386 		if (gxx_status & GI_STALE_DATA(cidx)) {
387 			if (stale_data)
388 				*stale_data = 1;
389 		}
390 		if (read_register(counter, NITIO_STATUS2_REG(cidx)) &
391 		    GI_PERMANENT_STALE(cidx)) {
392 			dev_info(counter->counter_dev->dev->class_dev,
393 				 "%s: Gi_Permanent_Stale_Data detected.\n",
394 				 __func__);
395 			if (perm_stale_data)
396 				*perm_stale_data = 1;
397 		}
398 	}
399 }
400 
ni_tio_acknowledge(struct ni_gpct * counter)401 void ni_tio_acknowledge(struct ni_gpct *counter)
402 {
403 	ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
404 }
405 EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
406 
ni_tio_handle_interrupt(struct ni_gpct * counter,struct comedi_subdevice * s)407 void ni_tio_handle_interrupt(struct ni_gpct *counter,
408 			     struct comedi_subdevice *s)
409 {
410 	unsigned cidx = counter->counter_index;
411 	unsigned gpct_mite_status;
412 	unsigned long flags;
413 	int gate_error;
414 	int tc_error;
415 	int perm_stale_data;
416 
417 	ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
418 				       &perm_stale_data, NULL);
419 	if (gate_error) {
420 		dev_notice(counter->counter_dev->dev->class_dev,
421 			   "%s: Gi_Gate_Error detected.\n", __func__);
422 		s->async->events |= COMEDI_CB_OVERFLOW;
423 	}
424 	if (perm_stale_data)
425 		s->async->events |= COMEDI_CB_ERROR;
426 	switch (counter->counter_dev->variant) {
427 	case ni_gpct_variant_m_series:
428 	case ni_gpct_variant_660x:
429 		if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) &
430 		    GI_DRQ_ERROR) {
431 			dev_notice(counter->counter_dev->dev->class_dev,
432 				   "%s: Gi_DRQ_Error detected.\n", __func__);
433 			s->async->events |= COMEDI_CB_OVERFLOW;
434 		}
435 		break;
436 	case ni_gpct_variant_e_series:
437 		break;
438 	}
439 	spin_lock_irqsave(&counter->lock, flags);
440 	if (!counter->mite_chan) {
441 		spin_unlock_irqrestore(&counter->lock, flags);
442 		return;
443 	}
444 	gpct_mite_status = mite_get_status(counter->mite_chan);
445 	if (gpct_mite_status & CHSR_LINKC)
446 		writel(CHOR_CLRLC,
447 		       counter->mite_chan->mite->mite_io_addr +
448 		       MITE_CHOR(counter->mite_chan->channel));
449 	mite_sync_input_dma(counter->mite_chan, s);
450 	spin_unlock_irqrestore(&counter->lock, flags);
451 }
452 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
453 
ni_tio_set_mite_channel(struct ni_gpct * counter,struct mite_channel * mite_chan)454 void ni_tio_set_mite_channel(struct ni_gpct *counter,
455 			     struct mite_channel *mite_chan)
456 {
457 	unsigned long flags;
458 
459 	spin_lock_irqsave(&counter->lock, flags);
460 	counter->mite_chan = mite_chan;
461 	spin_unlock_irqrestore(&counter->lock, flags);
462 }
463 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
464 
ni_tiocmd_init_module(void)465 static int __init ni_tiocmd_init_module(void)
466 {
467 	return 0;
468 }
469 module_init(ni_tiocmd_init_module);
470 
ni_tiocmd_cleanup_module(void)471 static void __exit ni_tiocmd_cleanup_module(void)
472 {
473 }
474 module_exit(ni_tiocmd_cleanup_module);
475 
476 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
477 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
478 MODULE_LICENSE("GPL");
479