1 /*
2 comedi/drivers/ni_tiocmd.c
3 Command support for NI general purpose counters
4
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16 */
17
18 /*
19 * Module: ni_tiocmd
20 * Description: National Instruments general purpose counters command support
21 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
22 * Herman.Bruyninckx@mech.kuleuven.ac.be,
23 * Wim.Meeussen@mech.kuleuven.ac.be,
24 * Klaas.Gadeyne@mech.kuleuven.ac.be,
25 * Frank Mori Hess <fmhess@users.sourceforge.net>
26 * Updated: Fri, 11 Apr 2008 12:32:35 +0100
27 * Status: works
28 *
29 * This module is not used directly by end-users. Rather, it
30 * is used by other drivers (for example ni_660x and ni_pcimio)
31 * to provide command support for NI's general purpose counters.
32 * It was originally split out of ni_tio.c to stop the 'ni_tio'
33 * module depending on the 'mite' module.
34 *
35 * References:
36 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
37 * DAQ 6601/6602 User Manual (NI 322137B-01)
38 * 340934b.pdf DAQ-STC reference manual
39 */
40
41 /*
42 TODO:
43 Support use of both banks X and Y
44 */
45
46 #include <linux/module.h>
47 #include "ni_tio_internal.h"
48 #include "mite.h"
49
ni_tio_configure_dma(struct ni_gpct * counter,bool enable,bool read)50 static void ni_tio_configure_dma(struct ni_gpct *counter,
51 bool enable, bool read)
52 {
53 struct ni_gpct_device *counter_dev = counter->counter_dev;
54 unsigned cidx = counter->counter_index;
55 unsigned mask;
56 unsigned bits;
57
58 mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
59 bits = 0;
60
61 if (enable) {
62 if (read)
63 bits |= GI_READ_ACKS_IRQ;
64 else
65 bits |= GI_WRITE_ACKS_IRQ;
66 }
67 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
68
69 switch (counter_dev->variant) {
70 case ni_gpct_variant_e_series:
71 break;
72 case ni_gpct_variant_m_series:
73 case ni_gpct_variant_660x:
74 mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
75 bits = 0;
76
77 if (enable)
78 bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
79 if (!read)
80 bits |= GI_DMA_WRITE;
81 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
82 break;
83 }
84 }
85
ni_tio_input_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)86 static int ni_tio_input_inttrig(struct comedi_device *dev,
87 struct comedi_subdevice *s,
88 unsigned int trig_num)
89 {
90 struct ni_gpct *counter = s->private;
91 struct comedi_cmd *cmd = &s->async->cmd;
92 unsigned long flags;
93 int ret = 0;
94
95 if (trig_num != cmd->start_arg)
96 return -EINVAL;
97
98 spin_lock_irqsave(&counter->lock, flags);
99 if (counter->mite_chan)
100 mite_dma_arm(counter->mite_chan);
101 else
102 ret = -EIO;
103 spin_unlock_irqrestore(&counter->lock, flags);
104 if (ret < 0)
105 return ret;
106 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
107 s->async->inttrig = NULL;
108
109 return ret;
110 }
111
ni_tio_input_cmd(struct comedi_subdevice * s)112 static int ni_tio_input_cmd(struct comedi_subdevice *s)
113 {
114 struct ni_gpct *counter = s->private;
115 struct ni_gpct_device *counter_dev = counter->counter_dev;
116 unsigned cidx = counter->counter_index;
117 struct comedi_async *async = s->async;
118 struct comedi_cmd *cmd = &async->cmd;
119 int ret = 0;
120
121 /* write alloc the entire buffer */
122 comedi_buf_write_alloc(s, async->prealloc_bufsz);
123 counter->mite_chan->dir = COMEDI_INPUT;
124 switch (counter_dev->variant) {
125 case ni_gpct_variant_m_series:
126 case ni_gpct_variant_660x:
127 mite_prep_dma(counter->mite_chan, 32, 32);
128 break;
129 case ni_gpct_variant_e_series:
130 mite_prep_dma(counter->mite_chan, 16, 32);
131 break;
132 default:
133 BUG();
134 break;
135 }
136 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
137 ni_tio_configure_dma(counter, true, true);
138
139 if (cmd->start_src == TRIG_INT) {
140 async->inttrig = &ni_tio_input_inttrig;
141 } else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
142 async->inttrig = NULL;
143 mite_dma_arm(counter->mite_chan);
144
145 if (cmd->start_src == TRIG_NOW)
146 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
147 else if (cmd->start_src == TRIG_EXT)
148 ret = ni_tio_arm(counter, 1, cmd->start_arg);
149 }
150 return ret;
151 }
152
ni_tio_output_cmd(struct comedi_subdevice * s)153 static int ni_tio_output_cmd(struct comedi_subdevice *s)
154 {
155 struct ni_gpct *counter = s->private;
156
157 dev_err(counter->counter_dev->dev->class_dev,
158 "output commands not yet implemented.\n");
159 return -ENOTSUPP;
160
161 counter->mite_chan->dir = COMEDI_OUTPUT;
162 mite_prep_dma(counter->mite_chan, 32, 32);
163 ni_tio_configure_dma(counter, true, false);
164 mite_dma_arm(counter->mite_chan);
165 return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
166 }
167
ni_tio_cmd_setup(struct comedi_subdevice * s)168 static int ni_tio_cmd_setup(struct comedi_subdevice *s)
169 {
170 struct comedi_cmd *cmd = &s->async->cmd;
171 struct ni_gpct *counter = s->private;
172 unsigned cidx = counter->counter_index;
173 int set_gate_source = 0;
174 unsigned gate_source;
175 int retval = 0;
176
177 if (cmd->scan_begin_src == TRIG_EXT) {
178 set_gate_source = 1;
179 gate_source = cmd->scan_begin_arg;
180 } else if (cmd->convert_src == TRIG_EXT) {
181 set_gate_source = 1;
182 gate_source = cmd->convert_arg;
183 }
184 if (set_gate_source)
185 retval = ni_tio_set_gate_src(counter, 0, gate_source);
186 if (cmd->flags & CMDF_WAKE_EOS) {
187 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
188 GI_GATE_INTERRUPT_ENABLE(cidx),
189 GI_GATE_INTERRUPT_ENABLE(cidx));
190 }
191 return retval;
192 }
193
ni_tio_cmd(struct comedi_device * dev,struct comedi_subdevice * s)194 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
195 {
196 struct ni_gpct *counter = s->private;
197 struct comedi_async *async = s->async;
198 struct comedi_cmd *cmd = &async->cmd;
199 int retval = 0;
200 unsigned long flags;
201
202 spin_lock_irqsave(&counter->lock, flags);
203 if (!counter->mite_chan) {
204 dev_err(counter->counter_dev->dev->class_dev,
205 "commands only supported with DMA. ");
206 dev_err(counter->counter_dev->dev->class_dev,
207 "Interrupt-driven commands not yet implemented.\n");
208 retval = -EIO;
209 } else {
210 retval = ni_tio_cmd_setup(s);
211 if (retval == 0) {
212 if (cmd->flags & CMDF_WRITE)
213 retval = ni_tio_output_cmd(s);
214 else
215 retval = ni_tio_input_cmd(s);
216 }
217 }
218 spin_unlock_irqrestore(&counter->lock, flags);
219 return retval;
220 }
221 EXPORT_SYMBOL_GPL(ni_tio_cmd);
222
ni_tio_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)223 int ni_tio_cmdtest(struct comedi_device *dev,
224 struct comedi_subdevice *s,
225 struct comedi_cmd *cmd)
226 {
227 struct ni_gpct *counter = s->private;
228 int err = 0;
229 unsigned int sources;
230
231 /* Step 1 : check if triggers are trivially valid */
232
233 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
234 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
235 sources |= TRIG_EXT;
236 err |= comedi_check_trigger_src(&cmd->start_src, sources);
237
238 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
239 TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
240 err |= comedi_check_trigger_src(&cmd->convert_src,
241 TRIG_NOW | TRIG_EXT | TRIG_OTHER);
242 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
243 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
244
245 if (err)
246 return 1;
247
248 /* Step 2a : make sure trigger sources are unique */
249
250 err |= comedi_check_trigger_is_unique(cmd->start_src);
251 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
252 err |= comedi_check_trigger_is_unique(cmd->convert_src);
253
254 /* Step 2b : and mutually compatible */
255
256 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
257 err |= -EINVAL;
258
259 if (err)
260 return 2;
261
262 /* Step 3: check if arguments are trivially valid */
263
264 switch (cmd->start_src) {
265 case TRIG_NOW:
266 case TRIG_INT:
267 case TRIG_OTHER:
268 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
269 break;
270 case TRIG_EXT:
271 /* start_arg is the start_trigger passed to ni_tio_arm() */
272 break;
273 }
274
275 if (cmd->scan_begin_src != TRIG_EXT)
276 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
277
278 if (cmd->convert_src != TRIG_EXT)
279 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
280
281 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
282 cmd->chanlist_len);
283 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
284
285 if (err)
286 return 3;
287
288 /* Step 4: fix up any arguments */
289
290 /* Step 5: check channel list if it exists */
291
292 return 0;
293 }
294 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
295
ni_tio_cancel(struct ni_gpct * counter)296 int ni_tio_cancel(struct ni_gpct *counter)
297 {
298 unsigned cidx = counter->counter_index;
299 unsigned long flags;
300
301 ni_tio_arm(counter, 0, 0);
302 spin_lock_irqsave(&counter->lock, flags);
303 if (counter->mite_chan)
304 mite_dma_disarm(counter->mite_chan);
305 spin_unlock_irqrestore(&counter->lock, flags);
306 ni_tio_configure_dma(counter, false, false);
307
308 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
309 GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
310 return 0;
311 }
312 EXPORT_SYMBOL_GPL(ni_tio_cancel);
313
314 /* During buffered input counter operation for e-series, the gate
315 interrupt is acked automatically by the dma controller, due to the
316 Gi_Read/Write_Acknowledges_IRQ bits in the input select register. */
should_ack_gate(struct ni_gpct * counter)317 static int should_ack_gate(struct ni_gpct *counter)
318 {
319 unsigned long flags;
320 int retval = 0;
321
322 switch (counter->counter_dev->variant) {
323 case ni_gpct_variant_m_series:
324 /* not sure if 660x really supports gate
325 interrupts (the bits are not listed
326 in register-level manual) */
327 case ni_gpct_variant_660x:
328 return 1;
329 case ni_gpct_variant_e_series:
330 spin_lock_irqsave(&counter->lock, flags);
331 {
332 if (!counter->mite_chan ||
333 counter->mite_chan->dir != COMEDI_INPUT ||
334 (mite_done(counter->mite_chan))) {
335 retval = 1;
336 }
337 }
338 spin_unlock_irqrestore(&counter->lock, flags);
339 break;
340 }
341 return retval;
342 }
343
ni_tio_acknowledge_and_confirm(struct ni_gpct * counter,int * gate_error,int * tc_error,int * perm_stale_data,int * stale_data)344 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
345 int *gate_error,
346 int *tc_error,
347 int *perm_stale_data,
348 int *stale_data)
349 {
350 unsigned cidx = counter->counter_index;
351 const unsigned short gxx_status = read_register(counter,
352 NITIO_SHARED_STATUS_REG(cidx));
353 const unsigned short gi_status = read_register(counter,
354 NITIO_STATUS_REG(cidx));
355 unsigned ack = 0;
356
357 if (gate_error)
358 *gate_error = 0;
359 if (tc_error)
360 *tc_error = 0;
361 if (perm_stale_data)
362 *perm_stale_data = 0;
363 if (stale_data)
364 *stale_data = 0;
365
366 if (gxx_status & GI_GATE_ERROR(cidx)) {
367 ack |= GI_GATE_ERROR_CONFIRM(cidx);
368 if (gate_error) {
369 /*660x don't support automatic acknowledgment
370 of gate interrupt via dma read/write
371 and report bogus gate errors */
372 if (counter->counter_dev->variant !=
373 ni_gpct_variant_660x)
374 *gate_error = 1;
375 }
376 }
377 if (gxx_status & GI_TC_ERROR(cidx)) {
378 ack |= GI_TC_ERROR_CONFIRM(cidx);
379 if (tc_error)
380 *tc_error = 1;
381 }
382 if (gi_status & GI_TC)
383 ack |= GI_TC_INTERRUPT_ACK;
384 if (gi_status & GI_GATE_INTERRUPT) {
385 if (should_ack_gate(counter))
386 ack |= GI_GATE_INTERRUPT_ACK;
387 }
388 if (ack)
389 write_register(counter, ack, NITIO_INT_ACK_REG(cidx));
390 if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
391 GI_LOADING_ON_GATE) {
392 if (gxx_status & GI_STALE_DATA(cidx)) {
393 if (stale_data)
394 *stale_data = 1;
395 }
396 if (read_register(counter, NITIO_STATUS2_REG(cidx)) &
397 GI_PERMANENT_STALE(cidx)) {
398 dev_info(counter->counter_dev->dev->class_dev,
399 "%s: Gi_Permanent_Stale_Data detected.\n",
400 __func__);
401 if (perm_stale_data)
402 *perm_stale_data = 1;
403 }
404 }
405 }
406
ni_tio_acknowledge(struct ni_gpct * counter)407 void ni_tio_acknowledge(struct ni_gpct *counter)
408 {
409 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
410 }
411 EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
412
ni_tio_handle_interrupt(struct ni_gpct * counter,struct comedi_subdevice * s)413 void ni_tio_handle_interrupt(struct ni_gpct *counter,
414 struct comedi_subdevice *s)
415 {
416 unsigned cidx = counter->counter_index;
417 unsigned gpct_mite_status;
418 unsigned long flags;
419 int gate_error;
420 int tc_error;
421 int perm_stale_data;
422
423 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
424 &perm_stale_data, NULL);
425 if (gate_error) {
426 dev_notice(counter->counter_dev->dev->class_dev,
427 "%s: Gi_Gate_Error detected.\n", __func__);
428 s->async->events |= COMEDI_CB_OVERFLOW;
429 }
430 if (perm_stale_data)
431 s->async->events |= COMEDI_CB_ERROR;
432 switch (counter->counter_dev->variant) {
433 case ni_gpct_variant_m_series:
434 case ni_gpct_variant_660x:
435 if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) &
436 GI_DRQ_ERROR) {
437 dev_notice(counter->counter_dev->dev->class_dev,
438 "%s: Gi_DRQ_Error detected.\n", __func__);
439 s->async->events |= COMEDI_CB_OVERFLOW;
440 }
441 break;
442 case ni_gpct_variant_e_series:
443 break;
444 }
445 spin_lock_irqsave(&counter->lock, flags);
446 if (!counter->mite_chan) {
447 spin_unlock_irqrestore(&counter->lock, flags);
448 return;
449 }
450 gpct_mite_status = mite_get_status(counter->mite_chan);
451 if (gpct_mite_status & CHSR_LINKC)
452 writel(CHOR_CLRLC,
453 counter->mite_chan->mite->mite_io_addr +
454 MITE_CHOR(counter->mite_chan->channel));
455 mite_sync_input_dma(counter->mite_chan, s);
456 spin_unlock_irqrestore(&counter->lock, flags);
457 }
458 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
459
ni_tio_set_mite_channel(struct ni_gpct * counter,struct mite_channel * mite_chan)460 void ni_tio_set_mite_channel(struct ni_gpct *counter,
461 struct mite_channel *mite_chan)
462 {
463 unsigned long flags;
464
465 spin_lock_irqsave(&counter->lock, flags);
466 counter->mite_chan = mite_chan;
467 spin_unlock_irqrestore(&counter->lock, flags);
468 }
469 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
470
ni_tiocmd_init_module(void)471 static int __init ni_tiocmd_init_module(void)
472 {
473 return 0;
474 }
475 module_init(ni_tiocmd_init_module);
476
ni_tiocmd_cleanup_module(void)477 static void __exit ni_tiocmd_cleanup_module(void)
478 {
479 }
480 module_exit(ni_tiocmd_cleanup_module);
481
482 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
483 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
484 MODULE_LICENSE("GPL");
485