1 /*
2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
5 *
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
8 *
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
11 *
12 * Credits:
13 * David Woodhouse for adding multichip support
14 *
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
18 * TODO:
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/mm.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
46 #include <linux/leds.h>
47 #include <linux/io.h>
48 #include <linux/mtd/partitions.h>
49 #include <linux/of_mtd.h>
50
51 /* Define default oob placement schemes for large and small page devices */
52 static struct nand_ecclayout nand_oob_8 = {
53 .eccbytes = 3,
54 .eccpos = {0, 1, 2},
55 .oobfree = {
56 {.offset = 3,
57 .length = 2},
58 {.offset = 6,
59 .length = 2} }
60 };
61
62 static struct nand_ecclayout nand_oob_16 = {
63 .eccbytes = 6,
64 .eccpos = {0, 1, 2, 3, 6, 7},
65 .oobfree = {
66 {.offset = 8,
67 . length = 8} }
68 };
69
70 static struct nand_ecclayout nand_oob_64 = {
71 .eccbytes = 24,
72 .eccpos = {
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
76 .oobfree = {
77 {.offset = 2,
78 .length = 38} }
79 };
80
81 static struct nand_ecclayout nand_oob_128 = {
82 .eccbytes = 48,
83 .eccpos = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
90 .oobfree = {
91 {.offset = 2,
92 .length = 78} }
93 };
94
95 static int nand_get_device(struct mtd_info *mtd, int new_state);
96
97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
99
100 /*
101 * For devices which display every fart in the system on a separate LED. Is
102 * compiled away when LED support is disabled.
103 */
104 DEFINE_LED_TRIGGER(nand_led_trigger);
105
check_offs_len(struct mtd_info * mtd,loff_t ofs,uint64_t len)106 static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
108 {
109 struct nand_chip *chip = mtd->priv;
110 int ret = 0;
111
112 /* Start address must align on block boundary */
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
114 pr_debug("%s: unaligned address\n", __func__);
115 ret = -EINVAL;
116 }
117
118 /* Length must align on block boundary */
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
120 pr_debug("%s: length not block aligned\n", __func__);
121 ret = -EINVAL;
122 }
123
124 return ret;
125 }
126
127 /**
128 * nand_release_device - [GENERIC] release chip
129 * @mtd: MTD device structure
130 *
131 * Release chip lock and wake up anyone waiting on the device.
132 */
nand_release_device(struct mtd_info * mtd)133 static void nand_release_device(struct mtd_info *mtd)
134 {
135 struct nand_chip *chip = mtd->priv;
136
137 /* Release the controller and the chip */
138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
143 }
144
145 /**
146 * nand_read_byte - [DEFAULT] read one byte from the chip
147 * @mtd: MTD device structure
148 *
149 * Default read function for 8bit buswidth
150 */
nand_read_byte(struct mtd_info * mtd)151 static uint8_t nand_read_byte(struct mtd_info *mtd)
152 {
153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
155 }
156
157 /**
158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
159 * @mtd: MTD device structure
160 *
161 * Default read function for 16bit buswidth with endianness conversion.
162 *
163 */
nand_read_byte16(struct mtd_info * mtd)164 static uint8_t nand_read_byte16(struct mtd_info *mtd)
165 {
166 struct nand_chip *chip = mtd->priv;
167 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
168 }
169
170 /**
171 * nand_read_word - [DEFAULT] read one word from the chip
172 * @mtd: MTD device structure
173 *
174 * Default read function for 16bit buswidth without endianness conversion.
175 */
nand_read_word(struct mtd_info * mtd)176 static u16 nand_read_word(struct mtd_info *mtd)
177 {
178 struct nand_chip *chip = mtd->priv;
179 return readw(chip->IO_ADDR_R);
180 }
181
182 /**
183 * nand_select_chip - [DEFAULT] control CE line
184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
186 *
187 * Default select function for 1 chip devices.
188 */
nand_select_chip(struct mtd_info * mtd,int chipnr)189 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
190 {
191 struct nand_chip *chip = mtd->priv;
192
193 switch (chipnr) {
194 case -1:
195 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
196 break;
197 case 0:
198 break;
199
200 default:
201 BUG();
202 }
203 }
204
205 /**
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
209 *
210 * Default function to write a byte to I/O[7:0]
211 */
nand_write_byte(struct mtd_info * mtd,uint8_t byte)212 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
213 {
214 struct nand_chip *chip = mtd->priv;
215
216 chip->write_buf(mtd, &byte, 1);
217 }
218
219 /**
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
223 *
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
225 */
nand_write_byte16(struct mtd_info * mtd,uint8_t byte)226 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
227 {
228 struct nand_chip *chip = mtd->priv;
229 uint16_t word = byte;
230
231 /*
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
234 *
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
241 *
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
246 */
247 chip->write_buf(mtd, (uint8_t *)&word, 2);
248 }
249
250 /**
251 * nand_write_buf - [DEFAULT] write buffer to chip
252 * @mtd: MTD device structure
253 * @buf: data buffer
254 * @len: number of bytes to write
255 *
256 * Default write function for 8bit buswidth.
257 */
nand_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)258 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
259 {
260 struct nand_chip *chip = mtd->priv;
261
262 iowrite8_rep(chip->IO_ADDR_W, buf, len);
263 }
264
265 /**
266 * nand_read_buf - [DEFAULT] read chip data into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
270 *
271 * Default read function for 8bit buswidth.
272 */
nand_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)273 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
274 {
275 struct nand_chip *chip = mtd->priv;
276
277 ioread8_rep(chip->IO_ADDR_R, buf, len);
278 }
279
280 /**
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
283 * @buf: data buffer
284 * @len: number of bytes to write
285 *
286 * Default write function for 16bit buswidth.
287 */
nand_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)288 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
289 {
290 struct nand_chip *chip = mtd->priv;
291 u16 *p = (u16 *) buf;
292
293 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
294 }
295
296 /**
297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
301 *
302 * Default read function for 16bit buswidth.
303 */
nand_read_buf16(struct mtd_info * mtd,uint8_t * buf,int len)304 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
305 {
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
308
309 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
310 }
311
312 /**
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
317 *
318 * Check, if the block is bad.
319 */
nand_block_bad(struct mtd_info * mtd,loff_t ofs,int getchip)320 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
321 {
322 int page, chipnr, res = 0, i = 0;
323 struct nand_chip *chip = mtd->priv;
324 u16 bad;
325
326 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
327 ofs += mtd->erasesize - mtd->writesize;
328
329 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
330
331 if (getchip) {
332 chipnr = (int)(ofs >> chip->chip_shift);
333
334 nand_get_device(mtd, FL_READING);
335
336 /* Select the NAND device */
337 chip->select_chip(mtd, chipnr);
338 }
339
340 do {
341 if (chip->options & NAND_BUSWIDTH_16) {
342 chip->cmdfunc(mtd, NAND_CMD_READOOB,
343 chip->badblockpos & 0xFE, page);
344 bad = cpu_to_le16(chip->read_word(mtd));
345 if (chip->badblockpos & 0x1)
346 bad >>= 8;
347 else
348 bad &= 0xFF;
349 } else {
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
351 page);
352 bad = chip->read_byte(mtd);
353 }
354
355 if (likely(chip->badblockbits == 8))
356 res = bad != 0xFF;
357 else
358 res = hweight8(bad) < chip->badblockbits;
359 ofs += mtd->writesize;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
361 i++;
362 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
363
364 if (getchip) {
365 chip->select_chip(mtd, -1);
366 nand_release_device(mtd);
367 }
368
369 return res;
370 }
371
372 /**
373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
374 * @mtd: MTD device structure
375 * @ofs: offset from device start
376 *
377 * This is the default implementation, which can be overridden by a hardware
378 * specific driver. It provides the details for writing a bad block marker to a
379 * block.
380 */
nand_default_block_markbad(struct mtd_info * mtd,loff_t ofs)381 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
382 {
383 struct nand_chip *chip = mtd->priv;
384 struct mtd_oob_ops ops;
385 uint8_t buf[2] = { 0, 0 };
386 int ret = 0, res, i = 0;
387
388 memset(&ops, 0, sizeof(ops));
389 ops.oobbuf = buf;
390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
394 } else {
395 ops.len = ops.ooblen = 1;
396 }
397 ops.mode = MTD_OPS_PLACE_OOB;
398
399 /* Write to first/last page(s) if necessary */
400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 ofs += mtd->erasesize - mtd->writesize;
402 do {
403 res = nand_do_write_oob(mtd, ofs, &ops);
404 if (!ret)
405 ret = res;
406
407 i++;
408 ofs += mtd->writesize;
409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
410
411 return ret;
412 }
413
414 /**
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
418 *
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
422 *
423 * We try operations in the following order:
424 * (1) erase the affected block, to allow OOB marker to be written cleanly
425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
427 * (3) update the BBT
428 * Note that we retain the first error encountered in (2) or (3), finish the
429 * procedures, and dump the error in the end.
430 */
nand_block_markbad_lowlevel(struct mtd_info * mtd,loff_t ofs)431 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
432 {
433 struct nand_chip *chip = mtd->priv;
434 int res, ret = 0;
435
436 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
437 struct erase_info einfo;
438
439 /* Attempt erase before marking OOB */
440 memset(&einfo, 0, sizeof(einfo));
441 einfo.mtd = mtd;
442 einfo.addr = ofs;
443 einfo.len = 1ULL << chip->phys_erase_shift;
444 nand_erase_nand(mtd, &einfo, 0);
445
446 /* Write bad block marker to OOB */
447 nand_get_device(mtd, FL_WRITING);
448 ret = chip->block_markbad(mtd, ofs);
449 nand_release_device(mtd);
450 }
451
452 /* Mark block bad in BBT */
453 if (chip->bbt) {
454 res = nand_markbad_bbt(mtd, ofs);
455 if (!ret)
456 ret = res;
457 }
458
459 if (!ret)
460 mtd->ecc_stats.badblocks++;
461
462 return ret;
463 }
464
465 /**
466 * nand_check_wp - [GENERIC] check if the chip is write protected
467 * @mtd: MTD device structure
468 *
469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
471 */
nand_check_wp(struct mtd_info * mtd)472 static int nand_check_wp(struct mtd_info *mtd)
473 {
474 struct nand_chip *chip = mtd->priv;
475
476 /* Broken xD cards report WP despite being writable */
477 if (chip->options & NAND_BROKEN_XD)
478 return 0;
479
480 /* Check the WP bit */
481 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
482 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
483 }
484
485 /**
486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
487 * @mtd: MTD device structure
488 * @ofs: offset from device start
489 *
490 * Check if the block is marked as reserved.
491 */
nand_block_isreserved(struct mtd_info * mtd,loff_t ofs)492 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
493 {
494 struct nand_chip *chip = mtd->priv;
495
496 if (!chip->bbt)
497 return 0;
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd, ofs);
500 }
501
502 /**
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
508 *
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
511 */
nand_block_checkbad(struct mtd_info * mtd,loff_t ofs,int getchip,int allowbbt)512 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
513 int allowbbt)
514 {
515 struct nand_chip *chip = mtd->priv;
516
517 if (!chip->bbt)
518 return chip->block_bad(mtd, ofs, getchip);
519
520 /* Return info from the table */
521 return nand_isbad_bbt(mtd, ofs, allowbbt);
522 }
523
524 /**
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
526 * @mtd: MTD device structure
527 * @timeo: Timeout
528 *
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
530 * context.
531 */
panic_nand_wait_ready(struct mtd_info * mtd,unsigned long timeo)532 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
533 {
534 struct nand_chip *chip = mtd->priv;
535 int i;
536
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
540 break;
541 touch_softlockup_watchdog();
542 mdelay(1);
543 }
544 }
545
546 /**
547 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
548 * @mtd: MTD device structure
549 *
550 * Wait for the ready pin after a command, and warn if a timeout occurs.
551 */
nand_wait_ready(struct mtd_info * mtd)552 void nand_wait_ready(struct mtd_info *mtd)
553 {
554 struct nand_chip *chip = mtd->priv;
555 unsigned long timeo = 400;
556
557 if (in_interrupt() || oops_in_progress)
558 return panic_nand_wait_ready(mtd, timeo);
559
560 led_trigger_event(nand_led_trigger, LED_FULL);
561 /* Wait until command is processed or timeout occurs */
562 timeo = jiffies + msecs_to_jiffies(timeo);
563 do {
564 if (chip->dev_ready(mtd))
565 goto out;
566 cond_resched();
567 } while (time_before(jiffies, timeo));
568
569 pr_warn_ratelimited(
570 "timeout while waiting for chip to become ready\n");
571 out:
572 led_trigger_event(nand_led_trigger, LED_OFF);
573 }
574 EXPORT_SYMBOL_GPL(nand_wait_ready);
575
576 /**
577 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
578 * @mtd: MTD device structure
579 * @timeo: Timeout in ms
580 *
581 * Wait for status ready (i.e. command done) or timeout.
582 */
nand_wait_status_ready(struct mtd_info * mtd,unsigned long timeo)583 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
584 {
585 register struct nand_chip *chip = mtd->priv;
586
587 timeo = jiffies + msecs_to_jiffies(timeo);
588 do {
589 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
590 break;
591 touch_softlockup_watchdog();
592 } while (time_before(jiffies, timeo));
593 };
594
595 /**
596 * nand_command - [DEFAULT] Send command to NAND device
597 * @mtd: MTD device structure
598 * @command: the command to be sent
599 * @column: the column address for this command, -1 if none
600 * @page_addr: the page address for this command, -1 if none
601 *
602 * Send command to NAND device. This function is used for small page devices
603 * (512 Bytes per page).
604 */
nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)605 static void nand_command(struct mtd_info *mtd, unsigned int command,
606 int column, int page_addr)
607 {
608 register struct nand_chip *chip = mtd->priv;
609 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
610
611 /* Write out the command to the device */
612 if (command == NAND_CMD_SEQIN) {
613 int readcmd;
614
615 if (column >= mtd->writesize) {
616 /* OOB area */
617 column -= mtd->writesize;
618 readcmd = NAND_CMD_READOOB;
619 } else if (column < 256) {
620 /* First 256 bytes --> READ0 */
621 readcmd = NAND_CMD_READ0;
622 } else {
623 column -= 256;
624 readcmd = NAND_CMD_READ1;
625 }
626 chip->cmd_ctrl(mtd, readcmd, ctrl);
627 ctrl &= ~NAND_CTRL_CHANGE;
628 }
629 chip->cmd_ctrl(mtd, command, ctrl);
630
631 /* Address cycle, when necessary */
632 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
633 /* Serially input address */
634 if (column != -1) {
635 /* Adjust columns for 16 bit buswidth */
636 if (chip->options & NAND_BUSWIDTH_16 &&
637 !nand_opcode_8bits(command))
638 column >>= 1;
639 chip->cmd_ctrl(mtd, column, ctrl);
640 ctrl &= ~NAND_CTRL_CHANGE;
641 }
642 if (page_addr != -1) {
643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 ctrl &= ~NAND_CTRL_CHANGE;
645 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
646 /* One more address cycle for devices > 32MiB */
647 if (chip->chipsize > (32 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
649 }
650 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
651
652 /*
653 * Program and erase have their own busy handlers status and sequential
654 * in needs no delay
655 */
656 switch (command) {
657
658 case NAND_CMD_PAGEPROG:
659 case NAND_CMD_ERASE1:
660 case NAND_CMD_ERASE2:
661 case NAND_CMD_SEQIN:
662 case NAND_CMD_STATUS:
663 return;
664
665 case NAND_CMD_RESET:
666 if (chip->dev_ready)
667 break;
668 udelay(chip->chip_delay);
669 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
670 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
671 chip->cmd_ctrl(mtd,
672 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
673 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
674 nand_wait_status_ready(mtd, 250);
675 return;
676
677 /* This applies to read commands */
678 default:
679 /*
680 * If we don't have access to the busy pin, we apply the given
681 * command delay
682 */
683 if (!chip->dev_ready) {
684 udelay(chip->chip_delay);
685 return;
686 }
687 }
688 /*
689 * Apply this short delay always to ensure that we do wait tWB in
690 * any case on any machine.
691 */
692 ndelay(100);
693
694 nand_wait_ready(mtd);
695 }
696
697 /**
698 * nand_command_lp - [DEFAULT] Send command to NAND large page device
699 * @mtd: MTD device structure
700 * @command: the command to be sent
701 * @column: the column address for this command, -1 if none
702 * @page_addr: the page address for this command, -1 if none
703 *
704 * Send command to NAND device. This is the version for the new large page
705 * devices. We don't have the separate regions as we have in the small page
706 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
707 */
nand_command_lp(struct mtd_info * mtd,unsigned int command,int column,int page_addr)708 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
709 int column, int page_addr)
710 {
711 register struct nand_chip *chip = mtd->priv;
712
713 /* Emulate NAND_CMD_READOOB */
714 if (command == NAND_CMD_READOOB) {
715 column += mtd->writesize;
716 command = NAND_CMD_READ0;
717 }
718
719 /* Command latch cycle */
720 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
721
722 if (column != -1 || page_addr != -1) {
723 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
724
725 /* Serially input address */
726 if (column != -1) {
727 /* Adjust columns for 16 bit buswidth */
728 if (chip->options & NAND_BUSWIDTH_16 &&
729 !nand_opcode_8bits(command))
730 column >>= 1;
731 chip->cmd_ctrl(mtd, column, ctrl);
732 ctrl &= ~NAND_CTRL_CHANGE;
733 chip->cmd_ctrl(mtd, column >> 8, ctrl);
734 }
735 if (page_addr != -1) {
736 chip->cmd_ctrl(mtd, page_addr, ctrl);
737 chip->cmd_ctrl(mtd, page_addr >> 8,
738 NAND_NCE | NAND_ALE);
739 /* One more address cycle for devices > 128MiB */
740 if (chip->chipsize > (128 << 20))
741 chip->cmd_ctrl(mtd, page_addr >> 16,
742 NAND_NCE | NAND_ALE);
743 }
744 }
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
746
747 /*
748 * Program and erase have their own busy handlers status, sequential
749 * in and status need no delay.
750 */
751 switch (command) {
752
753 case NAND_CMD_CACHEDPROG:
754 case NAND_CMD_PAGEPROG:
755 case NAND_CMD_ERASE1:
756 case NAND_CMD_ERASE2:
757 case NAND_CMD_SEQIN:
758 case NAND_CMD_RNDIN:
759 case NAND_CMD_STATUS:
760 return;
761
762 case NAND_CMD_RESET:
763 if (chip->dev_ready)
764 break;
765 udelay(chip->chip_delay);
766 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
767 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
768 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
769 NAND_NCE | NAND_CTRL_CHANGE);
770 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
771 nand_wait_status_ready(mtd, 250);
772 return;
773
774 case NAND_CMD_RNDOUT:
775 /* No ready / busy check necessary */
776 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
777 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
779 NAND_NCE | NAND_CTRL_CHANGE);
780 return;
781
782 case NAND_CMD_READ0:
783 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
784 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
785 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
786 NAND_NCE | NAND_CTRL_CHANGE);
787
788 /* This applies to read commands */
789 default:
790 /*
791 * If we don't have access to the busy pin, we apply the given
792 * command delay.
793 */
794 if (!chip->dev_ready) {
795 udelay(chip->chip_delay);
796 return;
797 }
798 }
799
800 /*
801 * Apply this short delay always to ensure that we do wait tWB in
802 * any case on any machine.
803 */
804 ndelay(100);
805
806 nand_wait_ready(mtd);
807 }
808
809 /**
810 * panic_nand_get_device - [GENERIC] Get chip for selected access
811 * @chip: the nand chip descriptor
812 * @mtd: MTD device structure
813 * @new_state: the state which is requested
814 *
815 * Used when in panic, no locks are taken.
816 */
panic_nand_get_device(struct nand_chip * chip,struct mtd_info * mtd,int new_state)817 static void panic_nand_get_device(struct nand_chip *chip,
818 struct mtd_info *mtd, int new_state)
819 {
820 /* Hardware controller shared among independent devices */
821 chip->controller->active = chip;
822 chip->state = new_state;
823 }
824
825 /**
826 * nand_get_device - [GENERIC] Get chip for selected access
827 * @mtd: MTD device structure
828 * @new_state: the state which is requested
829 *
830 * Get the device and lock it for exclusive access
831 */
832 static int
nand_get_device(struct mtd_info * mtd,int new_state)833 nand_get_device(struct mtd_info *mtd, int new_state)
834 {
835 struct nand_chip *chip = mtd->priv;
836 spinlock_t *lock = &chip->controller->lock;
837 wait_queue_head_t *wq = &chip->controller->wq;
838 DECLARE_WAITQUEUE(wait, current);
839 retry:
840 spin_lock(lock);
841
842 /* Hardware controller shared among independent devices */
843 if (!chip->controller->active)
844 chip->controller->active = chip;
845
846 if (chip->controller->active == chip && chip->state == FL_READY) {
847 chip->state = new_state;
848 spin_unlock(lock);
849 return 0;
850 }
851 if (new_state == FL_PM_SUSPENDED) {
852 if (chip->controller->active->state == FL_PM_SUSPENDED) {
853 chip->state = FL_PM_SUSPENDED;
854 spin_unlock(lock);
855 return 0;
856 }
857 }
858 set_current_state(TASK_UNINTERRUPTIBLE);
859 add_wait_queue(wq, &wait);
860 spin_unlock(lock);
861 schedule();
862 remove_wait_queue(wq, &wait);
863 goto retry;
864 }
865
866 /**
867 * panic_nand_wait - [GENERIC] wait until the command is done
868 * @mtd: MTD device structure
869 * @chip: NAND chip structure
870 * @timeo: timeout
871 *
872 * Wait for command done. This is a helper function for nand_wait used when
873 * we are in interrupt context. May happen when in panic and trying to write
874 * an oops through mtdoops.
875 */
panic_nand_wait(struct mtd_info * mtd,struct nand_chip * chip,unsigned long timeo)876 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
877 unsigned long timeo)
878 {
879 int i;
880 for (i = 0; i < timeo; i++) {
881 if (chip->dev_ready) {
882 if (chip->dev_ready(mtd))
883 break;
884 } else {
885 if (chip->read_byte(mtd) & NAND_STATUS_READY)
886 break;
887 }
888 mdelay(1);
889 }
890 }
891
892 /**
893 * nand_wait - [DEFAULT] wait until the command is done
894 * @mtd: MTD device structure
895 * @chip: NAND chip structure
896 *
897 * Wait for command done. This applies to erase and program only.
898 */
nand_wait(struct mtd_info * mtd,struct nand_chip * chip)899 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
900 {
901
902 int status;
903 unsigned long timeo = 400;
904
905 led_trigger_event(nand_led_trigger, LED_FULL);
906
907 /*
908 * Apply this short delay always to ensure that we do wait tWB in any
909 * case on any machine.
910 */
911 ndelay(100);
912
913 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
914
915 if (in_interrupt() || oops_in_progress)
916 panic_nand_wait(mtd, chip, timeo);
917 else {
918 timeo = jiffies + msecs_to_jiffies(timeo);
919 do {
920 if (chip->dev_ready) {
921 if (chip->dev_ready(mtd))
922 break;
923 } else {
924 if (chip->read_byte(mtd) & NAND_STATUS_READY)
925 break;
926 }
927 cond_resched();
928 } while (time_before(jiffies, timeo));
929 }
930 led_trigger_event(nand_led_trigger, LED_OFF);
931
932 status = (int)chip->read_byte(mtd);
933 /* This can happen if in case of timeout or buggy dev_ready */
934 WARN_ON(!(status & NAND_STATUS_READY));
935 return status;
936 }
937
938 /**
939 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
940 * @mtd: mtd info
941 * @ofs: offset to start unlock from
942 * @len: length to unlock
943 * @invert: when = 0, unlock the range of blocks within the lower and
944 * upper boundary address
945 * when = 1, unlock the range of blocks outside the boundaries
946 * of the lower and upper boundary address
947 *
948 * Returs unlock status.
949 */
__nand_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len,int invert)950 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
951 uint64_t len, int invert)
952 {
953 int ret = 0;
954 int status, page;
955 struct nand_chip *chip = mtd->priv;
956
957 /* Submit address of first page to unlock */
958 page = ofs >> chip->page_shift;
959 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
960
961 /* Submit address of last page to unlock */
962 page = (ofs + len) >> chip->page_shift;
963 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
964 (page | invert) & chip->pagemask);
965
966 /* Call wait ready function */
967 status = chip->waitfunc(mtd, chip);
968 /* See if device thinks it succeeded */
969 if (status & NAND_STATUS_FAIL) {
970 pr_debug("%s: error status = 0x%08x\n",
971 __func__, status);
972 ret = -EIO;
973 }
974
975 return ret;
976 }
977
978 /**
979 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
980 * @mtd: mtd info
981 * @ofs: offset to start unlock from
982 * @len: length to unlock
983 *
984 * Returns unlock status.
985 */
nand_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)986 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
987 {
988 int ret = 0;
989 int chipnr;
990 struct nand_chip *chip = mtd->priv;
991
992 pr_debug("%s: start = 0x%012llx, len = %llu\n",
993 __func__, (unsigned long long)ofs, len);
994
995 if (check_offs_len(mtd, ofs, len))
996 return -EINVAL;
997
998 /* Align to last block address if size addresses end of the device */
999 if (ofs + len == mtd->size)
1000 len -= mtd->erasesize;
1001
1002 nand_get_device(mtd, FL_UNLOCKING);
1003
1004 /* Shift to get chip number */
1005 chipnr = ofs >> chip->chip_shift;
1006
1007 chip->select_chip(mtd, chipnr);
1008
1009 /*
1010 * Reset the chip.
1011 * If we want to check the WP through READ STATUS and check the bit 7
1012 * we must reset the chip
1013 * some operation can also clear the bit 7 of status register
1014 * eg. erase/program a locked block
1015 */
1016 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1017
1018 /* Check, if it is write protected */
1019 if (nand_check_wp(mtd)) {
1020 pr_debug("%s: device is write protected!\n",
1021 __func__);
1022 ret = -EIO;
1023 goto out;
1024 }
1025
1026 ret = __nand_unlock(mtd, ofs, len, 0);
1027
1028 out:
1029 chip->select_chip(mtd, -1);
1030 nand_release_device(mtd);
1031
1032 return ret;
1033 }
1034 EXPORT_SYMBOL(nand_unlock);
1035
1036 /**
1037 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1038 * @mtd: mtd info
1039 * @ofs: offset to start unlock from
1040 * @len: length to unlock
1041 *
1042 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1043 * have this feature, but it allows only to lock all blocks, not for specified
1044 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1045 * now.
1046 *
1047 * Returns lock status.
1048 */
nand_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)1049 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1050 {
1051 int ret = 0;
1052 int chipnr, status, page;
1053 struct nand_chip *chip = mtd->priv;
1054
1055 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1056 __func__, (unsigned long long)ofs, len);
1057
1058 if (check_offs_len(mtd, ofs, len))
1059 return -EINVAL;
1060
1061 nand_get_device(mtd, FL_LOCKING);
1062
1063 /* Shift to get chip number */
1064 chipnr = ofs >> chip->chip_shift;
1065
1066 chip->select_chip(mtd, chipnr);
1067
1068 /*
1069 * Reset the chip.
1070 * If we want to check the WP through READ STATUS and check the bit 7
1071 * we must reset the chip
1072 * some operation can also clear the bit 7 of status register
1073 * eg. erase/program a locked block
1074 */
1075 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1076
1077 /* Check, if it is write protected */
1078 if (nand_check_wp(mtd)) {
1079 pr_debug("%s: device is write protected!\n",
1080 __func__);
1081 status = MTD_ERASE_FAILED;
1082 ret = -EIO;
1083 goto out;
1084 }
1085
1086 /* Submit address of first page to lock */
1087 page = ofs >> chip->page_shift;
1088 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1089
1090 /* Call wait ready function */
1091 status = chip->waitfunc(mtd, chip);
1092 /* See if device thinks it succeeded */
1093 if (status & NAND_STATUS_FAIL) {
1094 pr_debug("%s: error status = 0x%08x\n",
1095 __func__, status);
1096 ret = -EIO;
1097 goto out;
1098 }
1099
1100 ret = __nand_unlock(mtd, ofs, len, 0x1);
1101
1102 out:
1103 chip->select_chip(mtd, -1);
1104 nand_release_device(mtd);
1105
1106 return ret;
1107 }
1108 EXPORT_SYMBOL(nand_lock);
1109
1110 /**
1111 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1112 * @buf: buffer to test
1113 * @len: buffer length
1114 * @bitflips_threshold: maximum number of bitflips
1115 *
1116 * Check if a buffer contains only 0xff, which means the underlying region
1117 * has been erased and is ready to be programmed.
1118 * The bitflips_threshold specify the maximum number of bitflips before
1119 * considering the region is not erased.
1120 * Note: The logic of this function has been extracted from the memweight
1121 * implementation, except that nand_check_erased_buf function exit before
1122 * testing the whole buffer if the number of bitflips exceed the
1123 * bitflips_threshold value.
1124 *
1125 * Returns a positive number of bitflips less than or equal to
1126 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1127 * threshold.
1128 */
nand_check_erased_buf(void * buf,int len,int bitflips_threshold)1129 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1130 {
1131 const unsigned char *bitmap = buf;
1132 int bitflips = 0;
1133 int weight;
1134
1135 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1136 len--, bitmap++) {
1137 weight = hweight8(*bitmap);
1138 bitflips += BITS_PER_BYTE - weight;
1139 if (unlikely(bitflips > bitflips_threshold))
1140 return -EBADMSG;
1141 }
1142
1143 for (; len >= sizeof(long);
1144 len -= sizeof(long), bitmap += sizeof(long)) {
1145 weight = hweight_long(*((unsigned long *)bitmap));
1146 bitflips += BITS_PER_LONG - weight;
1147 if (unlikely(bitflips > bitflips_threshold))
1148 return -EBADMSG;
1149 }
1150
1151 for (; len > 0; len--, bitmap++) {
1152 weight = hweight8(*bitmap);
1153 bitflips += BITS_PER_BYTE - weight;
1154 if (unlikely(bitflips > bitflips_threshold))
1155 return -EBADMSG;
1156 }
1157
1158 return bitflips;
1159 }
1160
1161 /**
1162 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1163 * 0xff data
1164 * @data: data buffer to test
1165 * @datalen: data length
1166 * @ecc: ECC buffer
1167 * @ecclen: ECC length
1168 * @extraoob: extra OOB buffer
1169 * @extraooblen: extra OOB length
1170 * @bitflips_threshold: maximum number of bitflips
1171 *
1172 * Check if a data buffer and its associated ECC and OOB data contains only
1173 * 0xff pattern, which means the underlying region has been erased and is
1174 * ready to be programmed.
1175 * The bitflips_threshold specify the maximum number of bitflips before
1176 * considering the region as not erased.
1177 *
1178 * Note:
1179 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1180 * different from the NAND page size. When fixing bitflips, ECC engines will
1181 * report the number of errors per chunk, and the NAND core infrastructure
1182 * expect you to return the maximum number of bitflips for the whole page.
1183 * This is why you should always use this function on a single chunk and
1184 * not on the whole page. After checking each chunk you should update your
1185 * max_bitflips value accordingly.
1186 * 2/ When checking for bitflips in erased pages you should not only check
1187 * the payload data but also their associated ECC data, because a user might
1188 * have programmed almost all bits to 1 but a few. In this case, we
1189 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1190 * this case.
1191 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1192 * data are protected by the ECC engine.
1193 * It could also be used if you support subpages and want to attach some
1194 * extra OOB data to an ECC chunk.
1195 *
1196 * Returns a positive number of bitflips less than or equal to
1197 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1198 * threshold. In case of success, the passed buffers are filled with 0xff.
1199 */
nand_check_erased_ecc_chunk(void * data,int datalen,void * ecc,int ecclen,void * extraoob,int extraooblen,int bitflips_threshold)1200 int nand_check_erased_ecc_chunk(void *data, int datalen,
1201 void *ecc, int ecclen,
1202 void *extraoob, int extraooblen,
1203 int bitflips_threshold)
1204 {
1205 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1206
1207 data_bitflips = nand_check_erased_buf(data, datalen,
1208 bitflips_threshold);
1209 if (data_bitflips < 0)
1210 return data_bitflips;
1211
1212 bitflips_threshold -= data_bitflips;
1213
1214 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1215 if (ecc_bitflips < 0)
1216 return ecc_bitflips;
1217
1218 bitflips_threshold -= ecc_bitflips;
1219
1220 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1221 bitflips_threshold);
1222 if (extraoob_bitflips < 0)
1223 return extraoob_bitflips;
1224
1225 if (data_bitflips)
1226 memset(data, 0xff, datalen);
1227
1228 if (ecc_bitflips)
1229 memset(ecc, 0xff, ecclen);
1230
1231 if (extraoob_bitflips)
1232 memset(extraoob, 0xff, extraooblen);
1233
1234 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1235 }
1236 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1237
1238 /**
1239 * nand_read_page_raw - [INTERN] read raw page data without ecc
1240 * @mtd: mtd info structure
1241 * @chip: nand chip info structure
1242 * @buf: buffer to store read data
1243 * @oob_required: caller requires OOB data read to chip->oob_poi
1244 * @page: page number to read
1245 *
1246 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1247 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1248 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1249 uint8_t *buf, int oob_required, int page)
1250 {
1251 chip->read_buf(mtd, buf, mtd->writesize);
1252 if (oob_required)
1253 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1254 return 0;
1255 }
1256
1257 /**
1258 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1259 * @mtd: mtd info structure
1260 * @chip: nand chip info structure
1261 * @buf: buffer to store read data
1262 * @oob_required: caller requires OOB data read to chip->oob_poi
1263 * @page: page number to read
1264 *
1265 * We need a special oob layout and handling even when OOB isn't used.
1266 */
nand_read_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1267 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1268 struct nand_chip *chip, uint8_t *buf,
1269 int oob_required, int page)
1270 {
1271 int eccsize = chip->ecc.size;
1272 int eccbytes = chip->ecc.bytes;
1273 uint8_t *oob = chip->oob_poi;
1274 int steps, size;
1275
1276 for (steps = chip->ecc.steps; steps > 0; steps--) {
1277 chip->read_buf(mtd, buf, eccsize);
1278 buf += eccsize;
1279
1280 if (chip->ecc.prepad) {
1281 chip->read_buf(mtd, oob, chip->ecc.prepad);
1282 oob += chip->ecc.prepad;
1283 }
1284
1285 chip->read_buf(mtd, oob, eccbytes);
1286 oob += eccbytes;
1287
1288 if (chip->ecc.postpad) {
1289 chip->read_buf(mtd, oob, chip->ecc.postpad);
1290 oob += chip->ecc.postpad;
1291 }
1292 }
1293
1294 size = mtd->oobsize - (oob - chip->oob_poi);
1295 if (size)
1296 chip->read_buf(mtd, oob, size);
1297
1298 return 0;
1299 }
1300
1301 /**
1302 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1303 * @mtd: mtd info structure
1304 * @chip: nand chip info structure
1305 * @buf: buffer to store read data
1306 * @oob_required: caller requires OOB data read to chip->oob_poi
1307 * @page: page number to read
1308 */
nand_read_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1309 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1310 uint8_t *buf, int oob_required, int page)
1311 {
1312 int i, eccsize = chip->ecc.size;
1313 int eccbytes = chip->ecc.bytes;
1314 int eccsteps = chip->ecc.steps;
1315 uint8_t *p = buf;
1316 uint8_t *ecc_calc = chip->buffers->ecccalc;
1317 uint8_t *ecc_code = chip->buffers->ecccode;
1318 uint32_t *eccpos = chip->ecc.layout->eccpos;
1319 unsigned int max_bitflips = 0;
1320
1321 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1322
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1324 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1325
1326 for (i = 0; i < chip->ecc.total; i++)
1327 ecc_code[i] = chip->oob_poi[eccpos[i]];
1328
1329 eccsteps = chip->ecc.steps;
1330 p = buf;
1331
1332 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333 int stat;
1334
1335 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1336 if (stat < 0) {
1337 mtd->ecc_stats.failed++;
1338 } else {
1339 mtd->ecc_stats.corrected += stat;
1340 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1341 }
1342 }
1343 return max_bitflips;
1344 }
1345
1346 /**
1347 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1348 * @mtd: mtd info structure
1349 * @chip: nand chip info structure
1350 * @data_offs: offset of requested data within the page
1351 * @readlen: data length
1352 * @bufpoi: buffer to store read data
1353 * @page: page number to read
1354 */
nand_read_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t data_offs,uint32_t readlen,uint8_t * bufpoi,int page)1355 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1356 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1357 int page)
1358 {
1359 int start_step, end_step, num_steps;
1360 uint32_t *eccpos = chip->ecc.layout->eccpos;
1361 uint8_t *p;
1362 int data_col_addr, i, gaps = 0;
1363 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1364 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1365 int index;
1366 unsigned int max_bitflips = 0;
1367
1368 /* Column address within the page aligned to ECC size (256bytes) */
1369 start_step = data_offs / chip->ecc.size;
1370 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1371 num_steps = end_step - start_step + 1;
1372 index = start_step * chip->ecc.bytes;
1373
1374 /* Data size aligned to ECC ecc.size */
1375 datafrag_len = num_steps * chip->ecc.size;
1376 eccfrag_len = num_steps * chip->ecc.bytes;
1377
1378 data_col_addr = start_step * chip->ecc.size;
1379 /* If we read not a page aligned data */
1380 if (data_col_addr != 0)
1381 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1382
1383 p = bufpoi + data_col_addr;
1384 chip->read_buf(mtd, p, datafrag_len);
1385
1386 /* Calculate ECC */
1387 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1388 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1389
1390 /*
1391 * The performance is faster if we position offsets according to
1392 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1393 */
1394 for (i = 0; i < eccfrag_len - 1; i++) {
1395 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1396 gaps = 1;
1397 break;
1398 }
1399 }
1400 if (gaps) {
1401 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1402 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1403 } else {
1404 /*
1405 * Send the command to read the particular ECC bytes take care
1406 * about buswidth alignment in read_buf.
1407 */
1408 aligned_pos = eccpos[index] & ~(busw - 1);
1409 aligned_len = eccfrag_len;
1410 if (eccpos[index] & (busw - 1))
1411 aligned_len++;
1412 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1413 aligned_len++;
1414
1415 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1416 mtd->writesize + aligned_pos, -1);
1417 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1418 }
1419
1420 for (i = 0; i < eccfrag_len; i++)
1421 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1422
1423 p = bufpoi + data_col_addr;
1424 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1425 int stat;
1426
1427 stat = chip->ecc.correct(mtd, p,
1428 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1429 if (stat < 0) {
1430 mtd->ecc_stats.failed++;
1431 } else {
1432 mtd->ecc_stats.corrected += stat;
1433 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1434 }
1435 }
1436 return max_bitflips;
1437 }
1438
1439 /**
1440 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1441 * @mtd: mtd info structure
1442 * @chip: nand chip info structure
1443 * @buf: buffer to store read data
1444 * @oob_required: caller requires OOB data read to chip->oob_poi
1445 * @page: page number to read
1446 *
1447 * Not for syndrome calculating ECC controllers which need a special oob layout.
1448 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1449 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1450 uint8_t *buf, int oob_required, int page)
1451 {
1452 int i, eccsize = chip->ecc.size;
1453 int eccbytes = chip->ecc.bytes;
1454 int eccsteps = chip->ecc.steps;
1455 uint8_t *p = buf;
1456 uint8_t *ecc_calc = chip->buffers->ecccalc;
1457 uint8_t *ecc_code = chip->buffers->ecccode;
1458 uint32_t *eccpos = chip->ecc.layout->eccpos;
1459 unsigned int max_bitflips = 0;
1460
1461 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1462 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1463 chip->read_buf(mtd, p, eccsize);
1464 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1465 }
1466 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1467
1468 for (i = 0; i < chip->ecc.total; i++)
1469 ecc_code[i] = chip->oob_poi[eccpos[i]];
1470
1471 eccsteps = chip->ecc.steps;
1472 p = buf;
1473
1474 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1475 int stat;
1476
1477 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1478 if (stat < 0) {
1479 mtd->ecc_stats.failed++;
1480 } else {
1481 mtd->ecc_stats.corrected += stat;
1482 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1483 }
1484 }
1485 return max_bitflips;
1486 }
1487
1488 /**
1489 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1490 * @mtd: mtd info structure
1491 * @chip: nand chip info structure
1492 * @buf: buffer to store read data
1493 * @oob_required: caller requires OOB data read to chip->oob_poi
1494 * @page: page number to read
1495 *
1496 * Hardware ECC for large page chips, require OOB to be read first. For this
1497 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1498 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1499 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1500 * the data area, by overwriting the NAND manufacturer bad block markings.
1501 */
nand_read_page_hwecc_oob_first(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1502 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1503 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1504 {
1505 int i, eccsize = chip->ecc.size;
1506 int eccbytes = chip->ecc.bytes;
1507 int eccsteps = chip->ecc.steps;
1508 uint8_t *p = buf;
1509 uint8_t *ecc_code = chip->buffers->ecccode;
1510 uint32_t *eccpos = chip->ecc.layout->eccpos;
1511 uint8_t *ecc_calc = chip->buffers->ecccalc;
1512 unsigned int max_bitflips = 0;
1513
1514 /* Read the OOB area first */
1515 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1516 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1517 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1518
1519 for (i = 0; i < chip->ecc.total; i++)
1520 ecc_code[i] = chip->oob_poi[eccpos[i]];
1521
1522 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1523 int stat;
1524
1525 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1526 chip->read_buf(mtd, p, eccsize);
1527 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1528
1529 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1530 if (stat < 0) {
1531 mtd->ecc_stats.failed++;
1532 } else {
1533 mtd->ecc_stats.corrected += stat;
1534 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1535 }
1536 }
1537 return max_bitflips;
1538 }
1539
1540 /**
1541 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1542 * @mtd: mtd info structure
1543 * @chip: nand chip info structure
1544 * @buf: buffer to store read data
1545 * @oob_required: caller requires OOB data read to chip->oob_poi
1546 * @page: page number to read
1547 *
1548 * The hw generator calculates the error syndrome automatically. Therefore we
1549 * need a special oob layout and handling.
1550 */
nand_read_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)1551 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1552 uint8_t *buf, int oob_required, int page)
1553 {
1554 int i, eccsize = chip->ecc.size;
1555 int eccbytes = chip->ecc.bytes;
1556 int eccsteps = chip->ecc.steps;
1557 uint8_t *p = buf;
1558 uint8_t *oob = chip->oob_poi;
1559 unsigned int max_bitflips = 0;
1560
1561 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1562 int stat;
1563
1564 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1565 chip->read_buf(mtd, p, eccsize);
1566
1567 if (chip->ecc.prepad) {
1568 chip->read_buf(mtd, oob, chip->ecc.prepad);
1569 oob += chip->ecc.prepad;
1570 }
1571
1572 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1573 chip->read_buf(mtd, oob, eccbytes);
1574 stat = chip->ecc.correct(mtd, p, oob, NULL);
1575
1576 if (stat < 0) {
1577 mtd->ecc_stats.failed++;
1578 } else {
1579 mtd->ecc_stats.corrected += stat;
1580 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1581 }
1582
1583 oob += eccbytes;
1584
1585 if (chip->ecc.postpad) {
1586 chip->read_buf(mtd, oob, chip->ecc.postpad);
1587 oob += chip->ecc.postpad;
1588 }
1589 }
1590
1591 /* Calculate remaining oob bytes */
1592 i = mtd->oobsize - (oob - chip->oob_poi);
1593 if (i)
1594 chip->read_buf(mtd, oob, i);
1595
1596 return max_bitflips;
1597 }
1598
1599 /**
1600 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1601 * @chip: nand chip structure
1602 * @oob: oob destination address
1603 * @ops: oob ops structure
1604 * @len: size of oob to transfer
1605 */
nand_transfer_oob(struct nand_chip * chip,uint8_t * oob,struct mtd_oob_ops * ops,size_t len)1606 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1607 struct mtd_oob_ops *ops, size_t len)
1608 {
1609 switch (ops->mode) {
1610
1611 case MTD_OPS_PLACE_OOB:
1612 case MTD_OPS_RAW:
1613 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1614 return oob + len;
1615
1616 case MTD_OPS_AUTO_OOB: {
1617 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1618 uint32_t boffs = 0, roffs = ops->ooboffs;
1619 size_t bytes = 0;
1620
1621 for (; free->length && len; free++, len -= bytes) {
1622 /* Read request not from offset 0? */
1623 if (unlikely(roffs)) {
1624 if (roffs >= free->length) {
1625 roffs -= free->length;
1626 continue;
1627 }
1628 boffs = free->offset + roffs;
1629 bytes = min_t(size_t, len,
1630 (free->length - roffs));
1631 roffs = 0;
1632 } else {
1633 bytes = min_t(size_t, len, free->length);
1634 boffs = free->offset;
1635 }
1636 memcpy(oob, chip->oob_poi + boffs, bytes);
1637 oob += bytes;
1638 }
1639 return oob;
1640 }
1641 default:
1642 BUG();
1643 }
1644 return NULL;
1645 }
1646
1647 /**
1648 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1649 * @mtd: MTD device structure
1650 * @retry_mode: the retry mode to use
1651 *
1652 * Some vendors supply a special command to shift the Vt threshold, to be used
1653 * when there are too many bitflips in a page (i.e., ECC error). After setting
1654 * a new threshold, the host should retry reading the page.
1655 */
nand_setup_read_retry(struct mtd_info * mtd,int retry_mode)1656 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1657 {
1658 struct nand_chip *chip = mtd->priv;
1659
1660 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1661
1662 if (retry_mode >= chip->read_retries)
1663 return -EINVAL;
1664
1665 if (!chip->setup_read_retry)
1666 return -EOPNOTSUPP;
1667
1668 return chip->setup_read_retry(mtd, retry_mode);
1669 }
1670
1671 /**
1672 * nand_do_read_ops - [INTERN] Read data with ECC
1673 * @mtd: MTD device structure
1674 * @from: offset to read from
1675 * @ops: oob ops structure
1676 *
1677 * Internal function. Called with chip held.
1678 */
nand_do_read_ops(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)1679 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1680 struct mtd_oob_ops *ops)
1681 {
1682 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1683 struct nand_chip *chip = mtd->priv;
1684 int ret = 0;
1685 uint32_t readlen = ops->len;
1686 uint32_t oobreadlen = ops->ooblen;
1687 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1688 mtd->oobavail : mtd->oobsize;
1689
1690 uint8_t *bufpoi, *oob, *buf;
1691 int use_bufpoi;
1692 unsigned int max_bitflips = 0;
1693 int retry_mode = 0;
1694 bool ecc_fail = false;
1695
1696 chipnr = (int)(from >> chip->chip_shift);
1697 chip->select_chip(mtd, chipnr);
1698
1699 realpage = (int)(from >> chip->page_shift);
1700 page = realpage & chip->pagemask;
1701
1702 col = (int)(from & (mtd->writesize - 1));
1703
1704 buf = ops->datbuf;
1705 oob = ops->oobbuf;
1706 oob_required = oob ? 1 : 0;
1707
1708 while (1) {
1709 unsigned int ecc_failures = mtd->ecc_stats.failed;
1710
1711 bytes = min(mtd->writesize - col, readlen);
1712 aligned = (bytes == mtd->writesize);
1713
1714 if (!aligned)
1715 use_bufpoi = 1;
1716 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1717 use_bufpoi = !virt_addr_valid(buf);
1718 else
1719 use_bufpoi = 0;
1720
1721 /* Is the current page in the buffer? */
1722 if (realpage != chip->pagebuf || oob) {
1723 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1724
1725 if (use_bufpoi && aligned)
1726 pr_debug("%s: using read bounce buffer for buf@%p\n",
1727 __func__, buf);
1728
1729 read_retry:
1730 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1731
1732 /*
1733 * Now read the page into the buffer. Absent an error,
1734 * the read methods return max bitflips per ecc step.
1735 */
1736 if (unlikely(ops->mode == MTD_OPS_RAW))
1737 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1738 oob_required,
1739 page);
1740 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1741 !oob)
1742 ret = chip->ecc.read_subpage(mtd, chip,
1743 col, bytes, bufpoi,
1744 page);
1745 else
1746 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1747 oob_required, page);
1748 if (ret < 0) {
1749 if (use_bufpoi)
1750 /* Invalidate page cache */
1751 chip->pagebuf = -1;
1752 break;
1753 }
1754
1755 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1756
1757 /* Transfer not aligned data */
1758 if (use_bufpoi) {
1759 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1760 !(mtd->ecc_stats.failed - ecc_failures) &&
1761 (ops->mode != MTD_OPS_RAW)) {
1762 chip->pagebuf = realpage;
1763 chip->pagebuf_bitflips = ret;
1764 } else {
1765 /* Invalidate page cache */
1766 chip->pagebuf = -1;
1767 }
1768 memcpy(buf, chip->buffers->databuf + col, bytes);
1769 }
1770
1771 if (unlikely(oob)) {
1772 int toread = min(oobreadlen, max_oobsize);
1773
1774 if (toread) {
1775 oob = nand_transfer_oob(chip,
1776 oob, ops, toread);
1777 oobreadlen -= toread;
1778 }
1779 }
1780
1781 if (chip->options & NAND_NEED_READRDY) {
1782 /* Apply delay or wait for ready/busy pin */
1783 if (!chip->dev_ready)
1784 udelay(chip->chip_delay);
1785 else
1786 nand_wait_ready(mtd);
1787 }
1788
1789 if (mtd->ecc_stats.failed - ecc_failures) {
1790 if (retry_mode + 1 < chip->read_retries) {
1791 retry_mode++;
1792 ret = nand_setup_read_retry(mtd,
1793 retry_mode);
1794 if (ret < 0)
1795 break;
1796
1797 /* Reset failures; retry */
1798 mtd->ecc_stats.failed = ecc_failures;
1799 goto read_retry;
1800 } else {
1801 /* No more retry modes; real failure */
1802 ecc_fail = true;
1803 }
1804 }
1805
1806 buf += bytes;
1807 } else {
1808 memcpy(buf, chip->buffers->databuf + col, bytes);
1809 buf += bytes;
1810 max_bitflips = max_t(unsigned int, max_bitflips,
1811 chip->pagebuf_bitflips);
1812 }
1813
1814 readlen -= bytes;
1815
1816 /* Reset to retry mode 0 */
1817 if (retry_mode) {
1818 ret = nand_setup_read_retry(mtd, 0);
1819 if (ret < 0)
1820 break;
1821 retry_mode = 0;
1822 }
1823
1824 if (!readlen)
1825 break;
1826
1827 /* For subsequent reads align to page boundary */
1828 col = 0;
1829 /* Increment page address */
1830 realpage++;
1831
1832 page = realpage & chip->pagemask;
1833 /* Check, if we cross a chip boundary */
1834 if (!page) {
1835 chipnr++;
1836 chip->select_chip(mtd, -1);
1837 chip->select_chip(mtd, chipnr);
1838 }
1839 }
1840 chip->select_chip(mtd, -1);
1841
1842 ops->retlen = ops->len - (size_t) readlen;
1843 if (oob)
1844 ops->oobretlen = ops->ooblen - oobreadlen;
1845
1846 if (ret < 0)
1847 return ret;
1848
1849 if (ecc_fail)
1850 return -EBADMSG;
1851
1852 return max_bitflips;
1853 }
1854
1855 /**
1856 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1857 * @mtd: MTD device structure
1858 * @from: offset to read from
1859 * @len: number of bytes to read
1860 * @retlen: pointer to variable to store the number of read bytes
1861 * @buf: the databuffer to put data
1862 *
1863 * Get hold of the chip and call nand_do_read.
1864 */
nand_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,uint8_t * buf)1865 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1866 size_t *retlen, uint8_t *buf)
1867 {
1868 struct mtd_oob_ops ops;
1869 int ret;
1870
1871 nand_get_device(mtd, FL_READING);
1872 memset(&ops, 0, sizeof(ops));
1873 ops.len = len;
1874 ops.datbuf = buf;
1875 ops.mode = MTD_OPS_PLACE_OOB;
1876 ret = nand_do_read_ops(mtd, from, &ops);
1877 *retlen = ops.retlen;
1878 nand_release_device(mtd);
1879 return ret;
1880 }
1881
1882 /**
1883 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1884 * @mtd: mtd info structure
1885 * @chip: nand chip info structure
1886 * @page: page number to read
1887 */
nand_read_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1888 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1889 int page)
1890 {
1891 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1892 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1893 return 0;
1894 }
1895
1896 /**
1897 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1898 * with syndromes
1899 * @mtd: mtd info structure
1900 * @chip: nand chip info structure
1901 * @page: page number to read
1902 */
nand_read_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1903 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1904 int page)
1905 {
1906 int length = mtd->oobsize;
1907 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1908 int eccsize = chip->ecc.size;
1909 uint8_t *bufpoi = chip->oob_poi;
1910 int i, toread, sndrnd = 0, pos;
1911
1912 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1913 for (i = 0; i < chip->ecc.steps; i++) {
1914 if (sndrnd) {
1915 pos = eccsize + i * (eccsize + chunk);
1916 if (mtd->writesize > 512)
1917 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1918 else
1919 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1920 } else
1921 sndrnd = 1;
1922 toread = min_t(int, length, chunk);
1923 chip->read_buf(mtd, bufpoi, toread);
1924 bufpoi += toread;
1925 length -= toread;
1926 }
1927 if (length > 0)
1928 chip->read_buf(mtd, bufpoi, length);
1929
1930 return 0;
1931 }
1932
1933 /**
1934 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1935 * @mtd: mtd info structure
1936 * @chip: nand chip info structure
1937 * @page: page number to write
1938 */
nand_write_oob_std(struct mtd_info * mtd,struct nand_chip * chip,int page)1939 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1940 int page)
1941 {
1942 int status = 0;
1943 const uint8_t *buf = chip->oob_poi;
1944 int length = mtd->oobsize;
1945
1946 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1947 chip->write_buf(mtd, buf, length);
1948 /* Send command to program the OOB data */
1949 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1950
1951 status = chip->waitfunc(mtd, chip);
1952
1953 return status & NAND_STATUS_FAIL ? -EIO : 0;
1954 }
1955
1956 /**
1957 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1958 * with syndrome - only for large page flash
1959 * @mtd: mtd info structure
1960 * @chip: nand chip info structure
1961 * @page: page number to write
1962 */
nand_write_oob_syndrome(struct mtd_info * mtd,struct nand_chip * chip,int page)1963 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1964 struct nand_chip *chip, int page)
1965 {
1966 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1967 int eccsize = chip->ecc.size, length = mtd->oobsize;
1968 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1969 const uint8_t *bufpoi = chip->oob_poi;
1970
1971 /*
1972 * data-ecc-data-ecc ... ecc-oob
1973 * or
1974 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1975 */
1976 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1977 pos = steps * (eccsize + chunk);
1978 steps = 0;
1979 } else
1980 pos = eccsize;
1981
1982 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1983 for (i = 0; i < steps; i++) {
1984 if (sndcmd) {
1985 if (mtd->writesize <= 512) {
1986 uint32_t fill = 0xFFFFFFFF;
1987
1988 len = eccsize;
1989 while (len > 0) {
1990 int num = min_t(int, len, 4);
1991 chip->write_buf(mtd, (uint8_t *)&fill,
1992 num);
1993 len -= num;
1994 }
1995 } else {
1996 pos = eccsize + i * (eccsize + chunk);
1997 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1998 }
1999 } else
2000 sndcmd = 1;
2001 len = min_t(int, length, chunk);
2002 chip->write_buf(mtd, bufpoi, len);
2003 bufpoi += len;
2004 length -= len;
2005 }
2006 if (length > 0)
2007 chip->write_buf(mtd, bufpoi, length);
2008
2009 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2010 status = chip->waitfunc(mtd, chip);
2011
2012 return status & NAND_STATUS_FAIL ? -EIO : 0;
2013 }
2014
2015 /**
2016 * nand_do_read_oob - [INTERN] NAND read out-of-band
2017 * @mtd: MTD device structure
2018 * @from: offset to read from
2019 * @ops: oob operations description structure
2020 *
2021 * NAND read out-of-band data from the spare area.
2022 */
nand_do_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2023 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2024 struct mtd_oob_ops *ops)
2025 {
2026 int page, realpage, chipnr;
2027 struct nand_chip *chip = mtd->priv;
2028 struct mtd_ecc_stats stats;
2029 int readlen = ops->ooblen;
2030 int len;
2031 uint8_t *buf = ops->oobbuf;
2032 int ret = 0;
2033
2034 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2035 __func__, (unsigned long long)from, readlen);
2036
2037 stats = mtd->ecc_stats;
2038
2039 if (ops->mode == MTD_OPS_AUTO_OOB)
2040 len = chip->ecc.layout->oobavail;
2041 else
2042 len = mtd->oobsize;
2043
2044 if (unlikely(ops->ooboffs >= len)) {
2045 pr_debug("%s: attempt to start read outside oob\n",
2046 __func__);
2047 return -EINVAL;
2048 }
2049
2050 /* Do not allow reads past end of device */
2051 if (unlikely(from >= mtd->size ||
2052 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2053 (from >> chip->page_shift)) * len)) {
2054 pr_debug("%s: attempt to read beyond end of device\n",
2055 __func__);
2056 return -EINVAL;
2057 }
2058
2059 chipnr = (int)(from >> chip->chip_shift);
2060 chip->select_chip(mtd, chipnr);
2061
2062 /* Shift to get page */
2063 realpage = (int)(from >> chip->page_shift);
2064 page = realpage & chip->pagemask;
2065
2066 while (1) {
2067 if (ops->mode == MTD_OPS_RAW)
2068 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2069 else
2070 ret = chip->ecc.read_oob(mtd, chip, page);
2071
2072 if (ret < 0)
2073 break;
2074
2075 len = min(len, readlen);
2076 buf = nand_transfer_oob(chip, buf, ops, len);
2077
2078 if (chip->options & NAND_NEED_READRDY) {
2079 /* Apply delay or wait for ready/busy pin */
2080 if (!chip->dev_ready)
2081 udelay(chip->chip_delay);
2082 else
2083 nand_wait_ready(mtd);
2084 }
2085
2086 readlen -= len;
2087 if (!readlen)
2088 break;
2089
2090 /* Increment page address */
2091 realpage++;
2092
2093 page = realpage & chip->pagemask;
2094 /* Check, if we cross a chip boundary */
2095 if (!page) {
2096 chipnr++;
2097 chip->select_chip(mtd, -1);
2098 chip->select_chip(mtd, chipnr);
2099 }
2100 }
2101 chip->select_chip(mtd, -1);
2102
2103 ops->oobretlen = ops->ooblen - readlen;
2104
2105 if (ret < 0)
2106 return ret;
2107
2108 if (mtd->ecc_stats.failed - stats.failed)
2109 return -EBADMSG;
2110
2111 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2112 }
2113
2114 /**
2115 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2116 * @mtd: MTD device structure
2117 * @from: offset to read from
2118 * @ops: oob operation description structure
2119 *
2120 * NAND read data and/or out-of-band data.
2121 */
nand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)2122 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2123 struct mtd_oob_ops *ops)
2124 {
2125 int ret = -ENOTSUPP;
2126
2127 ops->retlen = 0;
2128
2129 /* Do not allow reads past end of device */
2130 if (ops->datbuf && (from + ops->len) > mtd->size) {
2131 pr_debug("%s: attempt to read beyond end of device\n",
2132 __func__);
2133 return -EINVAL;
2134 }
2135
2136 nand_get_device(mtd, FL_READING);
2137
2138 switch (ops->mode) {
2139 case MTD_OPS_PLACE_OOB:
2140 case MTD_OPS_AUTO_OOB:
2141 case MTD_OPS_RAW:
2142 break;
2143
2144 default:
2145 goto out;
2146 }
2147
2148 if (!ops->datbuf)
2149 ret = nand_do_read_oob(mtd, from, ops);
2150 else
2151 ret = nand_do_read_ops(mtd, from, ops);
2152
2153 out:
2154 nand_release_device(mtd);
2155 return ret;
2156 }
2157
2158
2159 /**
2160 * nand_write_page_raw - [INTERN] raw page write function
2161 * @mtd: mtd info structure
2162 * @chip: nand chip info structure
2163 * @buf: data buffer
2164 * @oob_required: must write chip->oob_poi to OOB
2165 * @page: page number to write
2166 *
2167 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2168 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2169 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2170 const uint8_t *buf, int oob_required, int page)
2171 {
2172 chip->write_buf(mtd, buf, mtd->writesize);
2173 if (oob_required)
2174 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2175
2176 return 0;
2177 }
2178
2179 /**
2180 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2181 * @mtd: mtd info structure
2182 * @chip: nand chip info structure
2183 * @buf: data buffer
2184 * @oob_required: must write chip->oob_poi to OOB
2185 * @page: page number to write
2186 *
2187 * We need a special oob layout and handling even when ECC isn't checked.
2188 */
nand_write_page_raw_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2189 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2190 struct nand_chip *chip,
2191 const uint8_t *buf, int oob_required,
2192 int page)
2193 {
2194 int eccsize = chip->ecc.size;
2195 int eccbytes = chip->ecc.bytes;
2196 uint8_t *oob = chip->oob_poi;
2197 int steps, size;
2198
2199 for (steps = chip->ecc.steps; steps > 0; steps--) {
2200 chip->write_buf(mtd, buf, eccsize);
2201 buf += eccsize;
2202
2203 if (chip->ecc.prepad) {
2204 chip->write_buf(mtd, oob, chip->ecc.prepad);
2205 oob += chip->ecc.prepad;
2206 }
2207
2208 chip->write_buf(mtd, oob, eccbytes);
2209 oob += eccbytes;
2210
2211 if (chip->ecc.postpad) {
2212 chip->write_buf(mtd, oob, chip->ecc.postpad);
2213 oob += chip->ecc.postpad;
2214 }
2215 }
2216
2217 size = mtd->oobsize - (oob - chip->oob_poi);
2218 if (size)
2219 chip->write_buf(mtd, oob, size);
2220
2221 return 0;
2222 }
2223 /**
2224 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2225 * @mtd: mtd info structure
2226 * @chip: nand chip info structure
2227 * @buf: data buffer
2228 * @oob_required: must write chip->oob_poi to OOB
2229 * @page: page number to write
2230 */
nand_write_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2231 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2232 const uint8_t *buf, int oob_required,
2233 int page)
2234 {
2235 int i, eccsize = chip->ecc.size;
2236 int eccbytes = chip->ecc.bytes;
2237 int eccsteps = chip->ecc.steps;
2238 uint8_t *ecc_calc = chip->buffers->ecccalc;
2239 const uint8_t *p = buf;
2240 uint32_t *eccpos = chip->ecc.layout->eccpos;
2241
2242 /* Software ECC calculation */
2243 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2244 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2245
2246 for (i = 0; i < chip->ecc.total; i++)
2247 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2248
2249 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2250 }
2251
2252 /**
2253 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2254 * @mtd: mtd info structure
2255 * @chip: nand chip info structure
2256 * @buf: data buffer
2257 * @oob_required: must write chip->oob_poi to OOB
2258 * @page: page number to write
2259 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2260 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2261 const uint8_t *buf, int oob_required,
2262 int page)
2263 {
2264 int i, eccsize = chip->ecc.size;
2265 int eccbytes = chip->ecc.bytes;
2266 int eccsteps = chip->ecc.steps;
2267 uint8_t *ecc_calc = chip->buffers->ecccalc;
2268 const uint8_t *p = buf;
2269 uint32_t *eccpos = chip->ecc.layout->eccpos;
2270
2271 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2272 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2273 chip->write_buf(mtd, p, eccsize);
2274 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2275 }
2276
2277 for (i = 0; i < chip->ecc.total; i++)
2278 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2279
2280 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2281
2282 return 0;
2283 }
2284
2285
2286 /**
2287 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2288 * @mtd: mtd info structure
2289 * @chip: nand chip info structure
2290 * @offset: column address of subpage within the page
2291 * @data_len: data length
2292 * @buf: data buffer
2293 * @oob_required: must write chip->oob_poi to OOB
2294 * @page: page number to write
2295 */
nand_write_subpage_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)2296 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2297 struct nand_chip *chip, uint32_t offset,
2298 uint32_t data_len, const uint8_t *buf,
2299 int oob_required, int page)
2300 {
2301 uint8_t *oob_buf = chip->oob_poi;
2302 uint8_t *ecc_calc = chip->buffers->ecccalc;
2303 int ecc_size = chip->ecc.size;
2304 int ecc_bytes = chip->ecc.bytes;
2305 int ecc_steps = chip->ecc.steps;
2306 uint32_t *eccpos = chip->ecc.layout->eccpos;
2307 uint32_t start_step = offset / ecc_size;
2308 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2309 int oob_bytes = mtd->oobsize / ecc_steps;
2310 int step, i;
2311
2312 for (step = 0; step < ecc_steps; step++) {
2313 /* configure controller for WRITE access */
2314 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2315
2316 /* write data (untouched subpages already masked by 0xFF) */
2317 chip->write_buf(mtd, buf, ecc_size);
2318
2319 /* mask ECC of un-touched subpages by padding 0xFF */
2320 if ((step < start_step) || (step > end_step))
2321 memset(ecc_calc, 0xff, ecc_bytes);
2322 else
2323 chip->ecc.calculate(mtd, buf, ecc_calc);
2324
2325 /* mask OOB of un-touched subpages by padding 0xFF */
2326 /* if oob_required, preserve OOB metadata of written subpage */
2327 if (!oob_required || (step < start_step) || (step > end_step))
2328 memset(oob_buf, 0xff, oob_bytes);
2329
2330 buf += ecc_size;
2331 ecc_calc += ecc_bytes;
2332 oob_buf += oob_bytes;
2333 }
2334
2335 /* copy calculated ECC for whole page to chip->buffer->oob */
2336 /* this include masked-value(0xFF) for unwritten subpages */
2337 ecc_calc = chip->buffers->ecccalc;
2338 for (i = 0; i < chip->ecc.total; i++)
2339 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2340
2341 /* write OOB buffer to NAND device */
2342 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2343
2344 return 0;
2345 }
2346
2347
2348 /**
2349 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2350 * @mtd: mtd info structure
2351 * @chip: nand chip info structure
2352 * @buf: data buffer
2353 * @oob_required: must write chip->oob_poi to OOB
2354 * @page: page number to write
2355 *
2356 * The hw generator calculates the error syndrome automatically. Therefore we
2357 * need a special oob layout and handling.
2358 */
nand_write_page_syndrome(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2359 static int nand_write_page_syndrome(struct mtd_info *mtd,
2360 struct nand_chip *chip,
2361 const uint8_t *buf, int oob_required,
2362 int page)
2363 {
2364 int i, eccsize = chip->ecc.size;
2365 int eccbytes = chip->ecc.bytes;
2366 int eccsteps = chip->ecc.steps;
2367 const uint8_t *p = buf;
2368 uint8_t *oob = chip->oob_poi;
2369
2370 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2371
2372 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2373 chip->write_buf(mtd, p, eccsize);
2374
2375 if (chip->ecc.prepad) {
2376 chip->write_buf(mtd, oob, chip->ecc.prepad);
2377 oob += chip->ecc.prepad;
2378 }
2379
2380 chip->ecc.calculate(mtd, p, oob);
2381 chip->write_buf(mtd, oob, eccbytes);
2382 oob += eccbytes;
2383
2384 if (chip->ecc.postpad) {
2385 chip->write_buf(mtd, oob, chip->ecc.postpad);
2386 oob += chip->ecc.postpad;
2387 }
2388 }
2389
2390 /* Calculate remaining oob bytes */
2391 i = mtd->oobsize - (oob - chip->oob_poi);
2392 if (i)
2393 chip->write_buf(mtd, oob, i);
2394
2395 return 0;
2396 }
2397
2398 /**
2399 * nand_write_page - [REPLACEABLE] write one page
2400 * @mtd: MTD device structure
2401 * @chip: NAND chip descriptor
2402 * @offset: address offset within the page
2403 * @data_len: length of actual data to be written
2404 * @buf: the data to write
2405 * @oob_required: must write chip->oob_poi to OOB
2406 * @page: page number to write
2407 * @cached: cached programming
2408 * @raw: use _raw version of write_page
2409 */
nand_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int cached,int raw)2410 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2411 uint32_t offset, int data_len, const uint8_t *buf,
2412 int oob_required, int page, int cached, int raw)
2413 {
2414 int status, subpage;
2415
2416 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2417 chip->ecc.write_subpage)
2418 subpage = offset || (data_len < mtd->writesize);
2419 else
2420 subpage = 0;
2421
2422 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2423
2424 if (unlikely(raw))
2425 status = chip->ecc.write_page_raw(mtd, chip, buf,
2426 oob_required, page);
2427 else if (subpage)
2428 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2429 buf, oob_required, page);
2430 else
2431 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2432 page);
2433
2434 if (status < 0)
2435 return status;
2436
2437 /*
2438 * Cached progamming disabled for now. Not sure if it's worth the
2439 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2440 */
2441 cached = 0;
2442
2443 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2444
2445 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2446 status = chip->waitfunc(mtd, chip);
2447 /*
2448 * See if operation failed and additional status checks are
2449 * available.
2450 */
2451 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2452 status = chip->errstat(mtd, chip, FL_WRITING, status,
2453 page);
2454
2455 if (status & NAND_STATUS_FAIL)
2456 return -EIO;
2457 } else {
2458 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2459 status = chip->waitfunc(mtd, chip);
2460 }
2461
2462 return 0;
2463 }
2464
2465 /**
2466 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2467 * @mtd: MTD device structure
2468 * @oob: oob data buffer
2469 * @len: oob data write length
2470 * @ops: oob ops structure
2471 */
nand_fill_oob(struct mtd_info * mtd,uint8_t * oob,size_t len,struct mtd_oob_ops * ops)2472 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2473 struct mtd_oob_ops *ops)
2474 {
2475 struct nand_chip *chip = mtd->priv;
2476
2477 /*
2478 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2479 * data from a previous OOB read.
2480 */
2481 memset(chip->oob_poi, 0xff, mtd->oobsize);
2482
2483 switch (ops->mode) {
2484
2485 case MTD_OPS_PLACE_OOB:
2486 case MTD_OPS_RAW:
2487 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2488 return oob + len;
2489
2490 case MTD_OPS_AUTO_OOB: {
2491 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2492 uint32_t boffs = 0, woffs = ops->ooboffs;
2493 size_t bytes = 0;
2494
2495 for (; free->length && len; free++, len -= bytes) {
2496 /* Write request not from offset 0? */
2497 if (unlikely(woffs)) {
2498 if (woffs >= free->length) {
2499 woffs -= free->length;
2500 continue;
2501 }
2502 boffs = free->offset + woffs;
2503 bytes = min_t(size_t, len,
2504 (free->length - woffs));
2505 woffs = 0;
2506 } else {
2507 bytes = min_t(size_t, len, free->length);
2508 boffs = free->offset;
2509 }
2510 memcpy(chip->oob_poi + boffs, oob, bytes);
2511 oob += bytes;
2512 }
2513 return oob;
2514 }
2515 default:
2516 BUG();
2517 }
2518 return NULL;
2519 }
2520
2521 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2522
2523 /**
2524 * nand_do_write_ops - [INTERN] NAND write with ECC
2525 * @mtd: MTD device structure
2526 * @to: offset to write to
2527 * @ops: oob operations description structure
2528 *
2529 * NAND write with ECC.
2530 */
nand_do_write_ops(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2531 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2532 struct mtd_oob_ops *ops)
2533 {
2534 int chipnr, realpage, page, blockmask, column;
2535 struct nand_chip *chip = mtd->priv;
2536 uint32_t writelen = ops->len;
2537
2538 uint32_t oobwritelen = ops->ooblen;
2539 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2540 mtd->oobavail : mtd->oobsize;
2541
2542 uint8_t *oob = ops->oobbuf;
2543 uint8_t *buf = ops->datbuf;
2544 int ret;
2545 int oob_required = oob ? 1 : 0;
2546
2547 ops->retlen = 0;
2548 if (!writelen)
2549 return 0;
2550
2551 /* Reject writes, which are not page aligned */
2552 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2553 pr_notice("%s: attempt to write non page aligned data\n",
2554 __func__);
2555 return -EINVAL;
2556 }
2557
2558 column = to & (mtd->writesize - 1);
2559
2560 chipnr = (int)(to >> chip->chip_shift);
2561 chip->select_chip(mtd, chipnr);
2562
2563 /* Check, if it is write protected */
2564 if (nand_check_wp(mtd)) {
2565 ret = -EIO;
2566 goto err_out;
2567 }
2568
2569 realpage = (int)(to >> chip->page_shift);
2570 page = realpage & chip->pagemask;
2571 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2572
2573 /* Invalidate the page cache, when we write to the cached page */
2574 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2575 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2576 chip->pagebuf = -1;
2577
2578 /* Don't allow multipage oob writes with offset */
2579 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2580 ret = -EINVAL;
2581 goto err_out;
2582 }
2583
2584 while (1) {
2585 int bytes = mtd->writesize;
2586 int cached = writelen > bytes && page != blockmask;
2587 uint8_t *wbuf = buf;
2588 int use_bufpoi;
2589 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2590
2591 if (part_pagewr)
2592 use_bufpoi = 1;
2593 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2594 use_bufpoi = !virt_addr_valid(buf);
2595 else
2596 use_bufpoi = 0;
2597
2598 /* Partial page write?, or need to use bounce buffer */
2599 if (use_bufpoi) {
2600 pr_debug("%s: using write bounce buffer for buf@%p\n",
2601 __func__, buf);
2602 cached = 0;
2603 if (part_pagewr)
2604 bytes = min_t(int, bytes - column, writelen);
2605 chip->pagebuf = -1;
2606 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2607 memcpy(&chip->buffers->databuf[column], buf, bytes);
2608 wbuf = chip->buffers->databuf;
2609 }
2610
2611 if (unlikely(oob)) {
2612 size_t len = min(oobwritelen, oobmaxlen);
2613 oob = nand_fill_oob(mtd, oob, len, ops);
2614 oobwritelen -= len;
2615 } else {
2616 /* We still need to erase leftover OOB data */
2617 memset(chip->oob_poi, 0xff, mtd->oobsize);
2618 }
2619 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2620 oob_required, page, cached,
2621 (ops->mode == MTD_OPS_RAW));
2622 if (ret)
2623 break;
2624
2625 writelen -= bytes;
2626 if (!writelen)
2627 break;
2628
2629 column = 0;
2630 buf += bytes;
2631 realpage++;
2632
2633 page = realpage & chip->pagemask;
2634 /* Check, if we cross a chip boundary */
2635 if (!page) {
2636 chipnr++;
2637 chip->select_chip(mtd, -1);
2638 chip->select_chip(mtd, chipnr);
2639 }
2640 }
2641
2642 ops->retlen = ops->len - writelen;
2643 if (unlikely(oob))
2644 ops->oobretlen = ops->ooblen;
2645
2646 err_out:
2647 chip->select_chip(mtd, -1);
2648 return ret;
2649 }
2650
2651 /**
2652 * panic_nand_write - [MTD Interface] NAND write with ECC
2653 * @mtd: MTD device structure
2654 * @to: offset to write to
2655 * @len: number of bytes to write
2656 * @retlen: pointer to variable to store the number of written bytes
2657 * @buf: the data to write
2658 *
2659 * NAND write with ECC. Used when performing writes in interrupt context, this
2660 * may for example be called by mtdoops when writing an oops while in panic.
2661 */
panic_nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)2662 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2663 size_t *retlen, const uint8_t *buf)
2664 {
2665 struct nand_chip *chip = mtd->priv;
2666 struct mtd_oob_ops ops;
2667 int ret;
2668
2669 /* Wait for the device to get ready */
2670 panic_nand_wait(mtd, chip, 400);
2671
2672 /* Grab the device */
2673 panic_nand_get_device(chip, mtd, FL_WRITING);
2674
2675 memset(&ops, 0, sizeof(ops));
2676 ops.len = len;
2677 ops.datbuf = (uint8_t *)buf;
2678 ops.mode = MTD_OPS_PLACE_OOB;
2679
2680 ret = nand_do_write_ops(mtd, to, &ops);
2681
2682 *retlen = ops.retlen;
2683 return ret;
2684 }
2685
2686 /**
2687 * nand_write - [MTD Interface] NAND write with ECC
2688 * @mtd: MTD device structure
2689 * @to: offset to write to
2690 * @len: number of bytes to write
2691 * @retlen: pointer to variable to store the number of written bytes
2692 * @buf: the data to write
2693 *
2694 * NAND write with ECC.
2695 */
nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)2696 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2697 size_t *retlen, const uint8_t *buf)
2698 {
2699 struct mtd_oob_ops ops;
2700 int ret;
2701
2702 nand_get_device(mtd, FL_WRITING);
2703 memset(&ops, 0, sizeof(ops));
2704 ops.len = len;
2705 ops.datbuf = (uint8_t *)buf;
2706 ops.mode = MTD_OPS_PLACE_OOB;
2707 ret = nand_do_write_ops(mtd, to, &ops);
2708 *retlen = ops.retlen;
2709 nand_release_device(mtd);
2710 return ret;
2711 }
2712
2713 /**
2714 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2715 * @mtd: MTD device structure
2716 * @to: offset to write to
2717 * @ops: oob operation description structure
2718 *
2719 * NAND write out-of-band.
2720 */
nand_do_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2721 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2722 struct mtd_oob_ops *ops)
2723 {
2724 int chipnr, page, status, len;
2725 struct nand_chip *chip = mtd->priv;
2726
2727 pr_debug("%s: to = 0x%08x, len = %i\n",
2728 __func__, (unsigned int)to, (int)ops->ooblen);
2729
2730 if (ops->mode == MTD_OPS_AUTO_OOB)
2731 len = chip->ecc.layout->oobavail;
2732 else
2733 len = mtd->oobsize;
2734
2735 /* Do not allow write past end of page */
2736 if ((ops->ooboffs + ops->ooblen) > len) {
2737 pr_debug("%s: attempt to write past end of page\n",
2738 __func__);
2739 return -EINVAL;
2740 }
2741
2742 if (unlikely(ops->ooboffs >= len)) {
2743 pr_debug("%s: attempt to start write outside oob\n",
2744 __func__);
2745 return -EINVAL;
2746 }
2747
2748 /* Do not allow write past end of device */
2749 if (unlikely(to >= mtd->size ||
2750 ops->ooboffs + ops->ooblen >
2751 ((mtd->size >> chip->page_shift) -
2752 (to >> chip->page_shift)) * len)) {
2753 pr_debug("%s: attempt to write beyond end of device\n",
2754 __func__);
2755 return -EINVAL;
2756 }
2757
2758 chipnr = (int)(to >> chip->chip_shift);
2759 chip->select_chip(mtd, chipnr);
2760
2761 /* Shift to get page */
2762 page = (int)(to >> chip->page_shift);
2763
2764 /*
2765 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2766 * of my DiskOnChip 2000 test units) will clear the whole data page too
2767 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2768 * it in the doc2000 driver in August 1999. dwmw2.
2769 */
2770 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2771
2772 /* Check, if it is write protected */
2773 if (nand_check_wp(mtd)) {
2774 chip->select_chip(mtd, -1);
2775 return -EROFS;
2776 }
2777
2778 /* Invalidate the page cache, if we write to the cached page */
2779 if (page == chip->pagebuf)
2780 chip->pagebuf = -1;
2781
2782 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2783
2784 if (ops->mode == MTD_OPS_RAW)
2785 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2786 else
2787 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2788
2789 chip->select_chip(mtd, -1);
2790
2791 if (status)
2792 return status;
2793
2794 ops->oobretlen = ops->ooblen;
2795
2796 return 0;
2797 }
2798
2799 /**
2800 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2801 * @mtd: MTD device structure
2802 * @to: offset to write to
2803 * @ops: oob operation description structure
2804 */
nand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)2805 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2806 struct mtd_oob_ops *ops)
2807 {
2808 int ret = -ENOTSUPP;
2809
2810 ops->retlen = 0;
2811
2812 /* Do not allow writes past end of device */
2813 if (ops->datbuf && (to + ops->len) > mtd->size) {
2814 pr_debug("%s: attempt to write beyond end of device\n",
2815 __func__);
2816 return -EINVAL;
2817 }
2818
2819 nand_get_device(mtd, FL_WRITING);
2820
2821 switch (ops->mode) {
2822 case MTD_OPS_PLACE_OOB:
2823 case MTD_OPS_AUTO_OOB:
2824 case MTD_OPS_RAW:
2825 break;
2826
2827 default:
2828 goto out;
2829 }
2830
2831 if (!ops->datbuf)
2832 ret = nand_do_write_oob(mtd, to, ops);
2833 else
2834 ret = nand_do_write_ops(mtd, to, ops);
2835
2836 out:
2837 nand_release_device(mtd);
2838 return ret;
2839 }
2840
2841 /**
2842 * single_erase - [GENERIC] NAND standard block erase command function
2843 * @mtd: MTD device structure
2844 * @page: the page address of the block which will be erased
2845 *
2846 * Standard erase command for NAND chips. Returns NAND status.
2847 */
single_erase(struct mtd_info * mtd,int page)2848 static int single_erase(struct mtd_info *mtd, int page)
2849 {
2850 struct nand_chip *chip = mtd->priv;
2851 /* Send commands to erase a block */
2852 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2853 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2854
2855 return chip->waitfunc(mtd, chip);
2856 }
2857
2858 /**
2859 * nand_erase - [MTD Interface] erase block(s)
2860 * @mtd: MTD device structure
2861 * @instr: erase instruction
2862 *
2863 * Erase one ore more blocks.
2864 */
nand_erase(struct mtd_info * mtd,struct erase_info * instr)2865 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2866 {
2867 return nand_erase_nand(mtd, instr, 0);
2868 }
2869
2870 /**
2871 * nand_erase_nand - [INTERN] erase block(s)
2872 * @mtd: MTD device structure
2873 * @instr: erase instruction
2874 * @allowbbt: allow erasing the bbt area
2875 *
2876 * Erase one ore more blocks.
2877 */
nand_erase_nand(struct mtd_info * mtd,struct erase_info * instr,int allowbbt)2878 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2879 int allowbbt)
2880 {
2881 int page, status, pages_per_block, ret, chipnr;
2882 struct nand_chip *chip = mtd->priv;
2883 loff_t len;
2884
2885 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2886 __func__, (unsigned long long)instr->addr,
2887 (unsigned long long)instr->len);
2888
2889 if (check_offs_len(mtd, instr->addr, instr->len))
2890 return -EINVAL;
2891
2892 /* Grab the lock and see if the device is available */
2893 nand_get_device(mtd, FL_ERASING);
2894
2895 /* Shift to get first page */
2896 page = (int)(instr->addr >> chip->page_shift);
2897 chipnr = (int)(instr->addr >> chip->chip_shift);
2898
2899 /* Calculate pages in each block */
2900 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2901
2902 /* Select the NAND device */
2903 chip->select_chip(mtd, chipnr);
2904
2905 /* Check, if it is write protected */
2906 if (nand_check_wp(mtd)) {
2907 pr_debug("%s: device is write protected!\n",
2908 __func__);
2909 instr->state = MTD_ERASE_FAILED;
2910 goto erase_exit;
2911 }
2912
2913 /* Loop through the pages */
2914 len = instr->len;
2915
2916 instr->state = MTD_ERASING;
2917
2918 while (len) {
2919 /* Check if we have a bad block, we do not erase bad blocks! */
2920 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2921 chip->page_shift, 0, allowbbt)) {
2922 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2923 __func__, page);
2924 instr->state = MTD_ERASE_FAILED;
2925 goto erase_exit;
2926 }
2927
2928 /*
2929 * Invalidate the page cache, if we erase the block which
2930 * contains the current cached page.
2931 */
2932 if (page <= chip->pagebuf && chip->pagebuf <
2933 (page + pages_per_block))
2934 chip->pagebuf = -1;
2935
2936 status = chip->erase(mtd, page & chip->pagemask);
2937
2938 /*
2939 * See if operation failed and additional status checks are
2940 * available
2941 */
2942 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2943 status = chip->errstat(mtd, chip, FL_ERASING,
2944 status, page);
2945
2946 /* See if block erase succeeded */
2947 if (status & NAND_STATUS_FAIL) {
2948 pr_debug("%s: failed erase, page 0x%08x\n",
2949 __func__, page);
2950 instr->state = MTD_ERASE_FAILED;
2951 instr->fail_addr =
2952 ((loff_t)page << chip->page_shift);
2953 goto erase_exit;
2954 }
2955
2956 /* Increment page address and decrement length */
2957 len -= (1ULL << chip->phys_erase_shift);
2958 page += pages_per_block;
2959
2960 /* Check, if we cross a chip boundary */
2961 if (len && !(page & chip->pagemask)) {
2962 chipnr++;
2963 chip->select_chip(mtd, -1);
2964 chip->select_chip(mtd, chipnr);
2965 }
2966 }
2967 instr->state = MTD_ERASE_DONE;
2968
2969 erase_exit:
2970
2971 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2972
2973 /* Deselect and wake up anyone waiting on the device */
2974 chip->select_chip(mtd, -1);
2975 nand_release_device(mtd);
2976
2977 /* Do call back function */
2978 if (!ret)
2979 mtd_erase_callback(instr);
2980
2981 /* Return more or less happy */
2982 return ret;
2983 }
2984
2985 /**
2986 * nand_sync - [MTD Interface] sync
2987 * @mtd: MTD device structure
2988 *
2989 * Sync is actually a wait for chip ready function.
2990 */
nand_sync(struct mtd_info * mtd)2991 static void nand_sync(struct mtd_info *mtd)
2992 {
2993 pr_debug("%s: called\n", __func__);
2994
2995 /* Grab the lock and see if the device is available */
2996 nand_get_device(mtd, FL_SYNCING);
2997 /* Release it and go back */
2998 nand_release_device(mtd);
2999 }
3000
3001 /**
3002 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3003 * @mtd: MTD device structure
3004 * @offs: offset relative to mtd start
3005 */
nand_block_isbad(struct mtd_info * mtd,loff_t offs)3006 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3007 {
3008 return nand_block_checkbad(mtd, offs, 1, 0);
3009 }
3010
3011 /**
3012 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3013 * @mtd: MTD device structure
3014 * @ofs: offset relative to mtd start
3015 */
nand_block_markbad(struct mtd_info * mtd,loff_t ofs)3016 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3017 {
3018 int ret;
3019
3020 ret = nand_block_isbad(mtd, ofs);
3021 if (ret) {
3022 /* If it was bad already, return success and do nothing */
3023 if (ret > 0)
3024 return 0;
3025 return ret;
3026 }
3027
3028 return nand_block_markbad_lowlevel(mtd, ofs);
3029 }
3030
3031 /**
3032 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3033 * @mtd: MTD device structure
3034 * @chip: nand chip info structure
3035 * @addr: feature address.
3036 * @subfeature_param: the subfeature parameters, a four bytes array.
3037 */
nand_onfi_set_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3038 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3039 int addr, uint8_t *subfeature_param)
3040 {
3041 int status;
3042 int i;
3043
3044 if (!chip->onfi_version ||
3045 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3046 & ONFI_OPT_CMD_SET_GET_FEATURES))
3047 return -EINVAL;
3048
3049 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3050 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3051 chip->write_byte(mtd, subfeature_param[i]);
3052
3053 status = chip->waitfunc(mtd, chip);
3054 if (status & NAND_STATUS_FAIL)
3055 return -EIO;
3056 return 0;
3057 }
3058
3059 /**
3060 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3061 * @mtd: MTD device structure
3062 * @chip: nand chip info structure
3063 * @addr: feature address.
3064 * @subfeature_param: the subfeature parameters, a four bytes array.
3065 */
nand_onfi_get_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,uint8_t * subfeature_param)3066 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3067 int addr, uint8_t *subfeature_param)
3068 {
3069 int i;
3070
3071 if (!chip->onfi_version ||
3072 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3073 & ONFI_OPT_CMD_SET_GET_FEATURES))
3074 return -EINVAL;
3075
3076 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3077 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3078 *subfeature_param++ = chip->read_byte(mtd);
3079 return 0;
3080 }
3081
3082 /**
3083 * nand_suspend - [MTD Interface] Suspend the NAND flash
3084 * @mtd: MTD device structure
3085 */
nand_suspend(struct mtd_info * mtd)3086 static int nand_suspend(struct mtd_info *mtd)
3087 {
3088 return nand_get_device(mtd, FL_PM_SUSPENDED);
3089 }
3090
3091 /**
3092 * nand_resume - [MTD Interface] Resume the NAND flash
3093 * @mtd: MTD device structure
3094 */
nand_resume(struct mtd_info * mtd)3095 static void nand_resume(struct mtd_info *mtd)
3096 {
3097 struct nand_chip *chip = mtd->priv;
3098
3099 if (chip->state == FL_PM_SUSPENDED)
3100 nand_release_device(mtd);
3101 else
3102 pr_err("%s called for a chip which is not in suspended state\n",
3103 __func__);
3104 }
3105
3106 /**
3107 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3108 * prevent further operations
3109 * @mtd: MTD device structure
3110 */
nand_shutdown(struct mtd_info * mtd)3111 static void nand_shutdown(struct mtd_info *mtd)
3112 {
3113 nand_get_device(mtd, FL_PM_SUSPENDED);
3114 }
3115
3116 /* Set default functions */
nand_set_defaults(struct nand_chip * chip,int busw)3117 static void nand_set_defaults(struct nand_chip *chip, int busw)
3118 {
3119 /* check for proper chip_delay setup, set 20us if not */
3120 if (!chip->chip_delay)
3121 chip->chip_delay = 20;
3122
3123 /* check, if a user supplied command function given */
3124 if (chip->cmdfunc == NULL)
3125 chip->cmdfunc = nand_command;
3126
3127 /* check, if a user supplied wait function given */
3128 if (chip->waitfunc == NULL)
3129 chip->waitfunc = nand_wait;
3130
3131 if (!chip->select_chip)
3132 chip->select_chip = nand_select_chip;
3133
3134 /* set for ONFI nand */
3135 if (!chip->onfi_set_features)
3136 chip->onfi_set_features = nand_onfi_set_features;
3137 if (!chip->onfi_get_features)
3138 chip->onfi_get_features = nand_onfi_get_features;
3139
3140 /* If called twice, pointers that depend on busw may need to be reset */
3141 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3142 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3143 if (!chip->read_word)
3144 chip->read_word = nand_read_word;
3145 if (!chip->block_bad)
3146 chip->block_bad = nand_block_bad;
3147 if (!chip->block_markbad)
3148 chip->block_markbad = nand_default_block_markbad;
3149 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3150 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3151 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3152 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3153 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3154 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3155 if (!chip->scan_bbt)
3156 chip->scan_bbt = nand_default_bbt;
3157
3158 if (!chip->controller) {
3159 chip->controller = &chip->hwcontrol;
3160 spin_lock_init(&chip->controller->lock);
3161 init_waitqueue_head(&chip->controller->wq);
3162 }
3163
3164 }
3165
3166 /* Sanitize ONFI strings so we can safely print them */
sanitize_string(uint8_t * s,size_t len)3167 static void sanitize_string(uint8_t *s, size_t len)
3168 {
3169 ssize_t i;
3170
3171 /* Null terminate */
3172 s[len - 1] = 0;
3173
3174 /* Remove non printable chars */
3175 for (i = 0; i < len - 1; i++) {
3176 if (s[i] < ' ' || s[i] > 127)
3177 s[i] = '?';
3178 }
3179
3180 /* Remove trailing spaces */
3181 strim(s);
3182 }
3183
onfi_crc16(u16 crc,u8 const * p,size_t len)3184 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3185 {
3186 int i;
3187 while (len--) {
3188 crc ^= *p++ << 8;
3189 for (i = 0; i < 8; i++)
3190 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3191 }
3192
3193 return crc;
3194 }
3195
3196 /* Parse the Extended Parameter Page. */
nand_flash_detect_ext_param_page(struct mtd_info * mtd,struct nand_chip * chip,struct nand_onfi_params * p)3197 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3198 struct nand_chip *chip, struct nand_onfi_params *p)
3199 {
3200 struct onfi_ext_param_page *ep;
3201 struct onfi_ext_section *s;
3202 struct onfi_ext_ecc_info *ecc;
3203 uint8_t *cursor;
3204 int ret = -EINVAL;
3205 int len;
3206 int i;
3207
3208 len = le16_to_cpu(p->ext_param_page_length) * 16;
3209 ep = kmalloc(len, GFP_KERNEL);
3210 if (!ep)
3211 return -ENOMEM;
3212
3213 /* Send our own NAND_CMD_PARAM. */
3214 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3215
3216 /* Use the Change Read Column command to skip the ONFI param pages. */
3217 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3218 sizeof(*p) * p->num_of_param_pages , -1);
3219
3220 /* Read out the Extended Parameter Page. */
3221 chip->read_buf(mtd, (uint8_t *)ep, len);
3222 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3223 != le16_to_cpu(ep->crc))) {
3224 pr_debug("fail in the CRC.\n");
3225 goto ext_out;
3226 }
3227
3228 /*
3229 * Check the signature.
3230 * Do not strictly follow the ONFI spec, maybe changed in future.
3231 */
3232 if (strncmp(ep->sig, "EPPS", 4)) {
3233 pr_debug("The signature is invalid.\n");
3234 goto ext_out;
3235 }
3236
3237 /* find the ECC section. */
3238 cursor = (uint8_t *)(ep + 1);
3239 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3240 s = ep->sections + i;
3241 if (s->type == ONFI_SECTION_TYPE_2)
3242 break;
3243 cursor += s->length * 16;
3244 }
3245 if (i == ONFI_EXT_SECTION_MAX) {
3246 pr_debug("We can not find the ECC section.\n");
3247 goto ext_out;
3248 }
3249
3250 /* get the info we want. */
3251 ecc = (struct onfi_ext_ecc_info *)cursor;
3252
3253 if (!ecc->codeword_size) {
3254 pr_debug("Invalid codeword size\n");
3255 goto ext_out;
3256 }
3257
3258 chip->ecc_strength_ds = ecc->ecc_bits;
3259 chip->ecc_step_ds = 1 << ecc->codeword_size;
3260 ret = 0;
3261
3262 ext_out:
3263 kfree(ep);
3264 return ret;
3265 }
3266
nand_setup_read_retry_micron(struct mtd_info * mtd,int retry_mode)3267 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3268 {
3269 struct nand_chip *chip = mtd->priv;
3270 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3271
3272 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3273 feature);
3274 }
3275
3276 /*
3277 * Configure chip properties from Micron vendor-specific ONFI table
3278 */
nand_onfi_detect_micron(struct nand_chip * chip,struct nand_onfi_params * p)3279 static void nand_onfi_detect_micron(struct nand_chip *chip,
3280 struct nand_onfi_params *p)
3281 {
3282 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3283
3284 if (le16_to_cpu(p->vendor_revision) < 1)
3285 return;
3286
3287 chip->read_retries = micron->read_retry_options;
3288 chip->setup_read_retry = nand_setup_read_retry_micron;
3289 }
3290
3291 /*
3292 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3293 */
nand_flash_detect_onfi(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3294 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3295 int *busw)
3296 {
3297 struct nand_onfi_params *p = &chip->onfi_params;
3298 int i, j;
3299 int val;
3300
3301 /* Try ONFI for unknown chip or LP */
3302 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3303 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3304 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3305 return 0;
3306
3307 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3308 for (i = 0; i < 3; i++) {
3309 for (j = 0; j < sizeof(*p); j++)
3310 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3311 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3312 le16_to_cpu(p->crc)) {
3313 break;
3314 }
3315 }
3316
3317 if (i == 3) {
3318 pr_err("Could not find valid ONFI parameter page; aborting\n");
3319 return 0;
3320 }
3321
3322 /* Check version */
3323 val = le16_to_cpu(p->revision);
3324 if (val & (1 << 5))
3325 chip->onfi_version = 23;
3326 else if (val & (1 << 4))
3327 chip->onfi_version = 22;
3328 else if (val & (1 << 3))
3329 chip->onfi_version = 21;
3330 else if (val & (1 << 2))
3331 chip->onfi_version = 20;
3332 else if (val & (1 << 1))
3333 chip->onfi_version = 10;
3334
3335 if (!chip->onfi_version) {
3336 pr_info("unsupported ONFI version: %d\n", val);
3337 return 0;
3338 }
3339
3340 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3341 sanitize_string(p->model, sizeof(p->model));
3342 if (!mtd->name)
3343 mtd->name = p->model;
3344
3345 mtd->writesize = le32_to_cpu(p->byte_per_page);
3346
3347 /*
3348 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3349 * (don't ask me who thought of this...). MTD assumes that these
3350 * dimensions will be power-of-2, so just truncate the remaining area.
3351 */
3352 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3353 mtd->erasesize *= mtd->writesize;
3354
3355 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3356
3357 /* See erasesize comment */
3358 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3359 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3360 chip->bits_per_cell = p->bits_per_cell;
3361
3362 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3363 *busw = NAND_BUSWIDTH_16;
3364 else
3365 *busw = 0;
3366
3367 if (p->ecc_bits != 0xff) {
3368 chip->ecc_strength_ds = p->ecc_bits;
3369 chip->ecc_step_ds = 512;
3370 } else if (chip->onfi_version >= 21 &&
3371 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3372
3373 /*
3374 * The nand_flash_detect_ext_param_page() uses the
3375 * Change Read Column command which maybe not supported
3376 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3377 * now. We do not replace user supplied command function.
3378 */
3379 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3380 chip->cmdfunc = nand_command_lp;
3381
3382 /* The Extended Parameter Page is supported since ONFI 2.1. */
3383 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3384 pr_warn("Failed to detect ONFI extended param page\n");
3385 } else {
3386 pr_warn("Could not retrieve ONFI ECC requirements\n");
3387 }
3388
3389 if (p->jedec_id == NAND_MFR_MICRON)
3390 nand_onfi_detect_micron(chip, p);
3391
3392 return 1;
3393 }
3394
3395 /*
3396 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3397 */
nand_flash_detect_jedec(struct mtd_info * mtd,struct nand_chip * chip,int * busw)3398 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3399 int *busw)
3400 {
3401 struct nand_jedec_params *p = &chip->jedec_params;
3402 struct jedec_ecc_info *ecc;
3403 int val;
3404 int i, j;
3405
3406 /* Try JEDEC for unknown chip or LP */
3407 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3408 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3409 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3410 chip->read_byte(mtd) != 'C')
3411 return 0;
3412
3413 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3414 for (i = 0; i < 3; i++) {
3415 for (j = 0; j < sizeof(*p); j++)
3416 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3417
3418 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3419 le16_to_cpu(p->crc))
3420 break;
3421 }
3422
3423 if (i == 3) {
3424 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3425 return 0;
3426 }
3427
3428 /* Check version */
3429 val = le16_to_cpu(p->revision);
3430 if (val & (1 << 2))
3431 chip->jedec_version = 10;
3432 else if (val & (1 << 1))
3433 chip->jedec_version = 1; /* vendor specific version */
3434
3435 if (!chip->jedec_version) {
3436 pr_info("unsupported JEDEC version: %d\n", val);
3437 return 0;
3438 }
3439
3440 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3441 sanitize_string(p->model, sizeof(p->model));
3442 if (!mtd->name)
3443 mtd->name = p->model;
3444
3445 mtd->writesize = le32_to_cpu(p->byte_per_page);
3446
3447 /* Please reference to the comment for nand_flash_detect_onfi. */
3448 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3449 mtd->erasesize *= mtd->writesize;
3450
3451 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3452
3453 /* Please reference to the comment for nand_flash_detect_onfi. */
3454 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3455 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3456 chip->bits_per_cell = p->bits_per_cell;
3457
3458 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3459 *busw = NAND_BUSWIDTH_16;
3460 else
3461 *busw = 0;
3462
3463 /* ECC info */
3464 ecc = &p->ecc_info[0];
3465
3466 if (ecc->codeword_size >= 9) {
3467 chip->ecc_strength_ds = ecc->ecc_bits;
3468 chip->ecc_step_ds = 1 << ecc->codeword_size;
3469 } else {
3470 pr_warn("Invalid codeword size\n");
3471 }
3472
3473 return 1;
3474 }
3475
3476 /*
3477 * nand_id_has_period - Check if an ID string has a given wraparound period
3478 * @id_data: the ID string
3479 * @arrlen: the length of the @id_data array
3480 * @period: the period of repitition
3481 *
3482 * Check if an ID string is repeated within a given sequence of bytes at
3483 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3484 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3485 * if the repetition has a period of @period; otherwise, returns zero.
3486 */
nand_id_has_period(u8 * id_data,int arrlen,int period)3487 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3488 {
3489 int i, j;
3490 for (i = 0; i < period; i++)
3491 for (j = i + period; j < arrlen; j += period)
3492 if (id_data[i] != id_data[j])
3493 return 0;
3494 return 1;
3495 }
3496
3497 /*
3498 * nand_id_len - Get the length of an ID string returned by CMD_READID
3499 * @id_data: the ID string
3500 * @arrlen: the length of the @id_data array
3501
3502 * Returns the length of the ID string, according to known wraparound/trailing
3503 * zero patterns. If no pattern exists, returns the length of the array.
3504 */
nand_id_len(u8 * id_data,int arrlen)3505 static int nand_id_len(u8 *id_data, int arrlen)
3506 {
3507 int last_nonzero, period;
3508
3509 /* Find last non-zero byte */
3510 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3511 if (id_data[last_nonzero])
3512 break;
3513
3514 /* All zeros */
3515 if (last_nonzero < 0)
3516 return 0;
3517
3518 /* Calculate wraparound period */
3519 for (period = 1; period < arrlen; period++)
3520 if (nand_id_has_period(id_data, arrlen, period))
3521 break;
3522
3523 /* There's a repeated pattern */
3524 if (period < arrlen)
3525 return period;
3526
3527 /* There are trailing zeros */
3528 if (last_nonzero < arrlen - 1)
3529 return last_nonzero + 1;
3530
3531 /* No pattern detected */
3532 return arrlen;
3533 }
3534
3535 /* Extract the bits of per cell from the 3rd byte of the extended ID */
nand_get_bits_per_cell(u8 cellinfo)3536 static int nand_get_bits_per_cell(u8 cellinfo)
3537 {
3538 int bits;
3539
3540 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3541 bits >>= NAND_CI_CELLTYPE_SHIFT;
3542 return bits + 1;
3543 }
3544
3545 /*
3546 * Many new NAND share similar device ID codes, which represent the size of the
3547 * chip. The rest of the parameters must be decoded according to generic or
3548 * manufacturer-specific "extended ID" decoding patterns.
3549 */
nand_decode_ext_id(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8],int * busw)3550 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3551 u8 id_data[8], int *busw)
3552 {
3553 int extid, id_len;
3554 /* The 3rd id byte holds MLC / multichip data */
3555 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3556 /* The 4th id byte is the important one */
3557 extid = id_data[3];
3558
3559 id_len = nand_id_len(id_data, 8);
3560
3561 /*
3562 * Field definitions are in the following datasheets:
3563 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3564 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3565 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3566 *
3567 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3568 * ID to decide what to do.
3569 */
3570 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3571 !nand_is_slc(chip) && id_data[5] != 0x00) {
3572 /* Calc pagesize */
3573 mtd->writesize = 2048 << (extid & 0x03);
3574 extid >>= 2;
3575 /* Calc oobsize */
3576 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3577 case 1:
3578 mtd->oobsize = 128;
3579 break;
3580 case 2:
3581 mtd->oobsize = 218;
3582 break;
3583 case 3:
3584 mtd->oobsize = 400;
3585 break;
3586 case 4:
3587 mtd->oobsize = 436;
3588 break;
3589 case 5:
3590 mtd->oobsize = 512;
3591 break;
3592 case 6:
3593 mtd->oobsize = 640;
3594 break;
3595 case 7:
3596 default: /* Other cases are "reserved" (unknown) */
3597 mtd->oobsize = 1024;
3598 break;
3599 }
3600 extid >>= 2;
3601 /* Calc blocksize */
3602 mtd->erasesize = (128 * 1024) <<
3603 (((extid >> 1) & 0x04) | (extid & 0x03));
3604 *busw = 0;
3605 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3606 !nand_is_slc(chip)) {
3607 unsigned int tmp;
3608
3609 /* Calc pagesize */
3610 mtd->writesize = 2048 << (extid & 0x03);
3611 extid >>= 2;
3612 /* Calc oobsize */
3613 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3614 case 0:
3615 mtd->oobsize = 128;
3616 break;
3617 case 1:
3618 mtd->oobsize = 224;
3619 break;
3620 case 2:
3621 mtd->oobsize = 448;
3622 break;
3623 case 3:
3624 mtd->oobsize = 64;
3625 break;
3626 case 4:
3627 mtd->oobsize = 32;
3628 break;
3629 case 5:
3630 mtd->oobsize = 16;
3631 break;
3632 default:
3633 mtd->oobsize = 640;
3634 break;
3635 }
3636 extid >>= 2;
3637 /* Calc blocksize */
3638 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3639 if (tmp < 0x03)
3640 mtd->erasesize = (128 * 1024) << tmp;
3641 else if (tmp == 0x03)
3642 mtd->erasesize = 768 * 1024;
3643 else
3644 mtd->erasesize = (64 * 1024) << tmp;
3645 *busw = 0;
3646 } else {
3647 /* Calc pagesize */
3648 mtd->writesize = 1024 << (extid & 0x03);
3649 extid >>= 2;
3650 /* Calc oobsize */
3651 mtd->oobsize = (8 << (extid & 0x01)) *
3652 (mtd->writesize >> 9);
3653 extid >>= 2;
3654 /* Calc blocksize. Blocksize is multiples of 64KiB */
3655 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3656 extid >>= 2;
3657 /* Get buswidth information */
3658 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3659
3660 /*
3661 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3662 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3663 * follows:
3664 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3665 * 110b -> 24nm
3666 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3667 */
3668 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3669 nand_is_slc(chip) &&
3670 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3671 !(id_data[4] & 0x80) /* !BENAND */) {
3672 mtd->oobsize = 32 * mtd->writesize >> 9;
3673 }
3674
3675 }
3676 }
3677
3678 /*
3679 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3680 * decodes a matching ID table entry and assigns the MTD size parameters for
3681 * the chip.
3682 */
nand_decode_id(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 id_data[8],int * busw)3683 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3684 struct nand_flash_dev *type, u8 id_data[8],
3685 int *busw)
3686 {
3687 int maf_id = id_data[0];
3688
3689 mtd->erasesize = type->erasesize;
3690 mtd->writesize = type->pagesize;
3691 mtd->oobsize = mtd->writesize / 32;
3692 *busw = type->options & NAND_BUSWIDTH_16;
3693
3694 /* All legacy ID NAND are small-page, SLC */
3695 chip->bits_per_cell = 1;
3696
3697 /*
3698 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3699 * some Spansion chips have erasesize that conflicts with size
3700 * listed in nand_ids table.
3701 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3702 */
3703 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3704 && id_data[6] == 0x00 && id_data[7] == 0x00
3705 && mtd->writesize == 512) {
3706 mtd->erasesize = 128 * 1024;
3707 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3708 }
3709 }
3710
3711 /*
3712 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3713 * heuristic patterns using various detected parameters (e.g., manufacturer,
3714 * page size, cell-type information).
3715 */
nand_decode_bbm_options(struct mtd_info * mtd,struct nand_chip * chip,u8 id_data[8])3716 static void nand_decode_bbm_options(struct mtd_info *mtd,
3717 struct nand_chip *chip, u8 id_data[8])
3718 {
3719 int maf_id = id_data[0];
3720
3721 /* Set the bad block position */
3722 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3723 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3724 else
3725 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3726
3727 /*
3728 * Bad block marker is stored in the last page of each block on Samsung
3729 * and Hynix MLC devices; stored in first two pages of each block on
3730 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3731 * AMD/Spansion, and Macronix. All others scan only the first page.
3732 */
3733 if (!nand_is_slc(chip) &&
3734 (maf_id == NAND_MFR_SAMSUNG ||
3735 maf_id == NAND_MFR_HYNIX))
3736 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3737 else if ((nand_is_slc(chip) &&
3738 (maf_id == NAND_MFR_SAMSUNG ||
3739 maf_id == NAND_MFR_HYNIX ||
3740 maf_id == NAND_MFR_TOSHIBA ||
3741 maf_id == NAND_MFR_AMD ||
3742 maf_id == NAND_MFR_MACRONIX)) ||
3743 (mtd->writesize == 2048 &&
3744 maf_id == NAND_MFR_MICRON))
3745 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3746 }
3747
is_full_id_nand(struct nand_flash_dev * type)3748 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3749 {
3750 return type->id_len;
3751 }
3752
find_full_id_nand(struct mtd_info * mtd,struct nand_chip * chip,struct nand_flash_dev * type,u8 * id_data,int * busw)3753 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3754 struct nand_flash_dev *type, u8 *id_data, int *busw)
3755 {
3756 if (!strncmp(type->id, id_data, type->id_len)) {
3757 mtd->writesize = type->pagesize;
3758 mtd->erasesize = type->erasesize;
3759 mtd->oobsize = type->oobsize;
3760
3761 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3762 chip->chipsize = (uint64_t)type->chipsize << 20;
3763 chip->options |= type->options;
3764 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3765 chip->ecc_step_ds = NAND_ECC_STEP(type);
3766 chip->onfi_timing_mode_default =
3767 type->onfi_timing_mode_default;
3768
3769 *busw = type->options & NAND_BUSWIDTH_16;
3770
3771 if (!mtd->name)
3772 mtd->name = type->name;
3773
3774 return true;
3775 }
3776 return false;
3777 }
3778
3779 /*
3780 * Get the flash and manufacturer id and lookup if the type is supported.
3781 */
nand_get_flash_type(struct mtd_info * mtd,struct nand_chip * chip,int * maf_id,int * dev_id,struct nand_flash_dev * type)3782 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3783 struct nand_chip *chip,
3784 int *maf_id, int *dev_id,
3785 struct nand_flash_dev *type)
3786 {
3787 int busw;
3788 int i, maf_idx;
3789 u8 id_data[8];
3790
3791 /* Select the device */
3792 chip->select_chip(mtd, 0);
3793
3794 /*
3795 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3796 * after power-up.
3797 */
3798 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3799
3800 /* Send the command for reading device ID */
3801 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3802
3803 /* Read manufacturer and device IDs */
3804 *maf_id = chip->read_byte(mtd);
3805 *dev_id = chip->read_byte(mtd);
3806
3807 /*
3808 * Try again to make sure, as some systems the bus-hold or other
3809 * interface concerns can cause random data which looks like a
3810 * possibly credible NAND flash to appear. If the two results do
3811 * not match, ignore the device completely.
3812 */
3813
3814 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3815
3816 /* Read entire ID string */
3817 for (i = 0; i < 8; i++)
3818 id_data[i] = chip->read_byte(mtd);
3819
3820 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3821 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3822 *maf_id, *dev_id, id_data[0], id_data[1]);
3823 return ERR_PTR(-ENODEV);
3824 }
3825
3826 if (!type)
3827 type = nand_flash_ids;
3828
3829 for (; type->name != NULL; type++) {
3830 if (is_full_id_nand(type)) {
3831 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3832 goto ident_done;
3833 } else if (*dev_id == type->dev_id) {
3834 break;
3835 }
3836 }
3837
3838 chip->onfi_version = 0;
3839 if (!type->name || !type->pagesize) {
3840 /* Check if the chip is ONFI compliant */
3841 if (nand_flash_detect_onfi(mtd, chip, &busw))
3842 goto ident_done;
3843
3844 /* Check if the chip is JEDEC compliant */
3845 if (nand_flash_detect_jedec(mtd, chip, &busw))
3846 goto ident_done;
3847 }
3848
3849 if (!type->name)
3850 return ERR_PTR(-ENODEV);
3851
3852 if (!mtd->name)
3853 mtd->name = type->name;
3854
3855 chip->chipsize = (uint64_t)type->chipsize << 20;
3856
3857 if (!type->pagesize) {
3858 /* Decode parameters from extended ID */
3859 nand_decode_ext_id(mtd, chip, id_data, &busw);
3860 } else {
3861 nand_decode_id(mtd, chip, type, id_data, &busw);
3862 }
3863 /* Get chip options */
3864 chip->options |= type->options;
3865
3866 /*
3867 * Check if chip is not a Samsung device. Do not clear the
3868 * options for chips which do not have an extended id.
3869 */
3870 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3871 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3872 ident_done:
3873
3874 /* Try to identify manufacturer */
3875 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3876 if (nand_manuf_ids[maf_idx].id == *maf_id)
3877 break;
3878 }
3879
3880 if (chip->options & NAND_BUSWIDTH_AUTO) {
3881 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3882 chip->options |= busw;
3883 nand_set_defaults(chip, busw);
3884 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3885 /*
3886 * Check, if buswidth is correct. Hardware drivers should set
3887 * chip correct!
3888 */
3889 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3890 *maf_id, *dev_id);
3891 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3892 pr_warn("bus width %d instead %d bit\n",
3893 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3894 busw ? 16 : 8);
3895 return ERR_PTR(-EINVAL);
3896 }
3897
3898 nand_decode_bbm_options(mtd, chip, id_data);
3899
3900 /* Calculate the address shift from the page size */
3901 chip->page_shift = ffs(mtd->writesize) - 1;
3902 /* Convert chipsize to number of pages per chip -1 */
3903 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3904
3905 chip->bbt_erase_shift = chip->phys_erase_shift =
3906 ffs(mtd->erasesize) - 1;
3907 if (chip->chipsize & 0xffffffff)
3908 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3909 else {
3910 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3911 chip->chip_shift += 32 - 1;
3912 }
3913
3914 chip->badblockbits = 8;
3915 chip->erase = single_erase;
3916
3917 /* Do not replace user supplied command function! */
3918 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3919 chip->cmdfunc = nand_command_lp;
3920
3921 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3922 *maf_id, *dev_id);
3923
3924 if (chip->onfi_version)
3925 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3926 chip->onfi_params.model);
3927 else if (chip->jedec_version)
3928 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3929 chip->jedec_params.model);
3930 else
3931 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3932 type->name);
3933
3934 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3935 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3936 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3937 return type;
3938 }
3939
nand_dt_init(struct mtd_info * mtd,struct nand_chip * chip,struct device_node * dn)3940 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip,
3941 struct device_node *dn)
3942 {
3943 int ecc_mode, ecc_strength, ecc_step;
3944
3945 if (of_get_nand_bus_width(dn) == 16)
3946 chip->options |= NAND_BUSWIDTH_16;
3947
3948 if (of_get_nand_on_flash_bbt(dn))
3949 chip->bbt_options |= NAND_BBT_USE_FLASH;
3950
3951 ecc_mode = of_get_nand_ecc_mode(dn);
3952 ecc_strength = of_get_nand_ecc_strength(dn);
3953 ecc_step = of_get_nand_ecc_step_size(dn);
3954
3955 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3956 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3957 pr_err("must set both strength and step size in DT\n");
3958 return -EINVAL;
3959 }
3960
3961 if (ecc_mode >= 0)
3962 chip->ecc.mode = ecc_mode;
3963
3964 if (ecc_strength >= 0)
3965 chip->ecc.strength = ecc_strength;
3966
3967 if (ecc_step > 0)
3968 chip->ecc.size = ecc_step;
3969
3970 return 0;
3971 }
3972
3973 /**
3974 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3975 * @mtd: MTD device structure
3976 * @maxchips: number of chips to scan for
3977 * @table: alternative NAND ID table
3978 *
3979 * This is the first phase of the normal nand_scan() function. It reads the
3980 * flash ID and sets up MTD fields accordingly.
3981 *
3982 */
nand_scan_ident(struct mtd_info * mtd,int maxchips,struct nand_flash_dev * table)3983 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3984 struct nand_flash_dev *table)
3985 {
3986 int i, nand_maf_id, nand_dev_id;
3987 struct nand_chip *chip = mtd->priv;
3988 struct nand_flash_dev *type;
3989 int ret;
3990
3991 if (chip->flash_node) {
3992 ret = nand_dt_init(mtd, chip, chip->flash_node);
3993 if (ret)
3994 return ret;
3995 }
3996
3997 if (!mtd->name && mtd->dev.parent)
3998 mtd->name = dev_name(mtd->dev.parent);
3999
4000 /* Set the default functions */
4001 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4002
4003 /* Read the flash type */
4004 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4005 &nand_dev_id, table);
4006
4007 if (IS_ERR(type)) {
4008 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4009 pr_warn("No NAND device found\n");
4010 chip->select_chip(mtd, -1);
4011 return PTR_ERR(type);
4012 }
4013
4014 chip->select_chip(mtd, -1);
4015
4016 /* Check for a chip array */
4017 for (i = 1; i < maxchips; i++) {
4018 chip->select_chip(mtd, i);
4019 /* See comment in nand_get_flash_type for reset */
4020 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4021 /* Send the command for reading device ID */
4022 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4023 /* Read manufacturer and device IDs */
4024 if (nand_maf_id != chip->read_byte(mtd) ||
4025 nand_dev_id != chip->read_byte(mtd)) {
4026 chip->select_chip(mtd, -1);
4027 break;
4028 }
4029 chip->select_chip(mtd, -1);
4030 }
4031 if (i > 1)
4032 pr_info("%d chips detected\n", i);
4033
4034 /* Store the number of chips and calc total size for mtd */
4035 chip->numchips = i;
4036 mtd->size = i * chip->chipsize;
4037
4038 return 0;
4039 }
4040 EXPORT_SYMBOL(nand_scan_ident);
4041
4042 /*
4043 * Check if the chip configuration meet the datasheet requirements.
4044
4045 * If our configuration corrects A bits per B bytes and the minimum
4046 * required correction level is X bits per Y bytes, then we must ensure
4047 * both of the following are true:
4048 *
4049 * (1) A / B >= X / Y
4050 * (2) A >= X
4051 *
4052 * Requirement (1) ensures we can correct for the required bitflip density.
4053 * Requirement (2) ensures we can correct even when all bitflips are clumped
4054 * in the same sector.
4055 */
nand_ecc_strength_good(struct mtd_info * mtd)4056 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4057 {
4058 struct nand_chip *chip = mtd->priv;
4059 struct nand_ecc_ctrl *ecc = &chip->ecc;
4060 int corr, ds_corr;
4061
4062 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4063 /* Not enough information */
4064 return true;
4065
4066 /*
4067 * We get the number of corrected bits per page to compare
4068 * the correction density.
4069 */
4070 corr = (mtd->writesize * ecc->strength) / ecc->size;
4071 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4072
4073 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4074 }
4075
4076 /**
4077 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4078 * @mtd: MTD device structure
4079 *
4080 * This is the second phase of the normal nand_scan() function. It fills out
4081 * all the uninitialized function pointers with the defaults and scans for a
4082 * bad block table if appropriate.
4083 */
nand_scan_tail(struct mtd_info * mtd)4084 int nand_scan_tail(struct mtd_info *mtd)
4085 {
4086 int i;
4087 struct nand_chip *chip = mtd->priv;
4088 struct nand_ecc_ctrl *ecc = &chip->ecc;
4089 struct nand_buffers *nbuf;
4090
4091 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4092 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4093 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4094
4095 if (!(chip->options & NAND_OWN_BUFFERS)) {
4096 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4097 + mtd->oobsize * 3, GFP_KERNEL);
4098 if (!nbuf)
4099 return -ENOMEM;
4100 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4101 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4102 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4103
4104 chip->buffers = nbuf;
4105 } else {
4106 if (!chip->buffers)
4107 return -ENOMEM;
4108 }
4109
4110 /* Set the internal oob buffer location, just after the page data */
4111 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4112
4113 /*
4114 * If no default placement scheme is given, select an appropriate one.
4115 */
4116 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4117 switch (mtd->oobsize) {
4118 case 8:
4119 ecc->layout = &nand_oob_8;
4120 break;
4121 case 16:
4122 ecc->layout = &nand_oob_16;
4123 break;
4124 case 64:
4125 ecc->layout = &nand_oob_64;
4126 break;
4127 case 128:
4128 ecc->layout = &nand_oob_128;
4129 break;
4130 default:
4131 pr_warn("No oob scheme defined for oobsize %d\n",
4132 mtd->oobsize);
4133 BUG();
4134 }
4135 }
4136
4137 if (!chip->write_page)
4138 chip->write_page = nand_write_page;
4139
4140 /*
4141 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4142 * selected and we have 256 byte pagesize fallback to software ECC
4143 */
4144
4145 switch (ecc->mode) {
4146 case NAND_ECC_HW_OOB_FIRST:
4147 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4148 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4149 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4150 BUG();
4151 }
4152 if (!ecc->read_page)
4153 ecc->read_page = nand_read_page_hwecc_oob_first;
4154
4155 case NAND_ECC_HW:
4156 /* Use standard hwecc read page function? */
4157 if (!ecc->read_page)
4158 ecc->read_page = nand_read_page_hwecc;
4159 if (!ecc->write_page)
4160 ecc->write_page = nand_write_page_hwecc;
4161 if (!ecc->read_page_raw)
4162 ecc->read_page_raw = nand_read_page_raw;
4163 if (!ecc->write_page_raw)
4164 ecc->write_page_raw = nand_write_page_raw;
4165 if (!ecc->read_oob)
4166 ecc->read_oob = nand_read_oob_std;
4167 if (!ecc->write_oob)
4168 ecc->write_oob = nand_write_oob_std;
4169 if (!ecc->read_subpage)
4170 ecc->read_subpage = nand_read_subpage;
4171 if (!ecc->write_subpage)
4172 ecc->write_subpage = nand_write_subpage_hwecc;
4173
4174 case NAND_ECC_HW_SYNDROME:
4175 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4176 (!ecc->read_page ||
4177 ecc->read_page == nand_read_page_hwecc ||
4178 !ecc->write_page ||
4179 ecc->write_page == nand_write_page_hwecc)) {
4180 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4181 BUG();
4182 }
4183 /* Use standard syndrome read/write page function? */
4184 if (!ecc->read_page)
4185 ecc->read_page = nand_read_page_syndrome;
4186 if (!ecc->write_page)
4187 ecc->write_page = nand_write_page_syndrome;
4188 if (!ecc->read_page_raw)
4189 ecc->read_page_raw = nand_read_page_raw_syndrome;
4190 if (!ecc->write_page_raw)
4191 ecc->write_page_raw = nand_write_page_raw_syndrome;
4192 if (!ecc->read_oob)
4193 ecc->read_oob = nand_read_oob_syndrome;
4194 if (!ecc->write_oob)
4195 ecc->write_oob = nand_write_oob_syndrome;
4196
4197 if (mtd->writesize >= ecc->size) {
4198 if (!ecc->strength) {
4199 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4200 BUG();
4201 }
4202 break;
4203 }
4204 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4205 ecc->size, mtd->writesize);
4206 ecc->mode = NAND_ECC_SOFT;
4207
4208 case NAND_ECC_SOFT:
4209 ecc->calculate = nand_calculate_ecc;
4210 ecc->correct = nand_correct_data;
4211 ecc->read_page = nand_read_page_swecc;
4212 ecc->read_subpage = nand_read_subpage;
4213 ecc->write_page = nand_write_page_swecc;
4214 ecc->read_page_raw = nand_read_page_raw;
4215 ecc->write_page_raw = nand_write_page_raw;
4216 ecc->read_oob = nand_read_oob_std;
4217 ecc->write_oob = nand_write_oob_std;
4218 if (!ecc->size)
4219 ecc->size = 256;
4220 ecc->bytes = 3;
4221 ecc->strength = 1;
4222 break;
4223
4224 case NAND_ECC_SOFT_BCH:
4225 if (!mtd_nand_has_bch()) {
4226 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4227 BUG();
4228 }
4229 ecc->calculate = nand_bch_calculate_ecc;
4230 ecc->correct = nand_bch_correct_data;
4231 ecc->read_page = nand_read_page_swecc;
4232 ecc->read_subpage = nand_read_subpage;
4233 ecc->write_page = nand_write_page_swecc;
4234 ecc->read_page_raw = nand_read_page_raw;
4235 ecc->write_page_raw = nand_write_page_raw;
4236 ecc->read_oob = nand_read_oob_std;
4237 ecc->write_oob = nand_write_oob_std;
4238 /*
4239 * Board driver should supply ecc.size and ecc.strength values
4240 * to select how many bits are correctable. Otherwise, default
4241 * to 4 bits for large page devices.
4242 */
4243 if (!ecc->size && (mtd->oobsize >= 64)) {
4244 ecc->size = 512;
4245 ecc->strength = 4;
4246 }
4247
4248 /* See nand_bch_init() for details. */
4249 ecc->bytes = DIV_ROUND_UP(
4250 ecc->strength * fls(8 * ecc->size), 8);
4251 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4252 &ecc->layout);
4253 if (!ecc->priv) {
4254 pr_warn("BCH ECC initialization failed!\n");
4255 BUG();
4256 }
4257 break;
4258
4259 case NAND_ECC_NONE:
4260 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4261 ecc->read_page = nand_read_page_raw;
4262 ecc->write_page = nand_write_page_raw;
4263 ecc->read_oob = nand_read_oob_std;
4264 ecc->read_page_raw = nand_read_page_raw;
4265 ecc->write_page_raw = nand_write_page_raw;
4266 ecc->write_oob = nand_write_oob_std;
4267 ecc->size = mtd->writesize;
4268 ecc->bytes = 0;
4269 ecc->strength = 0;
4270 break;
4271
4272 default:
4273 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4274 BUG();
4275 }
4276
4277 /* For many systems, the standard OOB write also works for raw */
4278 if (!ecc->read_oob_raw)
4279 ecc->read_oob_raw = ecc->read_oob;
4280 if (!ecc->write_oob_raw)
4281 ecc->write_oob_raw = ecc->write_oob;
4282
4283 /*
4284 * The number of bytes available for a client to place data into
4285 * the out of band area.
4286 */
4287 ecc->layout->oobavail = 0;
4288 for (i = 0; ecc->layout->oobfree[i].length
4289 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4290 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4291 mtd->oobavail = ecc->layout->oobavail;
4292
4293 /* ECC sanity check: warn if it's too weak */
4294 if (!nand_ecc_strength_good(mtd))
4295 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4296 mtd->name);
4297
4298 /*
4299 * Set the number of read / write steps for one page depending on ECC
4300 * mode.
4301 */
4302 ecc->steps = mtd->writesize / ecc->size;
4303 if (ecc->steps * ecc->size != mtd->writesize) {
4304 pr_warn("Invalid ECC parameters\n");
4305 BUG();
4306 }
4307 ecc->total = ecc->steps * ecc->bytes;
4308
4309 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4310 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4311 switch (ecc->steps) {
4312 case 2:
4313 mtd->subpage_sft = 1;
4314 break;
4315 case 4:
4316 case 8:
4317 case 16:
4318 mtd->subpage_sft = 2;
4319 break;
4320 }
4321 }
4322 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4323
4324 /* Initialize state */
4325 chip->state = FL_READY;
4326
4327 /* Invalidate the pagebuffer reference */
4328 chip->pagebuf = -1;
4329
4330 /* Large page NAND with SOFT_ECC should support subpage reads */
4331 switch (ecc->mode) {
4332 case NAND_ECC_SOFT:
4333 case NAND_ECC_SOFT_BCH:
4334 if (chip->page_shift > 9)
4335 chip->options |= NAND_SUBPAGE_READ;
4336 break;
4337
4338 default:
4339 break;
4340 }
4341
4342 /* Fill in remaining MTD driver data */
4343 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4344 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4345 MTD_CAP_NANDFLASH;
4346 mtd->_erase = nand_erase;
4347 mtd->_point = NULL;
4348 mtd->_unpoint = NULL;
4349 mtd->_read = nand_read;
4350 mtd->_write = nand_write;
4351 mtd->_panic_write = panic_nand_write;
4352 mtd->_read_oob = nand_read_oob;
4353 mtd->_write_oob = nand_write_oob;
4354 mtd->_sync = nand_sync;
4355 mtd->_lock = NULL;
4356 mtd->_unlock = NULL;
4357 mtd->_suspend = nand_suspend;
4358 mtd->_resume = nand_resume;
4359 mtd->_reboot = nand_shutdown;
4360 mtd->_block_isreserved = nand_block_isreserved;
4361 mtd->_block_isbad = nand_block_isbad;
4362 mtd->_block_markbad = nand_block_markbad;
4363 mtd->writebufsize = mtd->writesize;
4364
4365 /* propagate ecc info to mtd_info */
4366 mtd->ecclayout = ecc->layout;
4367 mtd->ecc_strength = ecc->strength;
4368 mtd->ecc_step_size = ecc->size;
4369 /*
4370 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4371 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4372 * properly set.
4373 */
4374 if (!mtd->bitflip_threshold)
4375 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4376
4377 /* Check, if we should skip the bad block table scan */
4378 if (chip->options & NAND_SKIP_BBTSCAN)
4379 return 0;
4380
4381 /* Build bad block table */
4382 return chip->scan_bbt(mtd);
4383 }
4384 EXPORT_SYMBOL(nand_scan_tail);
4385
4386 /*
4387 * is_module_text_address() isn't exported, and it's mostly a pointless
4388 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4389 * to call us from in-kernel code if the core NAND support is modular.
4390 */
4391 #ifdef MODULE
4392 #define caller_is_module() (1)
4393 #else
4394 #define caller_is_module() \
4395 is_module_text_address((unsigned long)__builtin_return_address(0))
4396 #endif
4397
4398 /**
4399 * nand_scan - [NAND Interface] Scan for the NAND device
4400 * @mtd: MTD device structure
4401 * @maxchips: number of chips to scan for
4402 *
4403 * This fills out all the uninitialized function pointers with the defaults.
4404 * The flash ID is read and the mtd/chip structures are filled with the
4405 * appropriate values.
4406 */
nand_scan(struct mtd_info * mtd,int maxchips)4407 int nand_scan(struct mtd_info *mtd, int maxchips)
4408 {
4409 int ret;
4410
4411 ret = nand_scan_ident(mtd, maxchips, NULL);
4412 if (!ret)
4413 ret = nand_scan_tail(mtd);
4414 return ret;
4415 }
4416 EXPORT_SYMBOL(nand_scan);
4417
4418 /**
4419 * nand_release - [NAND Interface] Free resources held by the NAND device
4420 * @mtd: MTD device structure
4421 */
nand_release(struct mtd_info * mtd)4422 void nand_release(struct mtd_info *mtd)
4423 {
4424 struct nand_chip *chip = mtd->priv;
4425
4426 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4427 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4428
4429 mtd_device_unregister(mtd);
4430
4431 /* Free bad block table memory */
4432 kfree(chip->bbt);
4433 if (!(chip->options & NAND_OWN_BUFFERS))
4434 kfree(chip->buffers);
4435
4436 /* Free bad block descriptor memory */
4437 if (chip->badblock_pattern && chip->badblock_pattern->options
4438 & NAND_BBT_DYNAMICSTRUCT)
4439 kfree(chip->badblock_pattern);
4440 }
4441 EXPORT_SYMBOL_GPL(nand_release);
4442
nand_base_init(void)4443 static int __init nand_base_init(void)
4444 {
4445 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4446 return 0;
4447 }
4448
nand_base_exit(void)4449 static void __exit nand_base_exit(void)
4450 {
4451 led_trigger_unregister_simple(nand_led_trigger);
4452 }
4453
4454 module_init(nand_base_init);
4455 module_exit(nand_base_exit);
4456
4457 MODULE_LICENSE("GPL");
4458 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4459 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4460 MODULE_DESCRIPTION("Generic NAND flash driver code");
4461