1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/random.h>
36 #include <linux/vmalloc.h>
37 #include <linux/hardirq.h>
38 #include <linux/mlx5/driver.h>
39 #include <linux/mlx5/cmd.h>
40 #include "mlx5_core.h"
41
42 enum {
43 MLX5_HEALTH_POLL_INTERVAL = 2 * HZ,
44 MAX_MISSES = 3,
45 };
46
47 enum {
48 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
49 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
50 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
51 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
52 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
53 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
54 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
55 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
56 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
57 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
58 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10
59 };
60
61 enum {
62 MLX5_NIC_IFC_FULL = 0,
63 MLX5_NIC_IFC_DISABLED = 1,
64 MLX5_NIC_IFC_NO_DRAM_NIC = 2
65 };
66
get_nic_interface(struct mlx5_core_dev * dev)67 static u8 get_nic_interface(struct mlx5_core_dev *dev)
68 {
69 return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
70 }
71
trigger_cmd_completions(struct mlx5_core_dev * dev)72 static void trigger_cmd_completions(struct mlx5_core_dev *dev)
73 {
74 unsigned long flags;
75 u64 vector;
76
77 /* wait for pending handlers to complete */
78 synchronize_irq(dev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector);
79 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
80 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
81 if (!vector)
82 goto no_trig;
83
84 vector |= MLX5_TRIGGERED_CMD_COMP;
85 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
86
87 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
88 mlx5_cmd_comp_handler(dev, vector);
89 return;
90
91 no_trig:
92 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
93 }
94
in_fatal(struct mlx5_core_dev * dev)95 static int in_fatal(struct mlx5_core_dev *dev)
96 {
97 struct mlx5_core_health *health = &dev->priv.health;
98 struct health_buffer __iomem *h = health->health;
99
100 if (get_nic_interface(dev) == MLX5_NIC_IFC_DISABLED)
101 return 1;
102
103 if (ioread32be(&h->fw_ver) == 0xffffffff)
104 return 1;
105
106 return 0;
107 }
108
mlx5_enter_error_state(struct mlx5_core_dev * dev)109 void mlx5_enter_error_state(struct mlx5_core_dev *dev)
110 {
111 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
112 return;
113
114 mlx5_core_err(dev, "start\n");
115 if (pci_channel_offline(dev->pdev) || in_fatal(dev))
116 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
117
118 mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0);
119 mlx5_core_err(dev, "end\n");
120 }
121
mlx5_handle_bad_state(struct mlx5_core_dev * dev)122 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
123 {
124 u8 nic_interface = get_nic_interface(dev);
125
126 switch (nic_interface) {
127 case MLX5_NIC_IFC_FULL:
128 mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
129 break;
130
131 case MLX5_NIC_IFC_DISABLED:
132 mlx5_core_warn(dev, "starting teardown\n");
133 break;
134
135 case MLX5_NIC_IFC_NO_DRAM_NIC:
136 mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
137 break;
138 default:
139 mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
140 nic_interface);
141 }
142
143 mlx5_disable_device(dev);
144 }
145
health_care(struct work_struct * work)146 static void health_care(struct work_struct *work)
147 {
148 struct mlx5_core_health *health;
149 struct mlx5_core_dev *dev;
150 struct mlx5_priv *priv;
151
152 health = container_of(work, struct mlx5_core_health, work);
153 priv = container_of(health, struct mlx5_priv, health);
154 dev = container_of(priv, struct mlx5_core_dev, priv);
155 mlx5_core_warn(dev, "handling bad device here\n");
156 mlx5_handle_bad_state(dev);
157 }
158
hsynd_str(u8 synd)159 static const char *hsynd_str(u8 synd)
160 {
161 switch (synd) {
162 case MLX5_HEALTH_SYNDR_FW_ERR:
163 return "firmware internal error";
164 case MLX5_HEALTH_SYNDR_IRISC_ERR:
165 return "irisc not responding";
166 case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
167 return "unrecoverable hardware error";
168 case MLX5_HEALTH_SYNDR_CRC_ERR:
169 return "firmware CRC error";
170 case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
171 return "ICM fetch PCI error";
172 case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
173 return "HW fatal error\n";
174 case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
175 return "async EQ buffer overrun";
176 case MLX5_HEALTH_SYNDR_EQ_ERR:
177 return "EQ error";
178 case MLX5_HEALTH_SYNDR_EQ_INV:
179 return "Invalid EQ refrenced";
180 case MLX5_HEALTH_SYNDR_FFSER_ERR:
181 return "FFSER error";
182 case MLX5_HEALTH_SYNDR_HIGH_TEMP:
183 return "High temprature";
184 default:
185 return "unrecognized error";
186 }
187 }
188
get_maj(u32 fw)189 static u16 get_maj(u32 fw)
190 {
191 return fw >> 28;
192 }
193
get_min(u32 fw)194 static u16 get_min(u32 fw)
195 {
196 return fw >> 16 & 0xfff;
197 }
198
get_sub(u32 fw)199 static u16 get_sub(u32 fw)
200 {
201 return fw & 0xffff;
202 }
203
print_health_info(struct mlx5_core_dev * dev)204 static void print_health_info(struct mlx5_core_dev *dev)
205 {
206 struct mlx5_core_health *health = &dev->priv.health;
207 struct health_buffer __iomem *h = health->health;
208 char fw_str[18];
209 u32 fw;
210 int i;
211
212 /* If the syndrom is 0, the device is OK and no need to print buffer */
213 if (!ioread8(&h->synd))
214 return;
215
216 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
217 dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));
218
219 dev_err(&dev->pdev->dev, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr));
220 dev_err(&dev->pdev->dev, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra));
221 fw = ioread32be(&h->fw_ver);
222 sprintf(fw_str, "%d.%d.%d", get_maj(fw), get_min(fw), get_sub(fw));
223 dev_err(&dev->pdev->dev, "fw_ver %s\n", fw_str);
224 dev_err(&dev->pdev->dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
225 dev_err(&dev->pdev->dev, "irisc_index %d\n", ioread8(&h->irisc_index));
226 dev_err(&dev->pdev->dev, "synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd)));
227 dev_err(&dev->pdev->dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
228 }
229
get_next_poll_jiffies(void)230 static unsigned long get_next_poll_jiffies(void)
231 {
232 unsigned long next;
233
234 get_random_bytes(&next, sizeof(next));
235 next %= HZ;
236 next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
237
238 return next;
239 }
240
poll_health(unsigned long data)241 static void poll_health(unsigned long data)
242 {
243 struct mlx5_core_dev *dev = (struct mlx5_core_dev *)data;
244 struct mlx5_core_health *health = &dev->priv.health;
245 u32 count;
246
247 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
248 trigger_cmd_completions(dev);
249 mod_timer(&health->timer, get_next_poll_jiffies());
250 return;
251 }
252
253 count = ioread32be(health->health_counter);
254 if (count == health->prev)
255 ++health->miss_counter;
256 else
257 health->miss_counter = 0;
258
259 health->prev = count;
260 if (health->miss_counter == MAX_MISSES) {
261 dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
262 print_health_info(dev);
263 } else {
264 mod_timer(&health->timer, get_next_poll_jiffies());
265 }
266
267 if (in_fatal(dev) && !health->sick) {
268 health->sick = true;
269 print_health_info(dev);
270 queue_work(health->wq, &health->work);
271 }
272 }
273
mlx5_start_health_poll(struct mlx5_core_dev * dev)274 void mlx5_start_health_poll(struct mlx5_core_dev *dev)
275 {
276 struct mlx5_core_health *health = &dev->priv.health;
277
278 init_timer(&health->timer);
279 health->health = &dev->iseg->health;
280 health->health_counter = &dev->iseg->health_counter;
281
282 health->timer.data = (unsigned long)dev;
283 health->timer.function = poll_health;
284 health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
285 add_timer(&health->timer);
286 }
287
mlx5_stop_health_poll(struct mlx5_core_dev * dev)288 void mlx5_stop_health_poll(struct mlx5_core_dev *dev)
289 {
290 struct mlx5_core_health *health = &dev->priv.health;
291
292 del_timer_sync(&health->timer);
293 }
294
mlx5_health_cleanup(struct mlx5_core_dev * dev)295 void mlx5_health_cleanup(struct mlx5_core_dev *dev)
296 {
297 struct mlx5_core_health *health = &dev->priv.health;
298
299 destroy_workqueue(health->wq);
300 }
301
mlx5_health_init(struct mlx5_core_dev * dev)302 int mlx5_health_init(struct mlx5_core_dev *dev)
303 {
304 struct mlx5_core_health *health;
305 char *name;
306
307 health = &dev->priv.health;
308 name = kmalloc(64, GFP_KERNEL);
309 if (!name)
310 return -ENOMEM;
311
312 strcpy(name, "mlx5_health");
313 strcat(name, dev_name(&dev->pdev->dev));
314 health->wq = create_singlethread_workqueue(name);
315 kfree(name);
316 if (!health->wq)
317 return -ENOMEM;
318
319 INIT_WORK(&health->work, health_care);
320
321 return 0;
322 }
323