1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <asm/page.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
43 #include <linux/ip.h>
44 #include <linux/moduleparam.h>
45
46 #include "mlx4_en.h"
47
mlx4_en_create_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring ** pring,u32 size,u16 stride,int node,int queue_index)48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
49 struct mlx4_en_tx_ring **pring, u32 size,
50 u16 stride, int node, int queue_index)
51 {
52 struct mlx4_en_dev *mdev = priv->mdev;
53 struct mlx4_en_tx_ring *ring;
54 int tmp;
55 int err;
56
57 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
58 if (!ring) {
59 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
60 if (!ring) {
61 en_err(priv, "Failed allocating TX ring\n");
62 return -ENOMEM;
63 }
64 }
65
66 ring->size = size;
67 ring->size_mask = size - 1;
68 ring->stride = stride;
69 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
70
71 tmp = size * sizeof(struct mlx4_en_tx_info);
72 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
73 if (!ring->tx_info) {
74 ring->tx_info = vmalloc(tmp);
75 if (!ring->tx_info) {
76 err = -ENOMEM;
77 goto err_ring;
78 }
79 }
80
81 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
82 ring->tx_info, tmp);
83
84 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
85 if (!ring->bounce_buf) {
86 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
87 if (!ring->bounce_buf) {
88 err = -ENOMEM;
89 goto err_info;
90 }
91 }
92 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
93
94 /* Allocate HW buffers on provided NUMA node */
95 set_dev_node(&mdev->dev->persist->pdev->dev, node);
96 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
97 2 * PAGE_SIZE);
98 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
99 if (err) {
100 en_err(priv, "Failed allocating hwq resources\n");
101 goto err_bounce;
102 }
103
104 err = mlx4_en_map_buffer(&ring->wqres.buf);
105 if (err) {
106 en_err(priv, "Failed to map TX buffer\n");
107 goto err_hwq_res;
108 }
109
110 ring->buf = ring->wqres.buf.direct.buf;
111
112 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
113 ring, ring->buf, ring->size, ring->buf_size,
114 (unsigned long long) ring->wqres.buf.direct.map);
115
116 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
117 MLX4_RESERVE_ETH_BF_QP);
118 if (err) {
119 en_err(priv, "failed reserving qp for TX ring\n");
120 goto err_map;
121 }
122
123 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
124 if (err) {
125 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
126 goto err_reserve;
127 }
128 ring->qp.event = mlx4_en_sqp_event;
129
130 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
131 if (err) {
132 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
133 ring->bf.uar = &mdev->priv_uar;
134 ring->bf.uar->map = mdev->uar_map;
135 ring->bf_enabled = false;
136 ring->bf_alloced = false;
137 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
138 } else {
139 ring->bf_alloced = true;
140 ring->bf_enabled = !!(priv->pflags &
141 MLX4_EN_PRIV_FLAGS_BLUEFLAME);
142 }
143
144 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
145 ring->queue_index = queue_index;
146
147 if (queue_index < priv->num_tx_rings_p_up)
148 cpumask_set_cpu(cpumask_local_spread(queue_index,
149 priv->mdev->dev->numa_node),
150 &ring->affinity_mask);
151
152 *pring = ring;
153 return 0;
154
155 err_reserve:
156 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
157 err_map:
158 mlx4_en_unmap_buffer(&ring->wqres.buf);
159 err_hwq_res:
160 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
161 err_bounce:
162 kfree(ring->bounce_buf);
163 ring->bounce_buf = NULL;
164 err_info:
165 kvfree(ring->tx_info);
166 ring->tx_info = NULL;
167 err_ring:
168 kfree(ring);
169 *pring = NULL;
170 return err;
171 }
172
mlx4_en_destroy_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring ** pring)173 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
174 struct mlx4_en_tx_ring **pring)
175 {
176 struct mlx4_en_dev *mdev = priv->mdev;
177 struct mlx4_en_tx_ring *ring = *pring;
178 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
179
180 if (ring->bf_alloced)
181 mlx4_bf_free(mdev->dev, &ring->bf);
182 mlx4_qp_remove(mdev->dev, &ring->qp);
183 mlx4_qp_free(mdev->dev, &ring->qp);
184 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
185 mlx4_en_unmap_buffer(&ring->wqres.buf);
186 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
187 kfree(ring->bounce_buf);
188 ring->bounce_buf = NULL;
189 kvfree(ring->tx_info);
190 ring->tx_info = NULL;
191 kfree(ring);
192 *pring = NULL;
193 }
194
mlx4_en_activate_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int cq,int user_prio)195 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
196 struct mlx4_en_tx_ring *ring,
197 int cq, int user_prio)
198 {
199 struct mlx4_en_dev *mdev = priv->mdev;
200 int err;
201
202 ring->cqn = cq;
203 ring->prod = 0;
204 ring->cons = 0xffffffff;
205 ring->last_nr_txbb = 1;
206 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
207 memset(ring->buf, 0, ring->buf_size);
208
209 ring->qp_state = MLX4_QP_STATE_RST;
210 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
211 ring->mr_key = cpu_to_be32(mdev->mr.key);
212
213 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
214 ring->cqn, user_prio, &ring->context);
215 if (ring->bf_alloced)
216 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
217
218 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
219 &ring->qp, &ring->qp_state);
220 if (!cpumask_empty(&ring->affinity_mask))
221 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
222 ring->queue_index);
223
224 return err;
225 }
226
mlx4_en_deactivate_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring)227 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
228 struct mlx4_en_tx_ring *ring)
229 {
230 struct mlx4_en_dev *mdev = priv->mdev;
231
232 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
233 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
234 }
235
mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring * ring)236 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
237 {
238 return ring->prod - ring->cons > ring->full_size;
239 }
240
mlx4_en_stamp_wqe(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int index,u8 owner)241 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
242 struct mlx4_en_tx_ring *ring, int index,
243 u8 owner)
244 {
245 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
246 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
247 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
248 void *end = ring->buf + ring->buf_size;
249 __be32 *ptr = (__be32 *)tx_desc;
250 int i;
251
252 /* Optimize the common case when there are no wraparounds */
253 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
254 /* Stamp the freed descriptor */
255 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
256 i += STAMP_STRIDE) {
257 *ptr = stamp;
258 ptr += STAMP_DWORDS;
259 }
260 } else {
261 /* Stamp the freed descriptor */
262 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
263 i += STAMP_STRIDE) {
264 *ptr = stamp;
265 ptr += STAMP_DWORDS;
266 if ((void *)ptr >= end) {
267 ptr = ring->buf;
268 stamp ^= cpu_to_be32(0x80000000);
269 }
270 }
271 }
272 }
273
274
mlx4_en_free_tx_desc(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int index,u8 owner,u64 timestamp)275 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
276 struct mlx4_en_tx_ring *ring,
277 int index, u8 owner, u64 timestamp)
278 {
279 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
280 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
281 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
282 void *end = ring->buf + ring->buf_size;
283 struct sk_buff *skb = tx_info->skb;
284 int nr_maps = tx_info->nr_maps;
285 int i;
286
287 /* We do not touch skb here, so prefetch skb->users location
288 * to speedup consume_skb()
289 */
290 prefetchw(&skb->users);
291
292 if (unlikely(timestamp)) {
293 struct skb_shared_hwtstamps hwts;
294
295 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
296 skb_tstamp_tx(skb, &hwts);
297 }
298
299 /* Optimize the common case when there are no wraparounds */
300 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
301 if (!tx_info->inl) {
302 if (tx_info->linear)
303 dma_unmap_single(priv->ddev,
304 tx_info->map0_dma,
305 tx_info->map0_byte_count,
306 PCI_DMA_TODEVICE);
307 else
308 dma_unmap_page(priv->ddev,
309 tx_info->map0_dma,
310 tx_info->map0_byte_count,
311 PCI_DMA_TODEVICE);
312 for (i = 1; i < nr_maps; i++) {
313 data++;
314 dma_unmap_page(priv->ddev,
315 (dma_addr_t)be64_to_cpu(data->addr),
316 be32_to_cpu(data->byte_count),
317 PCI_DMA_TODEVICE);
318 }
319 }
320 } else {
321 if (!tx_info->inl) {
322 if ((void *) data >= end) {
323 data = ring->buf + ((void *)data - end);
324 }
325
326 if (tx_info->linear)
327 dma_unmap_single(priv->ddev,
328 tx_info->map0_dma,
329 tx_info->map0_byte_count,
330 PCI_DMA_TODEVICE);
331 else
332 dma_unmap_page(priv->ddev,
333 tx_info->map0_dma,
334 tx_info->map0_byte_count,
335 PCI_DMA_TODEVICE);
336 for (i = 1; i < nr_maps; i++) {
337 data++;
338 /* Check for wraparound before unmapping */
339 if ((void *) data >= end)
340 data = ring->buf;
341 dma_unmap_page(priv->ddev,
342 (dma_addr_t)be64_to_cpu(data->addr),
343 be32_to_cpu(data->byte_count),
344 PCI_DMA_TODEVICE);
345 }
346 }
347 }
348 dev_consume_skb_any(skb);
349 return tx_info->nr_txbb;
350 }
351
352
mlx4_en_free_tx_buf(struct net_device * dev,struct mlx4_en_tx_ring * ring)353 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
354 {
355 struct mlx4_en_priv *priv = netdev_priv(dev);
356 int cnt = 0;
357
358 /* Skip last polled descriptor */
359 ring->cons += ring->last_nr_txbb;
360 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
361 ring->cons, ring->prod);
362
363 if ((u32) (ring->prod - ring->cons) > ring->size) {
364 if (netif_msg_tx_err(priv))
365 en_warn(priv, "Tx consumer passed producer!\n");
366 return 0;
367 }
368
369 while (ring->cons != ring->prod) {
370 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
371 ring->cons & ring->size_mask,
372 !!(ring->cons & ring->size), 0);
373 ring->cons += ring->last_nr_txbb;
374 cnt++;
375 }
376
377 netdev_tx_reset_queue(ring->tx_queue);
378
379 if (cnt)
380 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
381
382 return cnt;
383 }
384
mlx4_en_process_tx_cq(struct net_device * dev,struct mlx4_en_cq * cq)385 static bool mlx4_en_process_tx_cq(struct net_device *dev,
386 struct mlx4_en_cq *cq)
387 {
388 struct mlx4_en_priv *priv = netdev_priv(dev);
389 struct mlx4_cq *mcq = &cq->mcq;
390 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
391 struct mlx4_cqe *cqe;
392 u16 index;
393 u16 new_index, ring_index, stamp_index;
394 u32 txbbs_skipped = 0;
395 u32 txbbs_stamp = 0;
396 u32 cons_index = mcq->cons_index;
397 int size = cq->size;
398 u32 size_mask = ring->size_mask;
399 struct mlx4_cqe *buf = cq->buf;
400 u32 packets = 0;
401 u32 bytes = 0;
402 int factor = priv->cqe_factor;
403 int done = 0;
404 int budget = priv->tx_work_limit;
405 u32 last_nr_txbb;
406 u32 ring_cons;
407
408 if (!priv->port_up)
409 return true;
410
411 netdev_txq_bql_complete_prefetchw(ring->tx_queue);
412
413 index = cons_index & size_mask;
414 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
415 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
416 ring_cons = ACCESS_ONCE(ring->cons);
417 ring_index = ring_cons & size_mask;
418 stamp_index = ring_index;
419
420 /* Process all completed CQEs */
421 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
422 cons_index & size) && (done < budget)) {
423 /*
424 * make sure we read the CQE after we read the
425 * ownership bit
426 */
427 dma_rmb();
428
429 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
430 MLX4_CQE_OPCODE_ERROR)) {
431 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
432
433 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
434 cqe_err->vendor_err_syndrome,
435 cqe_err->syndrome);
436 }
437
438 /* Skip over last polled CQE */
439 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
440
441 do {
442 u64 timestamp = 0;
443
444 txbbs_skipped += last_nr_txbb;
445 ring_index = (ring_index + last_nr_txbb) & size_mask;
446
447 if (unlikely(ring->tx_info[ring_index].ts_requested))
448 timestamp = mlx4_en_get_cqe_ts(cqe);
449
450 /* free next descriptor */
451 last_nr_txbb = mlx4_en_free_tx_desc(
452 priv, ring, ring_index,
453 !!((ring_cons + txbbs_skipped) &
454 ring->size), timestamp);
455
456 mlx4_en_stamp_wqe(priv, ring, stamp_index,
457 !!((ring_cons + txbbs_stamp) &
458 ring->size));
459 stamp_index = ring_index;
460 txbbs_stamp = txbbs_skipped;
461 packets++;
462 bytes += ring->tx_info[ring_index].nr_bytes;
463 } while ((++done < budget) && (ring_index != new_index));
464
465 ++cons_index;
466 index = cons_index & size_mask;
467 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
468 }
469
470
471 /*
472 * To prevent CQ overflow we first update CQ consumer and only then
473 * the ring consumer.
474 */
475 mcq->cons_index = cons_index;
476 mlx4_cq_set_ci(mcq);
477 wmb();
478
479 /* we want to dirty this cache line once */
480 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
481 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
482
483 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
484
485 /* Wakeup Tx queue if this stopped, and ring is not full.
486 */
487 if (netif_tx_queue_stopped(ring->tx_queue) &&
488 !mlx4_en_is_tx_ring_full(ring)) {
489 netif_tx_wake_queue(ring->tx_queue);
490 ring->wake_queue++;
491 }
492 return done < budget;
493 }
494
mlx4_en_tx_irq(struct mlx4_cq * mcq)495 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
496 {
497 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
498 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
499
500 if (likely(priv->port_up))
501 napi_schedule_irqoff(&cq->napi);
502 else
503 mlx4_en_arm_cq(priv, cq);
504 }
505
506 /* TX CQ polling - called by NAPI */
mlx4_en_poll_tx_cq(struct napi_struct * napi,int budget)507 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
508 {
509 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
510 struct net_device *dev = cq->dev;
511 struct mlx4_en_priv *priv = netdev_priv(dev);
512 int clean_complete;
513
514 clean_complete = mlx4_en_process_tx_cq(dev, cq);
515 if (!clean_complete)
516 return budget;
517
518 napi_complete(napi);
519 mlx4_en_arm_cq(priv, cq);
520
521 return 0;
522 }
523
mlx4_en_bounce_to_desc(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,u32 index,unsigned int desc_size)524 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
525 struct mlx4_en_tx_ring *ring,
526 u32 index,
527 unsigned int desc_size)
528 {
529 u32 copy = (ring->size - index) * TXBB_SIZE;
530 int i;
531
532 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
533 if ((i & (TXBB_SIZE - 1)) == 0)
534 wmb();
535
536 *((u32 *) (ring->buf + i)) =
537 *((u32 *) (ring->bounce_buf + copy + i));
538 }
539
540 for (i = copy - 4; i >= 4 ; i -= 4) {
541 if ((i & (TXBB_SIZE - 1)) == 0)
542 wmb();
543
544 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
545 *((u32 *) (ring->bounce_buf + i));
546 }
547
548 /* Return real descriptor location */
549 return ring->buf + index * TXBB_SIZE;
550 }
551
552 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
553 *
554 * It seems strange we do not simply use skb_copy_bits().
555 * This would allow to inline all skbs iff skb->len <= inline_thold
556 *
557 * Note that caller already checked skb was not a gso packet
558 */
is_inline(int inline_thold,const struct sk_buff * skb,const struct skb_shared_info * shinfo,void ** pfrag)559 static bool is_inline(int inline_thold, const struct sk_buff *skb,
560 const struct skb_shared_info *shinfo,
561 void **pfrag)
562 {
563 void *ptr;
564
565 if (skb->len > inline_thold || !inline_thold)
566 return false;
567
568 if (shinfo->nr_frags == 1) {
569 ptr = skb_frag_address_safe(&shinfo->frags[0]);
570 if (unlikely(!ptr))
571 return false;
572 *pfrag = ptr;
573 return true;
574 }
575 if (shinfo->nr_frags)
576 return false;
577 return true;
578 }
579
inline_size(const struct sk_buff * skb)580 static int inline_size(const struct sk_buff *skb)
581 {
582 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
583 <= MLX4_INLINE_ALIGN)
584 return ALIGN(skb->len + CTRL_SIZE +
585 sizeof(struct mlx4_wqe_inline_seg), 16);
586 else
587 return ALIGN(skb->len + CTRL_SIZE + 2 *
588 sizeof(struct mlx4_wqe_inline_seg), 16);
589 }
590
get_real_size(const struct sk_buff * skb,const struct skb_shared_info * shinfo,struct net_device * dev,int * lso_header_size,bool * inline_ok,void ** pfrag)591 static int get_real_size(const struct sk_buff *skb,
592 const struct skb_shared_info *shinfo,
593 struct net_device *dev,
594 int *lso_header_size,
595 bool *inline_ok,
596 void **pfrag)
597 {
598 struct mlx4_en_priv *priv = netdev_priv(dev);
599 int real_size;
600
601 if (shinfo->gso_size) {
602 *inline_ok = false;
603 if (skb->encapsulation)
604 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
605 else
606 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
607 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
608 ALIGN(*lso_header_size + 4, DS_SIZE);
609 if (unlikely(*lso_header_size != skb_headlen(skb))) {
610 /* We add a segment for the skb linear buffer only if
611 * it contains data */
612 if (*lso_header_size < skb_headlen(skb))
613 real_size += DS_SIZE;
614 else {
615 if (netif_msg_tx_err(priv))
616 en_warn(priv, "Non-linear headers\n");
617 return 0;
618 }
619 }
620 } else {
621 *lso_header_size = 0;
622 *inline_ok = is_inline(priv->prof->inline_thold, skb,
623 shinfo, pfrag);
624
625 if (*inline_ok)
626 real_size = inline_size(skb);
627 else
628 real_size = CTRL_SIZE +
629 (shinfo->nr_frags + 1) * DS_SIZE;
630 }
631
632 return real_size;
633 }
634
build_inline_wqe(struct mlx4_en_tx_desc * tx_desc,const struct sk_buff * skb,const struct skb_shared_info * shinfo,int real_size,u16 * vlan_tag,int tx_ind,void * fragptr)635 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
636 const struct sk_buff *skb,
637 const struct skb_shared_info *shinfo,
638 int real_size, u16 *vlan_tag,
639 int tx_ind, void *fragptr)
640 {
641 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
642 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
643 unsigned int hlen = skb_headlen(skb);
644
645 if (skb->len <= spc) {
646 if (likely(skb->len >= MIN_PKT_LEN)) {
647 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
648 } else {
649 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
650 memset(((void *)(inl + 1)) + skb->len, 0,
651 MIN_PKT_LEN - skb->len);
652 }
653 skb_copy_from_linear_data(skb, inl + 1, hlen);
654 if (shinfo->nr_frags)
655 memcpy(((void *)(inl + 1)) + hlen, fragptr,
656 skb_frag_size(&shinfo->frags[0]));
657
658 } else {
659 inl->byte_count = cpu_to_be32(1 << 31 | spc);
660 if (hlen <= spc) {
661 skb_copy_from_linear_data(skb, inl + 1, hlen);
662 if (hlen < spc) {
663 memcpy(((void *)(inl + 1)) + hlen,
664 fragptr, spc - hlen);
665 fragptr += spc - hlen;
666 }
667 inl = (void *) (inl + 1) + spc;
668 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
669 } else {
670 skb_copy_from_linear_data(skb, inl + 1, spc);
671 inl = (void *) (inl + 1) + spc;
672 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
673 hlen - spc);
674 if (shinfo->nr_frags)
675 memcpy(((void *)(inl + 1)) + hlen - spc,
676 fragptr,
677 skb_frag_size(&shinfo->frags[0]));
678 }
679
680 dma_wmb();
681 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
682 }
683 }
684
mlx4_en_select_queue(struct net_device * dev,struct sk_buff * skb,void * accel_priv,select_queue_fallback_t fallback)685 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
686 void *accel_priv, select_queue_fallback_t fallback)
687 {
688 struct mlx4_en_priv *priv = netdev_priv(dev);
689 u16 rings_p_up = priv->num_tx_rings_p_up;
690 u8 up = 0;
691
692 if (dev->num_tc)
693 return skb_tx_hash(dev, skb);
694
695 if (skb_vlan_tag_present(skb))
696 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT;
697
698 return fallback(dev, skb) % rings_p_up + up * rings_p_up;
699 }
700
mlx4_bf_copy(void __iomem * dst,const void * src,unsigned int bytecnt)701 static void mlx4_bf_copy(void __iomem *dst, const void *src,
702 unsigned int bytecnt)
703 {
704 __iowrite64_copy(dst, src, bytecnt / 8);
705 }
706
mlx4_en_xmit(struct sk_buff * skb,struct net_device * dev)707 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
708 {
709 struct skb_shared_info *shinfo = skb_shinfo(skb);
710 struct mlx4_en_priv *priv = netdev_priv(dev);
711 struct device *ddev = priv->ddev;
712 struct mlx4_en_tx_ring *ring;
713 struct mlx4_en_tx_desc *tx_desc;
714 struct mlx4_wqe_data_seg *data;
715 struct mlx4_en_tx_info *tx_info;
716 int tx_ind = 0;
717 int nr_txbb;
718 int desc_size;
719 int real_size;
720 u32 index, bf_index;
721 __be32 op_own;
722 u16 vlan_tag = 0;
723 u16 vlan_proto = 0;
724 int i_frag;
725 int lso_header_size;
726 void *fragptr = NULL;
727 bool bounce = false;
728 bool send_doorbell;
729 bool stop_queue;
730 bool inline_ok;
731 u32 ring_cons;
732
733 if (!priv->port_up)
734 goto tx_drop;
735
736 tx_ind = skb_get_queue_mapping(skb);
737 ring = priv->tx_ring[tx_ind];
738
739 /* fetch ring->cons far ahead before needing it to avoid stall */
740 ring_cons = ACCESS_ONCE(ring->cons);
741
742 real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
743 &inline_ok, &fragptr);
744 if (unlikely(!real_size))
745 goto tx_drop;
746
747 /* Align descriptor to TXBB size */
748 desc_size = ALIGN(real_size, TXBB_SIZE);
749 nr_txbb = desc_size / TXBB_SIZE;
750 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
751 if (netif_msg_tx_err(priv))
752 en_warn(priv, "Oversized header or SG list\n");
753 goto tx_drop;
754 }
755
756 if (skb_vlan_tag_present(skb)) {
757 vlan_tag = skb_vlan_tag_get(skb);
758 vlan_proto = be16_to_cpu(skb->vlan_proto);
759 }
760
761 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
762
763 /* Track current inflight packets for performance analysis */
764 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
765 (u32)(ring->prod - ring_cons - 1));
766
767 /* Packet is good - grab an index and transmit it */
768 index = ring->prod & ring->size_mask;
769 bf_index = ring->prod;
770
771 /* See if we have enough space for whole descriptor TXBB for setting
772 * SW ownership on next descriptor; if not, use a bounce buffer. */
773 if (likely(index + nr_txbb <= ring->size))
774 tx_desc = ring->buf + index * TXBB_SIZE;
775 else {
776 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
777 bounce = true;
778 }
779
780 /* Save skb in tx_info ring */
781 tx_info = &ring->tx_info[index];
782 tx_info->skb = skb;
783 tx_info->nr_txbb = nr_txbb;
784
785 data = &tx_desc->data;
786 if (lso_header_size)
787 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
788 DS_SIZE));
789
790 /* valid only for none inline segments */
791 tx_info->data_offset = (void *)data - (void *)tx_desc;
792
793 tx_info->inl = inline_ok;
794
795 tx_info->linear = (lso_header_size < skb_headlen(skb) &&
796 !inline_ok) ? 1 : 0;
797
798 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
799 data += tx_info->nr_maps - 1;
800
801 if (!tx_info->inl) {
802 dma_addr_t dma = 0;
803 u32 byte_count = 0;
804
805 /* Map fragments if any */
806 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
807 const struct skb_frag_struct *frag;
808
809 frag = &shinfo->frags[i_frag];
810 byte_count = skb_frag_size(frag);
811 dma = skb_frag_dma_map(ddev, frag,
812 0, byte_count,
813 DMA_TO_DEVICE);
814 if (dma_mapping_error(ddev, dma))
815 goto tx_drop_unmap;
816
817 data->addr = cpu_to_be64(dma);
818 data->lkey = ring->mr_key;
819 dma_wmb();
820 data->byte_count = cpu_to_be32(byte_count);
821 --data;
822 }
823
824 /* Map linear part if needed */
825 if (tx_info->linear) {
826 byte_count = skb_headlen(skb) - lso_header_size;
827
828 dma = dma_map_single(ddev, skb->data +
829 lso_header_size, byte_count,
830 PCI_DMA_TODEVICE);
831 if (dma_mapping_error(ddev, dma))
832 goto tx_drop_unmap;
833
834 data->addr = cpu_to_be64(dma);
835 data->lkey = ring->mr_key;
836 dma_wmb();
837 data->byte_count = cpu_to_be32(byte_count);
838 }
839 /* tx completion can avoid cache line miss for common cases */
840 tx_info->map0_dma = dma;
841 tx_info->map0_byte_count = byte_count;
842 }
843
844 /*
845 * For timestamping add flag to skb_shinfo and
846 * set flag for further reference
847 */
848 tx_info->ts_requested = 0;
849 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
850 shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
851 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
852 tx_info->ts_requested = 1;
853 }
854
855 /* Prepare ctrl segement apart opcode+ownership, which depends on
856 * whether LSO is used */
857 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
858 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
859 if (!skb->encapsulation)
860 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
861 MLX4_WQE_CTRL_TCP_UDP_CSUM);
862 else
863 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
864 ring->tx_csum++;
865 }
866
867 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
868 struct ethhdr *ethh;
869
870 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
871 * so that VFs and PF can communicate with each other
872 */
873 ethh = (struct ethhdr *)skb->data;
874 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
875 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
876 }
877
878 /* Handle LSO (TSO) packets */
879 if (lso_header_size) {
880 int i;
881
882 /* Mark opcode as LSO */
883 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
884 ((ring->prod & ring->size) ?
885 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
886
887 /* Fill in the LSO prefix */
888 tx_desc->lso.mss_hdr_size = cpu_to_be32(
889 shinfo->gso_size << 16 | lso_header_size);
890
891 /* Copy headers;
892 * note that we already verified that it is linear */
893 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
894
895 ring->tso_packets++;
896
897 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
898 !!((skb->len - lso_header_size) % shinfo->gso_size);
899 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
900 ring->packets += i;
901 } else {
902 /* Normal (Non LSO) packet */
903 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
904 ((ring->prod & ring->size) ?
905 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
906 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
907 ring->packets++;
908 }
909 ring->bytes += tx_info->nr_bytes;
910 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
911 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
912
913 if (tx_info->inl)
914 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
915 tx_ind, fragptr);
916
917 if (skb->encapsulation) {
918 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
919 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
920 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
921 else
922 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
923 }
924
925 ring->prod += nr_txbb;
926
927 /* If we used a bounce buffer then copy descriptor back into place */
928 if (unlikely(bounce))
929 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
930
931 skb_tx_timestamp(skb);
932
933 /* Check available TXBBs And 2K spare for prefetch */
934 stop_queue = mlx4_en_is_tx_ring_full(ring);
935 if (unlikely(stop_queue)) {
936 netif_tx_stop_queue(ring->tx_queue);
937 ring->queue_stopped++;
938 }
939 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
940
941 real_size = (real_size / 16) & 0x3f;
942
943 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
944 !skb_vlan_tag_present(skb) && send_doorbell) {
945 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
946 cpu_to_be32(real_size);
947
948 op_own |= htonl((bf_index & 0xffff) << 8);
949 /* Ensure new descriptor hits memory
950 * before setting ownership of this descriptor to HW
951 */
952 dma_wmb();
953 tx_desc->ctrl.owner_opcode = op_own;
954
955 wmb();
956
957 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
958 desc_size);
959
960 wmb();
961
962 ring->bf.offset ^= ring->bf.buf_size;
963 } else {
964 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
965 if (vlan_proto == ETH_P_8021AD)
966 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
967 else if (vlan_proto == ETH_P_8021Q)
968 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
969 else
970 tx_desc->ctrl.ins_vlan = 0;
971
972 tx_desc->ctrl.fence_size = real_size;
973
974 /* Ensure new descriptor hits memory
975 * before setting ownership of this descriptor to HW
976 */
977 dma_wmb();
978 tx_desc->ctrl.owner_opcode = op_own;
979 if (send_doorbell) {
980 wmb();
981 /* Since there is no iowrite*_native() that writes the
982 * value as is, without byteswapping - using the one
983 * the doesn't do byteswapping in the relevant arch
984 * endianness.
985 */
986 #if defined(__LITTLE_ENDIAN)
987 iowrite32(
988 #else
989 iowrite32be(
990 #endif
991 ring->doorbell_qpn,
992 ring->bf.uar->map + MLX4_SEND_DOORBELL);
993 } else {
994 ring->xmit_more++;
995 }
996 }
997
998 if (unlikely(stop_queue)) {
999 /* If queue was emptied after the if (stop_queue) , and before
1000 * the netif_tx_stop_queue() - need to wake the queue,
1001 * or else it will remain stopped forever.
1002 * Need a memory barrier to make sure ring->cons was not
1003 * updated before queue was stopped.
1004 */
1005 smp_rmb();
1006
1007 ring_cons = ACCESS_ONCE(ring->cons);
1008 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1009 netif_tx_wake_queue(ring->tx_queue);
1010 ring->wake_queue++;
1011 }
1012 }
1013 return NETDEV_TX_OK;
1014
1015 tx_drop_unmap:
1016 en_err(priv, "DMA mapping error\n");
1017
1018 while (++i_frag < shinfo->nr_frags) {
1019 ++data;
1020 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1021 be32_to_cpu(data->byte_count),
1022 PCI_DMA_TODEVICE);
1023 }
1024
1025 tx_drop:
1026 dev_kfree_skb_any(skb);
1027 priv->stats.tx_dropped++;
1028 return NETDEV_TX_OK;
1029 }
1030
1031