1 /*
2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published by
8  * the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "mdp5_kms.h"
20 
21 #include "drm_crtc.h"
22 #include "drm_crtc_helper.h"
23 
24 struct mdp5_encoder {
25 	struct drm_encoder base;
26 	struct mdp5_interface intf;
27 	spinlock_t intf_lock;	/* protect REG_MDP5_INTF_* registers */
28 	bool enabled;
29 	uint32_t bsc;
30 
31 	struct mdp5_ctl *ctl;
32 };
33 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
34 
get_kms(struct drm_encoder * encoder)35 static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
36 {
37 	struct msm_drm_private *priv = encoder->dev->dev_private;
38 	return to_mdp5_kms(to_mdp_kms(priv->kms));
39 }
40 
41 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
42 #include <mach/board.h>
43 #include <mach/msm_bus.h>
44 #include <mach/msm_bus_board.h>
45 #define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val)		\
46 	{						\
47 		.src = MSM_BUS_MASTER_MDP_PORT0,	\
48 		.dst = MSM_BUS_SLAVE_EBI_CH0,		\
49 		.ab = (ab_val),				\
50 		.ib = (ib_val),				\
51 	}
52 
53 static struct msm_bus_vectors mdp_bus_vectors[] = {
54 	MDP_BUS_VECTOR_ENTRY(0, 0),
55 	MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
56 };
57 static struct msm_bus_paths mdp_bus_usecases[] = { {
58 		.num_paths = 1,
59 		.vectors = &mdp_bus_vectors[0],
60 }, {
61 		.num_paths = 1,
62 		.vectors = &mdp_bus_vectors[1],
63 } };
64 static struct msm_bus_scale_pdata mdp_bus_scale_table = {
65 	.usecase = mdp_bus_usecases,
66 	.num_usecases = ARRAY_SIZE(mdp_bus_usecases),
67 	.name = "mdss_mdp",
68 };
69 
bs_init(struct mdp5_encoder * mdp5_encoder)70 static void bs_init(struct mdp5_encoder *mdp5_encoder)
71 {
72 	mdp5_encoder->bsc = msm_bus_scale_register_client(
73 			&mdp_bus_scale_table);
74 	DBG("bus scale client: %08x", mdp5_encoder->bsc);
75 }
76 
bs_fini(struct mdp5_encoder * mdp5_encoder)77 static void bs_fini(struct mdp5_encoder *mdp5_encoder)
78 {
79 	if (mdp5_encoder->bsc) {
80 		msm_bus_scale_unregister_client(mdp5_encoder->bsc);
81 		mdp5_encoder->bsc = 0;
82 	}
83 }
84 
bs_set(struct mdp5_encoder * mdp5_encoder,int idx)85 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
86 {
87 	if (mdp5_encoder->bsc) {
88 		DBG("set bus scaling: %d", idx);
89 		/* HACK: scaling down, and then immediately back up
90 		 * seems to leave things broken (underflow).. so
91 		 * never disable:
92 		 */
93 		idx = 1;
94 		msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
95 	}
96 }
97 #else
bs_init(struct mdp5_encoder * mdp5_encoder)98 static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
bs_fini(struct mdp5_encoder * mdp5_encoder)99 static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
bs_set(struct mdp5_encoder * mdp5_encoder,int idx)100 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
101 #endif
102 
mdp5_encoder_destroy(struct drm_encoder * encoder)103 static void mdp5_encoder_destroy(struct drm_encoder *encoder)
104 {
105 	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
106 	bs_fini(mdp5_encoder);
107 	drm_encoder_cleanup(encoder);
108 	kfree(mdp5_encoder);
109 }
110 
111 static const struct drm_encoder_funcs mdp5_encoder_funcs = {
112 	.destroy = mdp5_encoder_destroy,
113 };
114 
mdp5_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)115 static bool mdp5_encoder_mode_fixup(struct drm_encoder *encoder,
116 		const struct drm_display_mode *mode,
117 		struct drm_display_mode *adjusted_mode)
118 {
119 	return true;
120 }
121 
mdp5_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)122 static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
123 		struct drm_display_mode *mode,
124 		struct drm_display_mode *adjusted_mode)
125 {
126 	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
127 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
128 	struct drm_device *dev = encoder->dev;
129 	struct drm_connector *connector;
130 	int intf = mdp5_encoder->intf.num;
131 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
132 	uint32_t display_v_start, display_v_end;
133 	uint32_t hsync_start_x, hsync_end_x;
134 	uint32_t format = 0x2100;
135 	unsigned long flags;
136 
137 	mode = adjusted_mode;
138 
139 	DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
140 			mode->base.id, mode->name,
141 			mode->vrefresh, mode->clock,
142 			mode->hdisplay, mode->hsync_start,
143 			mode->hsync_end, mode->htotal,
144 			mode->vdisplay, mode->vsync_start,
145 			mode->vsync_end, mode->vtotal,
146 			mode->type, mode->flags);
147 
148 	ctrl_pol = 0;
149 
150 	/* DSI controller cannot handle active-low sync signals. */
151 	if (mdp5_encoder->intf.type != INTF_DSI) {
152 		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
153 			ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
154 		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
155 			ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
156 	}
157 	/* probably need to get DATA_EN polarity from panel.. */
158 
159 	dtv_hsync_skew = 0;  /* get this from panel? */
160 
161 	/* Get color format from panel, default is 8bpc */
162 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
163 		if (connector->encoder == encoder) {
164 			switch (connector->display_info.bpc) {
165 			case 4:
166 				format |= 0;
167 				break;
168 			case 5:
169 				format |= 0x15;
170 				break;
171 			case 6:
172 				format |= 0x2A;
173 				break;
174 			case 8:
175 			default:
176 				format |= 0x3F;
177 				break;
178 			}
179 			break;
180 		}
181 	}
182 
183 	hsync_start_x = (mode->htotal - mode->hsync_start);
184 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
185 
186 	vsync_period = mode->vtotal * mode->htotal;
187 	vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
188 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
189 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
190 
191 	/*
192 	 * For edp only:
193 	 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
194 	 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
195 	 */
196 	if (mdp5_encoder->intf.type == INTF_eDP) {
197 		display_v_start += mode->htotal - mode->hsync_start;
198 		display_v_end -= mode->hsync_start - mode->hdisplay;
199 	}
200 
201 	spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
202 
203 	mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
204 			MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
205 			MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
206 	mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
207 	mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
208 	mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
209 			MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
210 			MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
211 	mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
212 	mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
213 	mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
214 	mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
215 	mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
216 	mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
217 	mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
218 			MDP5_INTF_ACTIVE_HCTL_START(0) |
219 			MDP5_INTF_ACTIVE_HCTL_END(0));
220 	mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
221 	mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
222 	mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
223 	mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3);  /* frame+line? */
224 
225 	spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
226 
227 	mdp5_crtc_set_pipeline(encoder->crtc, &mdp5_encoder->intf,
228 				mdp5_encoder->ctl);
229 }
230 
mdp5_encoder_disable(struct drm_encoder * encoder)231 static void mdp5_encoder_disable(struct drm_encoder *encoder)
232 {
233 	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
234 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
235 	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
236 	int lm = mdp5_crtc_get_lm(encoder->crtc);
237 	struct mdp5_interface *intf = &mdp5_encoder->intf;
238 	int intfn = mdp5_encoder->intf.num;
239 	unsigned long flags;
240 
241 	if (WARN_ON(!mdp5_encoder->enabled))
242 		return;
243 
244 	mdp5_ctl_set_encoder_state(ctl, false);
245 
246 	spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
247 	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
248 	spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
249 	mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
250 
251 	/*
252 	 * Wait for a vsync so we know the ENABLE=0 latched before
253 	 * the (connector) source of the vsync's gets disabled,
254 	 * otherwise we end up in a funny state if we re-enable
255 	 * before the disable latches, which results that some of
256 	 * the settings changes for the new modeset (like new
257 	 * scanout buffer) don't latch properly..
258 	 */
259 	mdp_irq_wait(&mdp5_kms->base, intf2vblank(lm, intf));
260 
261 	bs_set(mdp5_encoder, 0);
262 
263 	mdp5_encoder->enabled = false;
264 }
265 
mdp5_encoder_enable(struct drm_encoder * encoder)266 static void mdp5_encoder_enable(struct drm_encoder *encoder)
267 {
268 	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
269 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
270 	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
271 	struct mdp5_interface *intf = &mdp5_encoder->intf;
272 	int intfn = mdp5_encoder->intf.num;
273 	unsigned long flags;
274 
275 	if (WARN_ON(mdp5_encoder->enabled))
276 		return;
277 
278 	bs_set(mdp5_encoder, 1);
279 	spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
280 	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
281 	spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
282 	mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
283 
284 	mdp5_ctl_set_encoder_state(ctl, true);
285 
286 	mdp5_encoder->enabled = true;
287 }
288 
289 static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
290 	.mode_fixup = mdp5_encoder_mode_fixup,
291 	.mode_set = mdp5_encoder_mode_set,
292 	.disable = mdp5_encoder_disable,
293 	.enable = mdp5_encoder_enable,
294 };
295 
mdp5_encoder_set_split_display(struct drm_encoder * encoder,struct drm_encoder * slave_encoder)296 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
297 					struct drm_encoder *slave_encoder)
298 {
299 	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
300 	struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
301 	struct mdp5_kms *mdp5_kms;
302 	int intf_num;
303 	u32 data = 0;
304 
305 	if (!encoder || !slave_encoder)
306 		return -EINVAL;
307 
308 	mdp5_kms = get_kms(encoder);
309 	intf_num = mdp5_encoder->intf.num;
310 
311 	/* Switch slave encoder's TimingGen Sync mode,
312 	 * to use the master's enable signal for the slave encoder.
313 	 */
314 	if (intf_num == 1)
315 		data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
316 	else if (intf_num == 2)
317 		data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
318 	else
319 		return -EINVAL;
320 
321 	/* Make sure clocks are on when connectors calling this function. */
322 	mdp5_enable(mdp5_kms);
323 	/* Dumb Panel, Sync mode */
324 	mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0);
325 	mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data);
326 	mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
327 
328 	mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
329 
330 	mdp5_disable(mdp5_kms);
331 
332 	return 0;
333 }
334 
335 /* initialize encoder */
mdp5_encoder_init(struct drm_device * dev,struct mdp5_interface * intf,struct mdp5_ctl * ctl)336 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
337 			struct mdp5_interface *intf, struct mdp5_ctl *ctl)
338 {
339 	struct drm_encoder *encoder = NULL;
340 	struct mdp5_encoder *mdp5_encoder;
341 	int enc_type = (intf->type == INTF_DSI) ?
342 		DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;
343 	int ret;
344 
345 	mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
346 	if (!mdp5_encoder) {
347 		ret = -ENOMEM;
348 		goto fail;
349 	}
350 
351 	memcpy(&mdp5_encoder->intf, intf, sizeof(mdp5_encoder->intf));
352 	encoder = &mdp5_encoder->base;
353 	mdp5_encoder->ctl = ctl;
354 
355 	spin_lock_init(&mdp5_encoder->intf_lock);
356 
357 	drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type);
358 
359 	drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
360 
361 	bs_init(mdp5_encoder);
362 
363 	return encoder;
364 
365 fail:
366 	if (encoder)
367 		mdp5_encoder_destroy(encoder);
368 
369 	return ERR_PTR(ret);
370 }
371