1 /*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "mdp5_kms.h"
20
21 #include "drm_crtc.h"
22 #include "drm_crtc_helper.h"
23
24 struct mdp5_encoder {
25 struct drm_encoder base;
26 struct mdp5_interface intf;
27 spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */
28 bool enabled;
29 uint32_t bsc;
30 };
31 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
32
get_kms(struct drm_encoder * encoder)33 static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
34 {
35 struct msm_drm_private *priv = encoder->dev->dev_private;
36 return to_mdp5_kms(to_mdp_kms(priv->kms));
37 }
38
39 #ifdef CONFIG_MSM_BUS_SCALING
40 #include <mach/board.h>
41 #include <mach/msm_bus.h>
42 #include <mach/msm_bus_board.h>
43 #define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \
44 { \
45 .src = MSM_BUS_MASTER_MDP_PORT0, \
46 .dst = MSM_BUS_SLAVE_EBI_CH0, \
47 .ab = (ab_val), \
48 .ib = (ib_val), \
49 }
50
51 static struct msm_bus_vectors mdp_bus_vectors[] = {
52 MDP_BUS_VECTOR_ENTRY(0, 0),
53 MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
54 };
55 static struct msm_bus_paths mdp_bus_usecases[] = { {
56 .num_paths = 1,
57 .vectors = &mdp_bus_vectors[0],
58 }, {
59 .num_paths = 1,
60 .vectors = &mdp_bus_vectors[1],
61 } };
62 static struct msm_bus_scale_pdata mdp_bus_scale_table = {
63 .usecase = mdp_bus_usecases,
64 .num_usecases = ARRAY_SIZE(mdp_bus_usecases),
65 .name = "mdss_mdp",
66 };
67
bs_init(struct mdp5_encoder * mdp5_encoder)68 static void bs_init(struct mdp5_encoder *mdp5_encoder)
69 {
70 mdp5_encoder->bsc = msm_bus_scale_register_client(
71 &mdp_bus_scale_table);
72 DBG("bus scale client: %08x", mdp5_encoder->bsc);
73 }
74
bs_fini(struct mdp5_encoder * mdp5_encoder)75 static void bs_fini(struct mdp5_encoder *mdp5_encoder)
76 {
77 if (mdp5_encoder->bsc) {
78 msm_bus_scale_unregister_client(mdp5_encoder->bsc);
79 mdp5_encoder->bsc = 0;
80 }
81 }
82
bs_set(struct mdp5_encoder * mdp5_encoder,int idx)83 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
84 {
85 if (mdp5_encoder->bsc) {
86 DBG("set bus scaling: %d", idx);
87 /* HACK: scaling down, and then immediately back up
88 * seems to leave things broken (underflow).. so
89 * never disable:
90 */
91 idx = 1;
92 msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
93 }
94 }
95 #else
bs_init(struct mdp5_encoder * mdp5_encoder)96 static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
bs_fini(struct mdp5_encoder * mdp5_encoder)97 static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
bs_set(struct mdp5_encoder * mdp5_encoder,int idx)98 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
99 #endif
100
mdp5_encoder_destroy(struct drm_encoder * encoder)101 static void mdp5_encoder_destroy(struct drm_encoder *encoder)
102 {
103 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
104 bs_fini(mdp5_encoder);
105 drm_encoder_cleanup(encoder);
106 kfree(mdp5_encoder);
107 }
108
109 static const struct drm_encoder_funcs mdp5_encoder_funcs = {
110 .destroy = mdp5_encoder_destroy,
111 };
112
mdp5_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)113 static bool mdp5_encoder_mode_fixup(struct drm_encoder *encoder,
114 const struct drm_display_mode *mode,
115 struct drm_display_mode *adjusted_mode)
116 {
117 return true;
118 }
119
mdp5_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)120 static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
121 struct drm_display_mode *mode,
122 struct drm_display_mode *adjusted_mode)
123 {
124 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
125 struct mdp5_kms *mdp5_kms = get_kms(encoder);
126 struct drm_device *dev = encoder->dev;
127 struct drm_connector *connector;
128 int intf = mdp5_encoder->intf.num;
129 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
130 uint32_t display_v_start, display_v_end;
131 uint32_t hsync_start_x, hsync_end_x;
132 uint32_t format = 0x2100;
133 unsigned long flags;
134
135 mode = adjusted_mode;
136
137 DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
138 mode->base.id, mode->name,
139 mode->vrefresh, mode->clock,
140 mode->hdisplay, mode->hsync_start,
141 mode->hsync_end, mode->htotal,
142 mode->vdisplay, mode->vsync_start,
143 mode->vsync_end, mode->vtotal,
144 mode->type, mode->flags);
145
146 ctrl_pol = 0;
147 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
148 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
149 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
150 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
151 /* probably need to get DATA_EN polarity from panel.. */
152
153 dtv_hsync_skew = 0; /* get this from panel? */
154
155 /* Get color format from panel, default is 8bpc */
156 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
157 if (connector->encoder == encoder) {
158 switch (connector->display_info.bpc) {
159 case 4:
160 format |= 0;
161 break;
162 case 5:
163 format |= 0x15;
164 break;
165 case 6:
166 format |= 0x2A;
167 break;
168 case 8:
169 default:
170 format |= 0x3F;
171 break;
172 }
173 break;
174 }
175 }
176
177 hsync_start_x = (mode->htotal - mode->hsync_start);
178 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
179
180 vsync_period = mode->vtotal * mode->htotal;
181 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
182 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
183 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
184
185 /*
186 * For edp only:
187 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
188 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
189 */
190 if (mdp5_encoder->intf.type == INTF_eDP) {
191 display_v_start += mode->htotal - mode->hsync_start;
192 display_v_end -= mode->hsync_start - mode->hdisplay;
193 }
194
195 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
196
197 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
198 MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
199 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
200 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
201 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
202 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
203 MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
204 MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
205 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
206 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
207 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
208 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
209 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
210 mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
211 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
212 MDP5_INTF_ACTIVE_HCTL_START(0) |
213 MDP5_INTF_ACTIVE_HCTL_END(0));
214 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
215 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
216 mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
217 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */
218
219 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
220
221 mdp5_crtc_set_intf(encoder->crtc, &mdp5_encoder->intf);
222 }
223
mdp5_encoder_disable(struct drm_encoder * encoder)224 static void mdp5_encoder_disable(struct drm_encoder *encoder)
225 {
226 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
227 struct mdp5_kms *mdp5_kms = get_kms(encoder);
228 struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
229 int lm = mdp5_crtc_get_lm(encoder->crtc);
230 struct mdp5_interface *intf = &mdp5_encoder->intf;
231 int intfn = mdp5_encoder->intf.num;
232 unsigned long flags;
233
234 if (WARN_ON(!mdp5_encoder->enabled))
235 return;
236
237 mdp5_ctl_set_encoder_state(ctl, false);
238
239 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
240 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
241 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
242 mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
243
244 /*
245 * Wait for a vsync so we know the ENABLE=0 latched before
246 * the (connector) source of the vsync's gets disabled,
247 * otherwise we end up in a funny state if we re-enable
248 * before the disable latches, which results that some of
249 * the settings changes for the new modeset (like new
250 * scanout buffer) don't latch properly..
251 */
252 mdp_irq_wait(&mdp5_kms->base, intf2vblank(lm, intf));
253
254 bs_set(mdp5_encoder, 0);
255
256 mdp5_encoder->enabled = false;
257 }
258
mdp5_encoder_enable(struct drm_encoder * encoder)259 static void mdp5_encoder_enable(struct drm_encoder *encoder)
260 {
261 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
262 struct mdp5_kms *mdp5_kms = get_kms(encoder);
263 struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
264 struct mdp5_interface *intf = &mdp5_encoder->intf;
265 int intfn = mdp5_encoder->intf.num;
266 unsigned long flags;
267
268 if (WARN_ON(mdp5_encoder->enabled))
269 return;
270
271 bs_set(mdp5_encoder, 1);
272 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
273 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
274 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
275 mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));
276
277 mdp5_ctl_set_encoder_state(ctl, true);
278
279 mdp5_encoder->enabled = true;
280 }
281
282 static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
283 .mode_fixup = mdp5_encoder_mode_fixup,
284 .mode_set = mdp5_encoder_mode_set,
285 .disable = mdp5_encoder_disable,
286 .enable = mdp5_encoder_enable,
287 };
288
mdp5_encoder_set_split_display(struct drm_encoder * encoder,struct drm_encoder * slave_encoder)289 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
290 struct drm_encoder *slave_encoder)
291 {
292 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
293 struct mdp5_kms *mdp5_kms;
294 int intf_num;
295 u32 data = 0;
296
297 if (!encoder || !slave_encoder)
298 return -EINVAL;
299
300 mdp5_kms = get_kms(encoder);
301 intf_num = mdp5_encoder->intf.num;
302
303 /* Switch slave encoder's TimingGen Sync mode,
304 * to use the master's enable signal for the slave encoder.
305 */
306 if (intf_num == 1)
307 data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
308 else if (intf_num == 2)
309 data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
310 else
311 return -EINVAL;
312
313 /* Make sure clocks are on when connectors calling this function. */
314 mdp5_enable(mdp5_kms);
315 mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
316 MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
317 /* Dumb Panel, Sync mode */
318 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
319 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
320 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
321 mdp5_disable(mdp5_kms);
322
323 return 0;
324 }
325
326 /* initialize encoder */
mdp5_encoder_init(struct drm_device * dev,struct mdp5_interface * intf)327 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
328 struct mdp5_interface *intf)
329 {
330 struct drm_encoder *encoder = NULL;
331 struct mdp5_encoder *mdp5_encoder;
332 int enc_type = (intf->type == INTF_DSI) ?
333 DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;
334 int ret;
335
336 mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
337 if (!mdp5_encoder) {
338 ret = -ENOMEM;
339 goto fail;
340 }
341
342 memcpy(&mdp5_encoder->intf, intf, sizeof(mdp5_encoder->intf));
343 encoder = &mdp5_encoder->base;
344
345 spin_lock_init(&mdp5_encoder->intf_lock);
346
347 drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type);
348
349 drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
350
351 bs_init(mdp5_encoder);
352
353 return encoder;
354
355 fail:
356 if (encoder)
357 mdp5_encoder_destroy(encoder);
358
359 return ERR_PTR(ret);
360 }
361