1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "mdp4_kms.h"
19
20 #include <drm/drm_mode.h>
21 #include "drm_crtc.h"
22 #include "drm_crtc_helper.h"
23 #include "drm_flip_work.h"
24
25 struct mdp4_crtc {
26 struct drm_crtc base;
27 char name[8];
28 int id;
29 int ovlp;
30 enum mdp4_dma dma;
31 bool enabled;
32
33 /* which mixer/encoder we route output to: */
34 int mixer;
35
36 struct {
37 spinlock_t lock;
38 bool stale;
39 uint32_t width, height;
40 uint32_t x, y;
41
42 /* next cursor to scan-out: */
43 uint32_t next_iova;
44 struct drm_gem_object *next_bo;
45
46 /* current cursor being scanned out: */
47 struct drm_gem_object *scanout_bo;
48 } cursor;
49
50
51 /* if there is a pending flip, these will be non-null: */
52 struct drm_pending_vblank_event *event;
53
54 #define PENDING_CURSOR 0x1
55 #define PENDING_FLIP 0x2
56 atomic_t pending;
57
58 /* for unref'ing cursor bo's after scanout completes: */
59 struct drm_flip_work unref_cursor_work;
60
61 struct mdp_irq vblank;
62 struct mdp_irq err;
63 };
64 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
65
get_kms(struct drm_crtc * crtc)66 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
67 {
68 struct msm_drm_private *priv = crtc->dev->dev_private;
69 return to_mdp4_kms(to_mdp_kms(priv->kms));
70 }
71
request_pending(struct drm_crtc * crtc,uint32_t pending)72 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
73 {
74 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
75
76 atomic_or(pending, &mdp4_crtc->pending);
77 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
78 }
79
crtc_flush(struct drm_crtc * crtc)80 static void crtc_flush(struct drm_crtc *crtc)
81 {
82 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
83 struct mdp4_kms *mdp4_kms = get_kms(crtc);
84 struct drm_plane *plane;
85 uint32_t flush = 0;
86
87 drm_atomic_crtc_for_each_plane(plane, crtc) {
88 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
89 flush |= pipe2flush(pipe_id);
90 }
91
92 flush |= ovlp2flush(mdp4_crtc->ovlp);
93
94 DBG("%s: flush=%08x", mdp4_crtc->name, flush);
95
96 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
97 }
98
99 /* if file!=NULL, this is preclose potential cancel-flip path */
complete_flip(struct drm_crtc * crtc,struct drm_file * file)100 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
101 {
102 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
103 struct drm_device *dev = crtc->dev;
104 struct drm_pending_vblank_event *event;
105 unsigned long flags;
106
107 spin_lock_irqsave(&dev->event_lock, flags);
108 event = mdp4_crtc->event;
109 if (event) {
110 /* if regular vblank case (!file) or if cancel-flip from
111 * preclose on file that requested flip, then send the
112 * event:
113 */
114 if (!file || (event->base.file_priv == file)) {
115 mdp4_crtc->event = NULL;
116 DBG("%s: send event: %p", mdp4_crtc->name, event);
117 drm_send_vblank_event(dev, mdp4_crtc->id, event);
118 }
119 }
120 spin_unlock_irqrestore(&dev->event_lock, flags);
121 }
122
unref_cursor_worker(struct drm_flip_work * work,void * val)123 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
124 {
125 struct mdp4_crtc *mdp4_crtc =
126 container_of(work, struct mdp4_crtc, unref_cursor_work);
127 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
128
129 msm_gem_put_iova(val, mdp4_kms->id);
130 drm_gem_object_unreference_unlocked(val);
131 }
132
mdp4_crtc_destroy(struct drm_crtc * crtc)133 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
134 {
135 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
136
137 drm_crtc_cleanup(crtc);
138 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
139
140 kfree(mdp4_crtc);
141 }
142
mdp4_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)143 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
144 const struct drm_display_mode *mode,
145 struct drm_display_mode *adjusted_mode)
146 {
147 return true;
148 }
149
150 /* statically (for now) map planes to mixer stage (z-order): */
151 static const int idxs[] = {
152 [VG1] = 1,
153 [VG2] = 2,
154 [RGB1] = 0,
155 [RGB2] = 0,
156 [RGB3] = 0,
157 [VG3] = 3,
158 [VG4] = 4,
159
160 };
161
162 /* setup mixer config, for which we need to consider all crtc's and
163 * the planes attached to them
164 *
165 * TODO may possibly need some extra locking here
166 */
setup_mixer(struct mdp4_kms * mdp4_kms)167 static void setup_mixer(struct mdp4_kms *mdp4_kms)
168 {
169 struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
170 struct drm_crtc *crtc;
171 uint32_t mixer_cfg = 0;
172 static const enum mdp_mixer_stage_id stages[] = {
173 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
174 };
175
176 list_for_each_entry(crtc, &config->crtc_list, head) {
177 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
178 struct drm_plane *plane;
179
180 drm_atomic_crtc_for_each_plane(plane, crtc) {
181 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
182 int idx = idxs[pipe_id];
183 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
184 pipe_id, stages[idx]);
185 }
186 }
187
188 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
189 }
190
blend_setup(struct drm_crtc * crtc)191 static void blend_setup(struct drm_crtc *crtc)
192 {
193 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
194 struct mdp4_kms *mdp4_kms = get_kms(crtc);
195 struct drm_plane *plane;
196 int i, ovlp = mdp4_crtc->ovlp;
197 bool alpha[4]= { false, false, false, false };
198
199 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
200 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
201 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
202 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
203
204 drm_atomic_crtc_for_each_plane(plane, crtc) {
205 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
206 int idx = idxs[pipe_id];
207 if (idx > 0) {
208 const struct mdp_format *format =
209 to_mdp_format(msm_framebuffer_format(plane->fb));
210 alpha[idx-1] = format->alpha_enable;
211 }
212 }
213
214 for (i = 0; i < 4; i++) {
215 uint32_t op;
216
217 if (alpha[i]) {
218 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
219 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
220 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
221 } else {
222 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
223 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
224 }
225
226 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
227 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
228 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
229 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
230 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
231 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
232 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
233 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
234 }
235
236 setup_mixer(mdp4_kms);
237 }
238
mdp4_crtc_mode_set_nofb(struct drm_crtc * crtc)239 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
240 {
241 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
242 struct mdp4_kms *mdp4_kms = get_kms(crtc);
243 enum mdp4_dma dma = mdp4_crtc->dma;
244 int ovlp = mdp4_crtc->ovlp;
245 struct drm_display_mode *mode;
246
247 if (WARN_ON(!crtc->state))
248 return;
249
250 mode = &crtc->state->adjusted_mode;
251
252 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
253 mdp4_crtc->name, mode->base.id, mode->name,
254 mode->vrefresh, mode->clock,
255 mode->hdisplay, mode->hsync_start,
256 mode->hsync_end, mode->htotal,
257 mode->vdisplay, mode->vsync_start,
258 mode->vsync_end, mode->vtotal,
259 mode->type, mode->flags);
260
261 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
262 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
263 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
264
265 /* take data from pipe: */
266 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
267 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
268 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
269 MDP4_DMA_DST_SIZE_WIDTH(0) |
270 MDP4_DMA_DST_SIZE_HEIGHT(0));
271
272 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
273 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
274 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
275 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
276 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
277
278 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
279
280 if (dma == DMA_E) {
281 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
282 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
283 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
284 }
285 }
286
mdp4_crtc_disable(struct drm_crtc * crtc)287 static void mdp4_crtc_disable(struct drm_crtc *crtc)
288 {
289 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
290 struct mdp4_kms *mdp4_kms = get_kms(crtc);
291
292 DBG("%s", mdp4_crtc->name);
293
294 if (WARN_ON(!mdp4_crtc->enabled))
295 return;
296
297 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
298 mdp4_disable(mdp4_kms);
299
300 mdp4_crtc->enabled = false;
301 }
302
mdp4_crtc_enable(struct drm_crtc * crtc)303 static void mdp4_crtc_enable(struct drm_crtc *crtc)
304 {
305 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
306 struct mdp4_kms *mdp4_kms = get_kms(crtc);
307
308 DBG("%s", mdp4_crtc->name);
309
310 if (WARN_ON(mdp4_crtc->enabled))
311 return;
312
313 mdp4_enable(mdp4_kms);
314 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
315
316 crtc_flush(crtc);
317
318 mdp4_crtc->enabled = true;
319 }
320
mdp4_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)321 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
322 struct drm_crtc_state *state)
323 {
324 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
325 DBG("%s: check", mdp4_crtc->name);
326 // TODO anything else to check?
327 return 0;
328 }
329
mdp4_crtc_atomic_begin(struct drm_crtc * crtc)330 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc)
331 {
332 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
333 DBG("%s: begin", mdp4_crtc->name);
334 }
335
mdp4_crtc_atomic_flush(struct drm_crtc * crtc)336 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc)
337 {
338 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
339 struct drm_device *dev = crtc->dev;
340 unsigned long flags;
341
342 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
343
344 WARN_ON(mdp4_crtc->event);
345
346 spin_lock_irqsave(&dev->event_lock, flags);
347 mdp4_crtc->event = crtc->state->event;
348 spin_unlock_irqrestore(&dev->event_lock, flags);
349
350 blend_setup(crtc);
351 crtc_flush(crtc);
352 request_pending(crtc, PENDING_FLIP);
353 }
354
mdp4_crtc_set_property(struct drm_crtc * crtc,struct drm_property * property,uint64_t val)355 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
356 struct drm_property *property, uint64_t val)
357 {
358 // XXX
359 return -EINVAL;
360 }
361
362 #define CURSOR_WIDTH 64
363 #define CURSOR_HEIGHT 64
364
365 /* called from IRQ to update cursor related registers (if needed). The
366 * cursor registers, other than x/y position, appear not to be double
367 * buffered, and changing them other than from vblank seems to trigger
368 * underflow.
369 */
update_cursor(struct drm_crtc * crtc)370 static void update_cursor(struct drm_crtc *crtc)
371 {
372 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
373 struct mdp4_kms *mdp4_kms = get_kms(crtc);
374 enum mdp4_dma dma = mdp4_crtc->dma;
375 unsigned long flags;
376
377 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
378 if (mdp4_crtc->cursor.stale) {
379 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
380 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
381 uint32_t iova = mdp4_crtc->cursor.next_iova;
382
383 if (next_bo) {
384 /* take a obj ref + iova ref when we start scanning out: */
385 drm_gem_object_reference(next_bo);
386 msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
387
388 /* enable cursor: */
389 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
390 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
391 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
392 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
393 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
394 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
395 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
396 } else {
397 /* disable cursor: */
398 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
399 mdp4_kms->blank_cursor_iova);
400 }
401
402 /* and drop the iova ref + obj rev when done scanning out: */
403 if (prev_bo)
404 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
405
406 mdp4_crtc->cursor.scanout_bo = next_bo;
407 mdp4_crtc->cursor.stale = false;
408 }
409
410 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
411 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
412 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
413
414 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
415 }
416
mdp4_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height)417 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
418 struct drm_file *file_priv, uint32_t handle,
419 uint32_t width, uint32_t height)
420 {
421 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
422 struct mdp4_kms *mdp4_kms = get_kms(crtc);
423 struct drm_device *dev = crtc->dev;
424 struct drm_gem_object *cursor_bo, *old_bo;
425 unsigned long flags;
426 uint32_t iova;
427 int ret;
428
429 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
430 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
431 return -EINVAL;
432 }
433
434 if (handle) {
435 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
436 if (!cursor_bo)
437 return -ENOENT;
438 } else {
439 cursor_bo = NULL;
440 }
441
442 if (cursor_bo) {
443 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
444 if (ret)
445 goto fail;
446 } else {
447 iova = 0;
448 }
449
450 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
451 old_bo = mdp4_crtc->cursor.next_bo;
452 mdp4_crtc->cursor.next_bo = cursor_bo;
453 mdp4_crtc->cursor.next_iova = iova;
454 mdp4_crtc->cursor.width = width;
455 mdp4_crtc->cursor.height = height;
456 mdp4_crtc->cursor.stale = true;
457 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
458
459 if (old_bo) {
460 /* drop our previous reference: */
461 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
462 }
463
464 request_pending(crtc, PENDING_CURSOR);
465
466 return 0;
467
468 fail:
469 drm_gem_object_unreference_unlocked(cursor_bo);
470 return ret;
471 }
472
mdp4_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)473 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
474 {
475 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
476 unsigned long flags;
477
478 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
479 mdp4_crtc->cursor.x = x;
480 mdp4_crtc->cursor.y = y;
481 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
482
483 crtc_flush(crtc);
484 request_pending(crtc, PENDING_CURSOR);
485
486 return 0;
487 }
488
489 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
490 .set_config = drm_atomic_helper_set_config,
491 .destroy = mdp4_crtc_destroy,
492 .page_flip = drm_atomic_helper_page_flip,
493 .set_property = mdp4_crtc_set_property,
494 .cursor_set = mdp4_crtc_cursor_set,
495 .cursor_move = mdp4_crtc_cursor_move,
496 .reset = drm_atomic_helper_crtc_reset,
497 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
498 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
499 };
500
501 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
502 .mode_fixup = mdp4_crtc_mode_fixup,
503 .mode_set_nofb = mdp4_crtc_mode_set_nofb,
504 .disable = mdp4_crtc_disable,
505 .enable = mdp4_crtc_enable,
506 .atomic_check = mdp4_crtc_atomic_check,
507 .atomic_begin = mdp4_crtc_atomic_begin,
508 .atomic_flush = mdp4_crtc_atomic_flush,
509 };
510
mdp4_crtc_vblank_irq(struct mdp_irq * irq,uint32_t irqstatus)511 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
512 {
513 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
514 struct drm_crtc *crtc = &mdp4_crtc->base;
515 struct msm_drm_private *priv = crtc->dev->dev_private;
516 unsigned pending;
517
518 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
519
520 pending = atomic_xchg(&mdp4_crtc->pending, 0);
521
522 if (pending & PENDING_FLIP) {
523 complete_flip(crtc, NULL);
524 }
525
526 if (pending & PENDING_CURSOR) {
527 update_cursor(crtc);
528 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
529 }
530 }
531
mdp4_crtc_err_irq(struct mdp_irq * irq,uint32_t irqstatus)532 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
533 {
534 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
535 struct drm_crtc *crtc = &mdp4_crtc->base;
536 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
537 crtc_flush(crtc);
538 }
539
mdp4_crtc_vblank(struct drm_crtc * crtc)540 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
541 {
542 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
543 return mdp4_crtc->vblank.irqmask;
544 }
545
mdp4_crtc_cancel_pending_flip(struct drm_crtc * crtc,struct drm_file * file)546 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
547 {
548 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
549 DBG("%s: cancel: %p", mdp4_crtc->name, file);
550 complete_flip(crtc, file);
551 }
552
553 /* set dma config, ie. the format the encoder wants. */
mdp4_crtc_set_config(struct drm_crtc * crtc,uint32_t config)554 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
555 {
556 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
557 struct mdp4_kms *mdp4_kms = get_kms(crtc);
558
559 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
560 }
561
562 /* set interface for routing crtc->encoder: */
mdp4_crtc_set_intf(struct drm_crtc * crtc,enum mdp4_intf intf,int mixer)563 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
564 {
565 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
566 struct mdp4_kms *mdp4_kms = get_kms(crtc);
567 uint32_t intf_sel;
568
569 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
570
571 switch (mdp4_crtc->dma) {
572 case DMA_P:
573 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
574 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
575 break;
576 case DMA_S:
577 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
578 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
579 break;
580 case DMA_E:
581 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
582 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
583 break;
584 }
585
586 if (intf == INTF_DSI_VIDEO) {
587 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
588 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
589 } else if (intf == INTF_DSI_CMD) {
590 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
591 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
592 }
593
594 mdp4_crtc->mixer = mixer;
595
596 blend_setup(crtc);
597
598 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
599
600 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
601 }
602
603 static const char *dma_names[] = {
604 "DMA_P", "DMA_S", "DMA_E",
605 };
606
607 /* initialize crtc */
mdp4_crtc_init(struct drm_device * dev,struct drm_plane * plane,int id,int ovlp_id,enum mdp4_dma dma_id)608 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
609 struct drm_plane *plane, int id, int ovlp_id,
610 enum mdp4_dma dma_id)
611 {
612 struct drm_crtc *crtc = NULL;
613 struct mdp4_crtc *mdp4_crtc;
614
615 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
616 if (!mdp4_crtc)
617 return ERR_PTR(-ENOMEM);
618
619 crtc = &mdp4_crtc->base;
620
621 mdp4_crtc->id = id;
622
623 mdp4_crtc->ovlp = ovlp_id;
624 mdp4_crtc->dma = dma_id;
625
626 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
627 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
628
629 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
630 mdp4_crtc->err.irq = mdp4_crtc_err_irq;
631
632 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
633 dma_names[dma_id], ovlp_id);
634
635 spin_lock_init(&mdp4_crtc->cursor.lock);
636
637 drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
638 "unref cursor", unref_cursor_worker);
639
640 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
641 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
642 plane->crtc = crtc;
643
644 mdp4_plane_install_properties(plane, &crtc->base);
645
646 return crtc;
647 }
648