1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* ethtool support for ixgbe */
30
31 #include <linux/interrupt.h>
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/slab.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/ethtool.h>
38 #include <linux/vmalloc.h>
39 #include <linux/highmem.h>
40 #include <linux/uaccess.h>
41
42 #include "ixgbe.h"
43 #include "ixgbe_phy.h"
44
45
46 #define IXGBE_ALL_RAR_ENTRIES 16
47
48 enum {NETDEV_STATS, IXGBE_STATS};
49
50 struct ixgbe_stats {
51 char stat_string[ETH_GSTRING_LEN];
52 int type;
53 int sizeof_stat;
54 int stat_offset;
55 };
56
57 #define IXGBE_STAT(m) IXGBE_STATS, \
58 sizeof(((struct ixgbe_adapter *)0)->m), \
59 offsetof(struct ixgbe_adapter, m)
60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
61 sizeof(((struct rtnl_link_stats64 *)0)->m), \
62 offsetof(struct rtnl_link_stats64, m)
63
64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
73 {"lsc_int", IXGBE_STAT(lsc_int)},
74 {"tx_busy", IXGBE_STAT(tx_busy)},
75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
80 {"multicast", IXGBE_NETDEV_STAT(multicast)},
81 {"broadcast", IXGBE_STAT(stats.bprc)},
82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
83 {"collisions", IXGBE_NETDEV_STAT(collisions)},
84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
99 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
114 #ifdef IXGBE_FCOE
115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
123 #endif /* IXGBE_FCOE */
124 };
125
126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
127 * we set the num_rx_queues to evaluate to num_tx_queues. This is
128 * used because we do not have a good way to get the max number of
129 * rx queues with CONFIG_RPS disabled.
130 */
131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132
133 #define IXGBE_QUEUE_STATS_LEN ( \
134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
137 #define IXGBE_PB_STATS_LEN ( \
138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 / sizeof(u64))
143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
144 IXGBE_PB_STATS_LEN + \
145 IXGBE_QUEUE_STATS_LEN)
146
147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
148 "Register test (offline)", "Eeprom test (offline)",
149 "Interrupt test (offline)", "Loopback test (offline)",
150 "Link test (on/offline)"
151 };
152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153
ixgbe_get_settings(struct net_device * netdev,struct ethtool_cmd * ecmd)154 static int ixgbe_get_settings(struct net_device *netdev,
155 struct ethtool_cmd *ecmd)
156 {
157 struct ixgbe_adapter *adapter = netdev_priv(netdev);
158 struct ixgbe_hw *hw = &adapter->hw;
159 ixgbe_link_speed supported_link;
160 u32 link_speed = 0;
161 bool autoneg = false;
162 bool link_up;
163
164 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
165
166 /* set the supported link speeds */
167 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
168 ecmd->supported |= SUPPORTED_10000baseT_Full;
169 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
170 ecmd->supported |= SUPPORTED_1000baseT_Full;
171 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
172 ecmd->supported |= SUPPORTED_100baseT_Full;
173
174 /* set the advertised speeds */
175 if (hw->phy.autoneg_advertised) {
176 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
177 ecmd->advertising |= ADVERTISED_100baseT_Full;
178 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
179 ecmd->advertising |= ADVERTISED_10000baseT_Full;
180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
181 ecmd->advertising |= ADVERTISED_1000baseT_Full;
182 } else {
183 /* default modes in case phy.autoneg_advertised isn't set */
184 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
185 ecmd->advertising |= ADVERTISED_10000baseT_Full;
186 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
187 ecmd->advertising |= ADVERTISED_1000baseT_Full;
188 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
189 ecmd->advertising |= ADVERTISED_100baseT_Full;
190
191 if (hw->phy.multispeed_fiber && !autoneg) {
192 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
193 ecmd->advertising = ADVERTISED_10000baseT_Full;
194 }
195 }
196
197 if (autoneg) {
198 ecmd->supported |= SUPPORTED_Autoneg;
199 ecmd->advertising |= ADVERTISED_Autoneg;
200 ecmd->autoneg = AUTONEG_ENABLE;
201 } else
202 ecmd->autoneg = AUTONEG_DISABLE;
203
204 ecmd->transceiver = XCVR_EXTERNAL;
205
206 /* Determine the remaining settings based on the PHY type. */
207 switch (adapter->hw.phy.type) {
208 case ixgbe_phy_tn:
209 case ixgbe_phy_aq:
210 case ixgbe_phy_cu_unknown:
211 ecmd->supported |= SUPPORTED_TP;
212 ecmd->advertising |= ADVERTISED_TP;
213 ecmd->port = PORT_TP;
214 break;
215 case ixgbe_phy_qt:
216 ecmd->supported |= SUPPORTED_FIBRE;
217 ecmd->advertising |= ADVERTISED_FIBRE;
218 ecmd->port = PORT_FIBRE;
219 break;
220 case ixgbe_phy_nl:
221 case ixgbe_phy_sfp_passive_tyco:
222 case ixgbe_phy_sfp_passive_unknown:
223 case ixgbe_phy_sfp_ftl:
224 case ixgbe_phy_sfp_avago:
225 case ixgbe_phy_sfp_intel:
226 case ixgbe_phy_sfp_unknown:
227 /* SFP+ devices, further checking needed */
228 switch (adapter->hw.phy.sfp_type) {
229 case ixgbe_sfp_type_da_cu:
230 case ixgbe_sfp_type_da_cu_core0:
231 case ixgbe_sfp_type_da_cu_core1:
232 ecmd->supported |= SUPPORTED_FIBRE;
233 ecmd->advertising |= ADVERTISED_FIBRE;
234 ecmd->port = PORT_DA;
235 break;
236 case ixgbe_sfp_type_sr:
237 case ixgbe_sfp_type_lr:
238 case ixgbe_sfp_type_srlr_core0:
239 case ixgbe_sfp_type_srlr_core1:
240 case ixgbe_sfp_type_1g_sx_core0:
241 case ixgbe_sfp_type_1g_sx_core1:
242 case ixgbe_sfp_type_1g_lx_core0:
243 case ixgbe_sfp_type_1g_lx_core1:
244 ecmd->supported |= SUPPORTED_FIBRE;
245 ecmd->advertising |= ADVERTISED_FIBRE;
246 ecmd->port = PORT_FIBRE;
247 break;
248 case ixgbe_sfp_type_not_present:
249 ecmd->supported |= SUPPORTED_FIBRE;
250 ecmd->advertising |= ADVERTISED_FIBRE;
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_sfp_type_1g_cu_core0:
254 case ixgbe_sfp_type_1g_cu_core1:
255 ecmd->supported |= SUPPORTED_TP;
256 ecmd->advertising |= ADVERTISED_TP;
257 ecmd->port = PORT_TP;
258 break;
259 case ixgbe_sfp_type_unknown:
260 default:
261 ecmd->supported |= SUPPORTED_FIBRE;
262 ecmd->advertising |= ADVERTISED_FIBRE;
263 ecmd->port = PORT_OTHER;
264 break;
265 }
266 break;
267 case ixgbe_phy_xaui:
268 ecmd->supported |= SUPPORTED_FIBRE;
269 ecmd->advertising |= ADVERTISED_FIBRE;
270 ecmd->port = PORT_NONE;
271 break;
272 case ixgbe_phy_unknown:
273 case ixgbe_phy_generic:
274 case ixgbe_phy_sfp_unsupported:
275 default:
276 ecmd->supported |= SUPPORTED_FIBRE;
277 ecmd->advertising |= ADVERTISED_FIBRE;
278 ecmd->port = PORT_OTHER;
279 break;
280 }
281
282 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
283 if (link_up) {
284 switch (link_speed) {
285 case IXGBE_LINK_SPEED_10GB_FULL:
286 ethtool_cmd_speed_set(ecmd, SPEED_10000);
287 break;
288 case IXGBE_LINK_SPEED_1GB_FULL:
289 ethtool_cmd_speed_set(ecmd, SPEED_1000);
290 break;
291 case IXGBE_LINK_SPEED_100_FULL:
292 ethtool_cmd_speed_set(ecmd, SPEED_100);
293 break;
294 default:
295 break;
296 }
297 ecmd->duplex = DUPLEX_FULL;
298 } else {
299 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
300 ecmd->duplex = DUPLEX_UNKNOWN;
301 }
302
303 return 0;
304 }
305
ixgbe_set_settings(struct net_device * netdev,struct ethtool_cmd * ecmd)306 static int ixgbe_set_settings(struct net_device *netdev,
307 struct ethtool_cmd *ecmd)
308 {
309 struct ixgbe_adapter *adapter = netdev_priv(netdev);
310 struct ixgbe_hw *hw = &adapter->hw;
311 u32 advertised, old;
312 s32 err = 0;
313
314 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
315 (hw->phy.multispeed_fiber)) {
316 /*
317 * this function does not support duplex forcing, but can
318 * limit the advertising of the adapter to the specified speed
319 */
320 if (ecmd->advertising & ~ecmd->supported)
321 return -EINVAL;
322
323 /* only allow one speed at a time if no autoneg */
324 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
325 if (ecmd->advertising ==
326 (ADVERTISED_10000baseT_Full |
327 ADVERTISED_1000baseT_Full))
328 return -EINVAL;
329 }
330
331 old = hw->phy.autoneg_advertised;
332 advertised = 0;
333 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
334 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
335
336 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
337 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
338
339 if (ecmd->advertising & ADVERTISED_100baseT_Full)
340 advertised |= IXGBE_LINK_SPEED_100_FULL;
341
342 if (old == advertised)
343 return err;
344 /* this sets the link speed and restarts auto-neg */
345 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
346 usleep_range(1000, 2000);
347
348 hw->mac.autotry_restart = true;
349 err = hw->mac.ops.setup_link(hw, advertised, true);
350 if (err) {
351 e_info(probe, "setup link failed with code %d\n", err);
352 hw->mac.ops.setup_link(hw, old, true);
353 }
354 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
355 } else {
356 /* in this case we currently only support 10Gb/FULL */
357 u32 speed = ethtool_cmd_speed(ecmd);
358 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
359 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
360 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
361 return -EINVAL;
362 }
363
364 return err;
365 }
366
ixgbe_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)367 static void ixgbe_get_pauseparam(struct net_device *netdev,
368 struct ethtool_pauseparam *pause)
369 {
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 struct ixgbe_hw *hw = &adapter->hw;
372
373 if (ixgbe_device_supports_autoneg_fc(hw) &&
374 !hw->fc.disable_fc_autoneg)
375 pause->autoneg = 1;
376 else
377 pause->autoneg = 0;
378
379 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
380 pause->rx_pause = 1;
381 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
382 pause->tx_pause = 1;
383 } else if (hw->fc.current_mode == ixgbe_fc_full) {
384 pause->rx_pause = 1;
385 pause->tx_pause = 1;
386 }
387 }
388
ixgbe_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)389 static int ixgbe_set_pauseparam(struct net_device *netdev,
390 struct ethtool_pauseparam *pause)
391 {
392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
393 struct ixgbe_hw *hw = &adapter->hw;
394 struct ixgbe_fc_info fc = hw->fc;
395
396 /* 82598 does no support link flow control with DCB enabled */
397 if ((hw->mac.type == ixgbe_mac_82598EB) &&
398 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
399 return -EINVAL;
400
401 /* some devices do not support autoneg of link flow control */
402 if ((pause->autoneg == AUTONEG_ENABLE) &&
403 !ixgbe_device_supports_autoneg_fc(hw))
404 return -EINVAL;
405
406 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
407
408 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
409 fc.requested_mode = ixgbe_fc_full;
410 else if (pause->rx_pause && !pause->tx_pause)
411 fc.requested_mode = ixgbe_fc_rx_pause;
412 else if (!pause->rx_pause && pause->tx_pause)
413 fc.requested_mode = ixgbe_fc_tx_pause;
414 else
415 fc.requested_mode = ixgbe_fc_none;
416
417 /* if the thing changed then we'll update and use new autoneg */
418 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
419 hw->fc = fc;
420 if (netif_running(netdev))
421 ixgbe_reinit_locked(adapter);
422 else
423 ixgbe_reset(adapter);
424 }
425
426 return 0;
427 }
428
ixgbe_get_msglevel(struct net_device * netdev)429 static u32 ixgbe_get_msglevel(struct net_device *netdev)
430 {
431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
432 return adapter->msg_enable;
433 }
434
ixgbe_set_msglevel(struct net_device * netdev,u32 data)435 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
436 {
437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
438 adapter->msg_enable = data;
439 }
440
ixgbe_get_regs_len(struct net_device * netdev)441 static int ixgbe_get_regs_len(struct net_device *netdev)
442 {
443 #define IXGBE_REGS_LEN 1139
444 return IXGBE_REGS_LEN * sizeof(u32);
445 }
446
447 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
448
ixgbe_get_regs(struct net_device * netdev,struct ethtool_regs * regs,void * p)449 static void ixgbe_get_regs(struct net_device *netdev,
450 struct ethtool_regs *regs, void *p)
451 {
452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
453 struct ixgbe_hw *hw = &adapter->hw;
454 u32 *regs_buff = p;
455 u8 i;
456
457 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
458
459 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
460 hw->device_id;
461
462 /* General Registers */
463 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
464 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
465 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
466 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
467 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
468 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
469 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
470 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
471
472 /* NVM Register */
473 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
474 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
475 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
476 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
477 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
478 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
479 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
480 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
481 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
482 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
483
484 /* Interrupt */
485 /* don't read EICR because it can clear interrupt causes, instead
486 * read EICS which is a shadow but doesn't clear EICR */
487 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
488 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
489 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
490 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
491 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
492 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
493 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
494 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
495 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
496 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
497 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
498 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
499
500 /* Flow Control */
501 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
502 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
503 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
504 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
505 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
506 for (i = 0; i < 8; i++) {
507 switch (hw->mac.type) {
508 case ixgbe_mac_82598EB:
509 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
510 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
511 break;
512 case ixgbe_mac_82599EB:
513 case ixgbe_mac_X540:
514 case ixgbe_mac_X550:
515 case ixgbe_mac_X550EM_x:
516 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
517 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
518 break;
519 default:
520 break;
521 }
522 }
523 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
524 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
525
526 /* Receive DMA */
527 for (i = 0; i < 64; i++)
528 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
529 for (i = 0; i < 64; i++)
530 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
531 for (i = 0; i < 64; i++)
532 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
533 for (i = 0; i < 64; i++)
534 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
535 for (i = 0; i < 64; i++)
536 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
537 for (i = 0; i < 64; i++)
538 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
539 for (i = 0; i < 16; i++)
540 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
541 for (i = 0; i < 16; i++)
542 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
543 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
544 for (i = 0; i < 8; i++)
545 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
546 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
547 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
548
549 /* Receive */
550 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
551 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
552 for (i = 0; i < 16; i++)
553 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
554 for (i = 0; i < 16; i++)
555 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
556 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
557 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
558 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
559 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
560 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
561 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
562 for (i = 0; i < 8; i++)
563 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
564 for (i = 0; i < 8; i++)
565 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
566 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
567
568 /* Transmit */
569 for (i = 0; i < 32; i++)
570 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
571 for (i = 0; i < 32; i++)
572 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
573 for (i = 0; i < 32; i++)
574 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
575 for (i = 0; i < 32; i++)
576 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
577 for (i = 0; i < 32; i++)
578 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
579 for (i = 0; i < 32; i++)
580 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
581 for (i = 0; i < 32; i++)
582 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
583 for (i = 0; i < 32; i++)
584 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
585 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
586 for (i = 0; i < 16; i++)
587 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
588 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
589 for (i = 0; i < 8; i++)
590 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
591 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
592
593 /* Wake Up */
594 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
595 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
596 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
597 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
598 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
599 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
600 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
601 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
602 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
603
604 /* DCB */
605 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
606 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
607
608 switch (hw->mac.type) {
609 case ixgbe_mac_82598EB:
610 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
611 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
612 for (i = 0; i < 8; i++)
613 regs_buff[833 + i] =
614 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
615 for (i = 0; i < 8; i++)
616 regs_buff[841 + i] =
617 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
618 for (i = 0; i < 8; i++)
619 regs_buff[849 + i] =
620 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[857 + i] =
623 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
624 break;
625 case ixgbe_mac_82599EB:
626 case ixgbe_mac_X540:
627 case ixgbe_mac_X550:
628 case ixgbe_mac_X550EM_x:
629 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
630 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
631 for (i = 0; i < 8; i++)
632 regs_buff[833 + i] =
633 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
634 for (i = 0; i < 8; i++)
635 regs_buff[841 + i] =
636 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
637 for (i = 0; i < 8; i++)
638 regs_buff[849 + i] =
639 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
640 for (i = 0; i < 8; i++)
641 regs_buff[857 + i] =
642 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
643 break;
644 default:
645 break;
646 }
647
648 for (i = 0; i < 8; i++)
649 regs_buff[865 + i] =
650 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
651 for (i = 0; i < 8; i++)
652 regs_buff[873 + i] =
653 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
654
655 /* Statistics */
656 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
657 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
658 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
659 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
660 for (i = 0; i < 8; i++)
661 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
662 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
663 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
664 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
665 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
666 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
667 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
668 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
669 for (i = 0; i < 8; i++)
670 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
671 for (i = 0; i < 8; i++)
672 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
673 for (i = 0; i < 8; i++)
674 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
675 for (i = 0; i < 8; i++)
676 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
677 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
678 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
679 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
680 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
681 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
682 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
683 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
684 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
685 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
686 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
687 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
688 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
689 for (i = 0; i < 8; i++)
690 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
691 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
692 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
693 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
694 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
695 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
696 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
697 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
698 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
699 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
700 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
701 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
702 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
703 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
704 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
705 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
706 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
707 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
708 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
709 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
710 for (i = 0; i < 16; i++)
711 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
712 for (i = 0; i < 16; i++)
713 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
714 for (i = 0; i < 16; i++)
715 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
716 for (i = 0; i < 16; i++)
717 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
718
719 /* MAC */
720 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
721 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
722 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
723 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
724 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
725 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
726 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
727 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
728 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
729 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
730 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
731 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
732 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
733 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
734 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
735 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
736 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
737 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
738 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
739 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
740 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
741 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
742 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
743 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
744 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
745 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
746 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
747 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
748 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
749 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
750 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
751 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
752 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
753
754 /* Diagnostic */
755 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
756 for (i = 0; i < 8; i++)
757 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
758 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
759 for (i = 0; i < 4; i++)
760 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
761 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
762 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
763 for (i = 0; i < 8; i++)
764 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
765 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
766 for (i = 0; i < 4; i++)
767 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
768 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
769 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
770 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
771 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
772 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
773 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
774 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
775 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
776 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
777 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
778 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
779 for (i = 0; i < 8; i++)
780 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
781 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
782 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
783 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
784 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
785 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
786 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
787 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
788 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
789 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
790
791 /* 82599 X540 specific registers */
792 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
793
794 /* 82599 X540 specific DCB registers */
795 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
796 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
797 for (i = 0; i < 4; i++)
798 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
799 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
800 /* same as RTTQCNRM */
801 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
802 /* same as RTTQCNRR */
803
804 /* X540 specific DCB registers */
805 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
806 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
807 }
808
ixgbe_get_eeprom_len(struct net_device * netdev)809 static int ixgbe_get_eeprom_len(struct net_device *netdev)
810 {
811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
812 return adapter->hw.eeprom.word_size * 2;
813 }
814
ixgbe_get_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)815 static int ixgbe_get_eeprom(struct net_device *netdev,
816 struct ethtool_eeprom *eeprom, u8 *bytes)
817 {
818 struct ixgbe_adapter *adapter = netdev_priv(netdev);
819 struct ixgbe_hw *hw = &adapter->hw;
820 u16 *eeprom_buff;
821 int first_word, last_word, eeprom_len;
822 int ret_val = 0;
823 u16 i;
824
825 if (eeprom->len == 0)
826 return -EINVAL;
827
828 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
829
830 first_word = eeprom->offset >> 1;
831 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
832 eeprom_len = last_word - first_word + 1;
833
834 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
835 if (!eeprom_buff)
836 return -ENOMEM;
837
838 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
839 eeprom_buff);
840
841 /* Device's eeprom is always little-endian, word addressable */
842 for (i = 0; i < eeprom_len; i++)
843 le16_to_cpus(&eeprom_buff[i]);
844
845 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
846 kfree(eeprom_buff);
847
848 return ret_val;
849 }
850
ixgbe_set_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)851 static int ixgbe_set_eeprom(struct net_device *netdev,
852 struct ethtool_eeprom *eeprom, u8 *bytes)
853 {
854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
855 struct ixgbe_hw *hw = &adapter->hw;
856 u16 *eeprom_buff;
857 void *ptr;
858 int max_len, first_word, last_word, ret_val = 0;
859 u16 i;
860
861 if (eeprom->len == 0)
862 return -EINVAL;
863
864 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
865 return -EINVAL;
866
867 max_len = hw->eeprom.word_size * 2;
868
869 first_word = eeprom->offset >> 1;
870 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
871 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
872 if (!eeprom_buff)
873 return -ENOMEM;
874
875 ptr = eeprom_buff;
876
877 if (eeprom->offset & 1) {
878 /*
879 * need read/modify/write of first changed EEPROM word
880 * only the second byte of the word is being modified
881 */
882 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
883 if (ret_val)
884 goto err;
885
886 ptr++;
887 }
888 if ((eeprom->offset + eeprom->len) & 1) {
889 /*
890 * need read/modify/write of last changed EEPROM word
891 * only the first byte of the word is being modified
892 */
893 ret_val = hw->eeprom.ops.read(hw, last_word,
894 &eeprom_buff[last_word - first_word]);
895 if (ret_val)
896 goto err;
897 }
898
899 /* Device's eeprom is always little-endian, word addressable */
900 for (i = 0; i < last_word - first_word + 1; i++)
901 le16_to_cpus(&eeprom_buff[i]);
902
903 memcpy(ptr, bytes, eeprom->len);
904
905 for (i = 0; i < last_word - first_word + 1; i++)
906 cpu_to_le16s(&eeprom_buff[i]);
907
908 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
909 last_word - first_word + 1,
910 eeprom_buff);
911
912 /* Update the checksum */
913 if (ret_val == 0)
914 hw->eeprom.ops.update_checksum(hw);
915
916 err:
917 kfree(eeprom_buff);
918 return ret_val;
919 }
920
ixgbe_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * drvinfo)921 static void ixgbe_get_drvinfo(struct net_device *netdev,
922 struct ethtool_drvinfo *drvinfo)
923 {
924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
925 u32 nvm_track_id;
926
927 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
928 strlcpy(drvinfo->version, ixgbe_driver_version,
929 sizeof(drvinfo->version));
930
931 nvm_track_id = (adapter->eeprom_verh << 16) |
932 adapter->eeprom_verl;
933 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
934 nvm_track_id);
935
936 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
937 sizeof(drvinfo->bus_info));
938 drvinfo->n_stats = IXGBE_STATS_LEN;
939 drvinfo->testinfo_len = IXGBE_TEST_LEN;
940 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
941 }
942
ixgbe_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)943 static void ixgbe_get_ringparam(struct net_device *netdev,
944 struct ethtool_ringparam *ring)
945 {
946 struct ixgbe_adapter *adapter = netdev_priv(netdev);
947 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
948 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
949
950 ring->rx_max_pending = IXGBE_MAX_RXD;
951 ring->tx_max_pending = IXGBE_MAX_TXD;
952 ring->rx_pending = rx_ring->count;
953 ring->tx_pending = tx_ring->count;
954 }
955
ixgbe_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)956 static int ixgbe_set_ringparam(struct net_device *netdev,
957 struct ethtool_ringparam *ring)
958 {
959 struct ixgbe_adapter *adapter = netdev_priv(netdev);
960 struct ixgbe_ring *temp_ring;
961 int i, err = 0;
962 u32 new_rx_count, new_tx_count;
963
964 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
965 return -EINVAL;
966
967 new_tx_count = clamp_t(u32, ring->tx_pending,
968 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
969 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
970
971 new_rx_count = clamp_t(u32, ring->rx_pending,
972 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
973 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
974
975 if ((new_tx_count == adapter->tx_ring_count) &&
976 (new_rx_count == adapter->rx_ring_count)) {
977 /* nothing to do */
978 return 0;
979 }
980
981 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
982 usleep_range(1000, 2000);
983
984 if (!netif_running(adapter->netdev)) {
985 for (i = 0; i < adapter->num_tx_queues; i++)
986 adapter->tx_ring[i]->count = new_tx_count;
987 for (i = 0; i < adapter->num_rx_queues; i++)
988 adapter->rx_ring[i]->count = new_rx_count;
989 adapter->tx_ring_count = new_tx_count;
990 adapter->rx_ring_count = new_rx_count;
991 goto clear_reset;
992 }
993
994 /* allocate temporary buffer to store rings in */
995 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
996 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
997
998 if (!temp_ring) {
999 err = -ENOMEM;
1000 goto clear_reset;
1001 }
1002
1003 ixgbe_down(adapter);
1004
1005 /*
1006 * Setup new Tx resources and free the old Tx resources in that order.
1007 * We can then assign the new resources to the rings via a memcpy.
1008 * The advantage to this approach is that we are guaranteed to still
1009 * have resources even in the case of an allocation failure.
1010 */
1011 if (new_tx_count != adapter->tx_ring_count) {
1012 for (i = 0; i < adapter->num_tx_queues; i++) {
1013 memcpy(&temp_ring[i], adapter->tx_ring[i],
1014 sizeof(struct ixgbe_ring));
1015
1016 temp_ring[i].count = new_tx_count;
1017 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1018 if (err) {
1019 while (i) {
1020 i--;
1021 ixgbe_free_tx_resources(&temp_ring[i]);
1022 }
1023 goto err_setup;
1024 }
1025 }
1026
1027 for (i = 0; i < adapter->num_tx_queues; i++) {
1028 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1029
1030 memcpy(adapter->tx_ring[i], &temp_ring[i],
1031 sizeof(struct ixgbe_ring));
1032 }
1033
1034 adapter->tx_ring_count = new_tx_count;
1035 }
1036
1037 /* Repeat the process for the Rx rings if needed */
1038 if (new_rx_count != adapter->rx_ring_count) {
1039 for (i = 0; i < adapter->num_rx_queues; i++) {
1040 memcpy(&temp_ring[i], adapter->rx_ring[i],
1041 sizeof(struct ixgbe_ring));
1042
1043 temp_ring[i].count = new_rx_count;
1044 err = ixgbe_setup_rx_resources(&temp_ring[i]);
1045 if (err) {
1046 while (i) {
1047 i--;
1048 ixgbe_free_rx_resources(&temp_ring[i]);
1049 }
1050 goto err_setup;
1051 }
1052
1053 }
1054
1055 for (i = 0; i < adapter->num_rx_queues; i++) {
1056 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1057
1058 memcpy(adapter->rx_ring[i], &temp_ring[i],
1059 sizeof(struct ixgbe_ring));
1060 }
1061
1062 adapter->rx_ring_count = new_rx_count;
1063 }
1064
1065 err_setup:
1066 ixgbe_up(adapter);
1067 vfree(temp_ring);
1068 clear_reset:
1069 clear_bit(__IXGBE_RESETTING, &adapter->state);
1070 return err;
1071 }
1072
ixgbe_get_sset_count(struct net_device * netdev,int sset)1073 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1074 {
1075 switch (sset) {
1076 case ETH_SS_TEST:
1077 return IXGBE_TEST_LEN;
1078 case ETH_SS_STATS:
1079 return IXGBE_STATS_LEN;
1080 default:
1081 return -EOPNOTSUPP;
1082 }
1083 }
1084
ixgbe_get_ethtool_stats(struct net_device * netdev,struct ethtool_stats * stats,u64 * data)1085 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1086 struct ethtool_stats *stats, u64 *data)
1087 {
1088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1089 struct rtnl_link_stats64 temp;
1090 const struct rtnl_link_stats64 *net_stats;
1091 unsigned int start;
1092 struct ixgbe_ring *ring;
1093 int i, j;
1094 char *p = NULL;
1095
1096 ixgbe_update_stats(adapter);
1097 net_stats = dev_get_stats(netdev, &temp);
1098 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1099 switch (ixgbe_gstrings_stats[i].type) {
1100 case NETDEV_STATS:
1101 p = (char *) net_stats +
1102 ixgbe_gstrings_stats[i].stat_offset;
1103 break;
1104 case IXGBE_STATS:
1105 p = (char *) adapter +
1106 ixgbe_gstrings_stats[i].stat_offset;
1107 break;
1108 default:
1109 data[i] = 0;
1110 continue;
1111 }
1112
1113 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1114 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1115 }
1116 for (j = 0; j < netdev->num_tx_queues; j++) {
1117 ring = adapter->tx_ring[j];
1118 if (!ring) {
1119 data[i] = 0;
1120 data[i+1] = 0;
1121 i += 2;
1122 #ifdef BP_EXTENDED_STATS
1123 data[i] = 0;
1124 data[i+1] = 0;
1125 data[i+2] = 0;
1126 i += 3;
1127 #endif
1128 continue;
1129 }
1130
1131 do {
1132 start = u64_stats_fetch_begin_irq(&ring->syncp);
1133 data[i] = ring->stats.packets;
1134 data[i+1] = ring->stats.bytes;
1135 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1136 i += 2;
1137 #ifdef BP_EXTENDED_STATS
1138 data[i] = ring->stats.yields;
1139 data[i+1] = ring->stats.misses;
1140 data[i+2] = ring->stats.cleaned;
1141 i += 3;
1142 #endif
1143 }
1144 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1145 ring = adapter->rx_ring[j];
1146 if (!ring) {
1147 data[i] = 0;
1148 data[i+1] = 0;
1149 i += 2;
1150 #ifdef BP_EXTENDED_STATS
1151 data[i] = 0;
1152 data[i+1] = 0;
1153 data[i+2] = 0;
1154 i += 3;
1155 #endif
1156 continue;
1157 }
1158
1159 do {
1160 start = u64_stats_fetch_begin_irq(&ring->syncp);
1161 data[i] = ring->stats.packets;
1162 data[i+1] = ring->stats.bytes;
1163 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1164 i += 2;
1165 #ifdef BP_EXTENDED_STATS
1166 data[i] = ring->stats.yields;
1167 data[i+1] = ring->stats.misses;
1168 data[i+2] = ring->stats.cleaned;
1169 i += 3;
1170 #endif
1171 }
1172
1173 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1174 data[i++] = adapter->stats.pxontxc[j];
1175 data[i++] = adapter->stats.pxofftxc[j];
1176 }
1177 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1178 data[i++] = adapter->stats.pxonrxc[j];
1179 data[i++] = adapter->stats.pxoffrxc[j];
1180 }
1181 }
1182
ixgbe_get_strings(struct net_device * netdev,u32 stringset,u8 * data)1183 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1184 u8 *data)
1185 {
1186 char *p = (char *)data;
1187 int i;
1188
1189 switch (stringset) {
1190 case ETH_SS_TEST:
1191 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1192 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1193 data += ETH_GSTRING_LEN;
1194 }
1195 break;
1196 case ETH_SS_STATS:
1197 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1198 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1199 ETH_GSTRING_LEN);
1200 p += ETH_GSTRING_LEN;
1201 }
1202 for (i = 0; i < netdev->num_tx_queues; i++) {
1203 sprintf(p, "tx_queue_%u_packets", i);
1204 p += ETH_GSTRING_LEN;
1205 sprintf(p, "tx_queue_%u_bytes", i);
1206 p += ETH_GSTRING_LEN;
1207 #ifdef BP_EXTENDED_STATS
1208 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
1209 p += ETH_GSTRING_LEN;
1210 sprintf(p, "tx_queue_%u_bp_misses", i);
1211 p += ETH_GSTRING_LEN;
1212 sprintf(p, "tx_queue_%u_bp_cleaned", i);
1213 p += ETH_GSTRING_LEN;
1214 #endif /* BP_EXTENDED_STATS */
1215 }
1216 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1217 sprintf(p, "rx_queue_%u_packets", i);
1218 p += ETH_GSTRING_LEN;
1219 sprintf(p, "rx_queue_%u_bytes", i);
1220 p += ETH_GSTRING_LEN;
1221 #ifdef BP_EXTENDED_STATS
1222 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
1223 p += ETH_GSTRING_LEN;
1224 sprintf(p, "rx_queue_%u_bp_misses", i);
1225 p += ETH_GSTRING_LEN;
1226 sprintf(p, "rx_queue_%u_bp_cleaned", i);
1227 p += ETH_GSTRING_LEN;
1228 #endif /* BP_EXTENDED_STATS */
1229 }
1230 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1231 sprintf(p, "tx_pb_%u_pxon", i);
1232 p += ETH_GSTRING_LEN;
1233 sprintf(p, "tx_pb_%u_pxoff", i);
1234 p += ETH_GSTRING_LEN;
1235 }
1236 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1237 sprintf(p, "rx_pb_%u_pxon", i);
1238 p += ETH_GSTRING_LEN;
1239 sprintf(p, "rx_pb_%u_pxoff", i);
1240 p += ETH_GSTRING_LEN;
1241 }
1242 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1243 break;
1244 }
1245 }
1246
ixgbe_link_test(struct ixgbe_adapter * adapter,u64 * data)1247 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1248 {
1249 struct ixgbe_hw *hw = &adapter->hw;
1250 bool link_up;
1251 u32 link_speed = 0;
1252
1253 if (ixgbe_removed(hw->hw_addr)) {
1254 *data = 1;
1255 return 1;
1256 }
1257 *data = 0;
1258
1259 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1260 if (link_up)
1261 return *data;
1262 else
1263 *data = 1;
1264 return *data;
1265 }
1266
1267 /* ethtool register test data */
1268 struct ixgbe_reg_test {
1269 u16 reg;
1270 u8 array_len;
1271 u8 test_type;
1272 u32 mask;
1273 u32 write;
1274 };
1275
1276 /* In the hardware, registers are laid out either singly, in arrays
1277 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1278 * most tests take place on arrays or single registers (handled
1279 * as a single-element array) and special-case the tables.
1280 * Table tests are always pattern tests.
1281 *
1282 * We also make provision for some required setup steps by specifying
1283 * registers to be written without any read-back testing.
1284 */
1285
1286 #define PATTERN_TEST 1
1287 #define SET_READ_TEST 2
1288 #define WRITE_NO_TEST 3
1289 #define TABLE32_TEST 4
1290 #define TABLE64_TEST_LO 5
1291 #define TABLE64_TEST_HI 6
1292
1293 /* default 82599 register test */
1294 static const struct ixgbe_reg_test reg_test_82599[] = {
1295 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1296 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1297 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1298 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1299 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1300 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1301 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1302 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1303 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1304 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1305 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1306 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1307 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1308 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1309 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1310 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1311 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1312 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1313 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1314 { .reg = 0 }
1315 };
1316
1317 /* default 82598 register test */
1318 static const struct ixgbe_reg_test reg_test_82598[] = {
1319 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1320 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1321 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1322 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1323 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1324 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1325 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1326 /* Enable all four RX queues before testing. */
1327 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1328 /* RDH is read-only for 82598, only test RDT. */
1329 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1330 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1331 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1332 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1333 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1334 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1335 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1336 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1337 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1338 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1339 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1340 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1341 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1342 { .reg = 0 }
1343 };
1344
reg_pattern_test(struct ixgbe_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1345 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1346 u32 mask, u32 write)
1347 {
1348 u32 pat, val, before;
1349 static const u32 test_pattern[] = {
1350 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1351
1352 if (ixgbe_removed(adapter->hw.hw_addr)) {
1353 *data = 1;
1354 return true;
1355 }
1356 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1357 before = ixgbe_read_reg(&adapter->hw, reg);
1358 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1359 val = ixgbe_read_reg(&adapter->hw, reg);
1360 if (val != (test_pattern[pat] & write & mask)) {
1361 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1362 reg, val, (test_pattern[pat] & write & mask));
1363 *data = reg;
1364 ixgbe_write_reg(&adapter->hw, reg, before);
1365 return true;
1366 }
1367 ixgbe_write_reg(&adapter->hw, reg, before);
1368 }
1369 return false;
1370 }
1371
reg_set_and_check(struct ixgbe_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1372 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1373 u32 mask, u32 write)
1374 {
1375 u32 val, before;
1376
1377 if (ixgbe_removed(adapter->hw.hw_addr)) {
1378 *data = 1;
1379 return true;
1380 }
1381 before = ixgbe_read_reg(&adapter->hw, reg);
1382 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1383 val = ixgbe_read_reg(&adapter->hw, reg);
1384 if ((write & mask) != (val & mask)) {
1385 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1386 reg, (val & mask), (write & mask));
1387 *data = reg;
1388 ixgbe_write_reg(&adapter->hw, reg, before);
1389 return true;
1390 }
1391 ixgbe_write_reg(&adapter->hw, reg, before);
1392 return false;
1393 }
1394
ixgbe_reg_test(struct ixgbe_adapter * adapter,u64 * data)1395 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1396 {
1397 const struct ixgbe_reg_test *test;
1398 u32 value, before, after;
1399 u32 i, toggle;
1400
1401 if (ixgbe_removed(adapter->hw.hw_addr)) {
1402 e_err(drv, "Adapter removed - register test blocked\n");
1403 *data = 1;
1404 return 1;
1405 }
1406 switch (adapter->hw.mac.type) {
1407 case ixgbe_mac_82598EB:
1408 toggle = 0x7FFFF3FF;
1409 test = reg_test_82598;
1410 break;
1411 case ixgbe_mac_82599EB:
1412 case ixgbe_mac_X540:
1413 case ixgbe_mac_X550:
1414 case ixgbe_mac_X550EM_x:
1415 toggle = 0x7FFFF30F;
1416 test = reg_test_82599;
1417 break;
1418 default:
1419 *data = 1;
1420 return 1;
1421 }
1422
1423 /*
1424 * Because the status register is such a special case,
1425 * we handle it separately from the rest of the register
1426 * tests. Some bits are read-only, some toggle, and some
1427 * are writeable on newer MACs.
1428 */
1429 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1430 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1431 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1432 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1433 if (value != after) {
1434 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1435 after, value);
1436 *data = 1;
1437 return 1;
1438 }
1439 /* restore previous status */
1440 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1441
1442 /*
1443 * Perform the remainder of the register test, looping through
1444 * the test table until we either fail or reach the null entry.
1445 */
1446 while (test->reg) {
1447 for (i = 0; i < test->array_len; i++) {
1448 bool b = false;
1449
1450 switch (test->test_type) {
1451 case PATTERN_TEST:
1452 b = reg_pattern_test(adapter, data,
1453 test->reg + (i * 0x40),
1454 test->mask,
1455 test->write);
1456 break;
1457 case SET_READ_TEST:
1458 b = reg_set_and_check(adapter, data,
1459 test->reg + (i * 0x40),
1460 test->mask,
1461 test->write);
1462 break;
1463 case WRITE_NO_TEST:
1464 ixgbe_write_reg(&adapter->hw,
1465 test->reg + (i * 0x40),
1466 test->write);
1467 break;
1468 case TABLE32_TEST:
1469 b = reg_pattern_test(adapter, data,
1470 test->reg + (i * 4),
1471 test->mask,
1472 test->write);
1473 break;
1474 case TABLE64_TEST_LO:
1475 b = reg_pattern_test(adapter, data,
1476 test->reg + (i * 8),
1477 test->mask,
1478 test->write);
1479 break;
1480 case TABLE64_TEST_HI:
1481 b = reg_pattern_test(adapter, data,
1482 (test->reg + 4) + (i * 8),
1483 test->mask,
1484 test->write);
1485 break;
1486 }
1487 if (b)
1488 return 1;
1489 }
1490 test++;
1491 }
1492
1493 *data = 0;
1494 return 0;
1495 }
1496
ixgbe_eeprom_test(struct ixgbe_adapter * adapter,u64 * data)1497 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1498 {
1499 struct ixgbe_hw *hw = &adapter->hw;
1500 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1501 *data = 1;
1502 else
1503 *data = 0;
1504 return *data;
1505 }
1506
ixgbe_test_intr(int irq,void * data)1507 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1508 {
1509 struct net_device *netdev = (struct net_device *) data;
1510 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1511
1512 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1513
1514 return IRQ_HANDLED;
1515 }
1516
ixgbe_intr_test(struct ixgbe_adapter * adapter,u64 * data)1517 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1518 {
1519 struct net_device *netdev = adapter->netdev;
1520 u32 mask, i = 0, shared_int = true;
1521 u32 irq = adapter->pdev->irq;
1522
1523 *data = 0;
1524
1525 /* Hook up test interrupt handler just for this test */
1526 if (adapter->msix_entries) {
1527 /* NOTE: we don't test MSI-X interrupts here, yet */
1528 return 0;
1529 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1530 shared_int = false;
1531 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1532 netdev)) {
1533 *data = 1;
1534 return -1;
1535 }
1536 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1537 netdev->name, netdev)) {
1538 shared_int = false;
1539 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1540 netdev->name, netdev)) {
1541 *data = 1;
1542 return -1;
1543 }
1544 e_info(hw, "testing %s interrupt\n", shared_int ?
1545 "shared" : "unshared");
1546
1547 /* Disable all the interrupts */
1548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1549 IXGBE_WRITE_FLUSH(&adapter->hw);
1550 usleep_range(10000, 20000);
1551
1552 /* Test each interrupt */
1553 for (; i < 10; i++) {
1554 /* Interrupt to test */
1555 mask = 1 << i;
1556
1557 if (!shared_int) {
1558 /*
1559 * Disable the interrupts to be reported in
1560 * the cause register and then force the same
1561 * interrupt and see if one gets posted. If
1562 * an interrupt was posted to the bus, the
1563 * test failed.
1564 */
1565 adapter->test_icr = 0;
1566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1567 ~mask & 0x00007FFF);
1568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1569 ~mask & 0x00007FFF);
1570 IXGBE_WRITE_FLUSH(&adapter->hw);
1571 usleep_range(10000, 20000);
1572
1573 if (adapter->test_icr & mask) {
1574 *data = 3;
1575 break;
1576 }
1577 }
1578
1579 /*
1580 * Enable the interrupt to be reported in the cause
1581 * register and then force the same interrupt and see
1582 * if one gets posted. If an interrupt was not posted
1583 * to the bus, the test failed.
1584 */
1585 adapter->test_icr = 0;
1586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1588 IXGBE_WRITE_FLUSH(&adapter->hw);
1589 usleep_range(10000, 20000);
1590
1591 if (!(adapter->test_icr & mask)) {
1592 *data = 4;
1593 break;
1594 }
1595
1596 if (!shared_int) {
1597 /*
1598 * Disable the other interrupts to be reported in
1599 * the cause register and then force the other
1600 * interrupts and see if any get posted. If
1601 * an interrupt was posted to the bus, the
1602 * test failed.
1603 */
1604 adapter->test_icr = 0;
1605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1606 ~mask & 0x00007FFF);
1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1608 ~mask & 0x00007FFF);
1609 IXGBE_WRITE_FLUSH(&adapter->hw);
1610 usleep_range(10000, 20000);
1611
1612 if (adapter->test_icr) {
1613 *data = 5;
1614 break;
1615 }
1616 }
1617 }
1618
1619 /* Disable all the interrupts */
1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1621 IXGBE_WRITE_FLUSH(&adapter->hw);
1622 usleep_range(10000, 20000);
1623
1624 /* Unhook test interrupt handler */
1625 free_irq(irq, netdev);
1626
1627 return *data;
1628 }
1629
ixgbe_free_desc_rings(struct ixgbe_adapter * adapter)1630 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1631 {
1632 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1633 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1634 struct ixgbe_hw *hw = &adapter->hw;
1635 u32 reg_ctl;
1636
1637 /* shut down the DMA engines now so they can be reinitialized later */
1638
1639 /* first Rx */
1640 hw->mac.ops.disable_rx(hw);
1641 ixgbe_disable_rx_queue(adapter, rx_ring);
1642
1643 /* now Tx */
1644 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1645 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1646 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1647
1648 switch (hw->mac.type) {
1649 case ixgbe_mac_82599EB:
1650 case ixgbe_mac_X540:
1651 case ixgbe_mac_X550:
1652 case ixgbe_mac_X550EM_x:
1653 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1654 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1655 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1656 break;
1657 default:
1658 break;
1659 }
1660
1661 ixgbe_reset(adapter);
1662
1663 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1664 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1665 }
1666
ixgbe_setup_desc_rings(struct ixgbe_adapter * adapter)1667 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1668 {
1669 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1670 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1671 struct ixgbe_hw *hw = &adapter->hw;
1672 u32 rctl, reg_data;
1673 int ret_val;
1674 int err;
1675
1676 /* Setup Tx descriptor ring and Tx buffers */
1677 tx_ring->count = IXGBE_DEFAULT_TXD;
1678 tx_ring->queue_index = 0;
1679 tx_ring->dev = &adapter->pdev->dev;
1680 tx_ring->netdev = adapter->netdev;
1681 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1682
1683 err = ixgbe_setup_tx_resources(tx_ring);
1684 if (err)
1685 return 1;
1686
1687 switch (adapter->hw.mac.type) {
1688 case ixgbe_mac_82599EB:
1689 case ixgbe_mac_X540:
1690 case ixgbe_mac_X550:
1691 case ixgbe_mac_X550EM_x:
1692 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1693 reg_data |= IXGBE_DMATXCTL_TE;
1694 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1695 break;
1696 default:
1697 break;
1698 }
1699
1700 ixgbe_configure_tx_ring(adapter, tx_ring);
1701
1702 /* Setup Rx Descriptor ring and Rx buffers */
1703 rx_ring->count = IXGBE_DEFAULT_RXD;
1704 rx_ring->queue_index = 0;
1705 rx_ring->dev = &adapter->pdev->dev;
1706 rx_ring->netdev = adapter->netdev;
1707 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1708
1709 err = ixgbe_setup_rx_resources(rx_ring);
1710 if (err) {
1711 ret_val = 4;
1712 goto err_nomem;
1713 }
1714
1715 hw->mac.ops.disable_rx(hw);
1716
1717 ixgbe_configure_rx_ring(adapter, rx_ring);
1718
1719 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1720 rctl |= IXGBE_RXCTRL_DMBYPS;
1721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1722
1723 hw->mac.ops.enable_rx(hw);
1724
1725 return 0;
1726
1727 err_nomem:
1728 ixgbe_free_desc_rings(adapter);
1729 return ret_val;
1730 }
1731
ixgbe_setup_loopback_test(struct ixgbe_adapter * adapter)1732 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1733 {
1734 struct ixgbe_hw *hw = &adapter->hw;
1735 u32 reg_data;
1736
1737
1738 /* Setup MAC loopback */
1739 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1740 reg_data |= IXGBE_HLREG0_LPBK;
1741 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1742
1743 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1744 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1745 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1746
1747 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1748 switch (adapter->hw.mac.type) {
1749 case ixgbe_mac_X540:
1750 case ixgbe_mac_X550:
1751 case ixgbe_mac_X550EM_x:
1752 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1753 reg_data |= IXGBE_MACC_FLU;
1754 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1755 break;
1756 default:
1757 if (hw->mac.orig_autoc) {
1758 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1759 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1760 } else {
1761 return 10;
1762 }
1763 }
1764 IXGBE_WRITE_FLUSH(hw);
1765 usleep_range(10000, 20000);
1766
1767 /* Disable Atlas Tx lanes; re-enabled in reset path */
1768 if (hw->mac.type == ixgbe_mac_82598EB) {
1769 u8 atlas;
1770
1771 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1772 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1773 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1774
1775 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1776 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1777 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1778
1779 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1780 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1781 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1782
1783 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1784 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1785 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1786 }
1787
1788 return 0;
1789 }
1790
ixgbe_loopback_cleanup(struct ixgbe_adapter * adapter)1791 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1792 {
1793 u32 reg_data;
1794
1795 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1796 reg_data &= ~IXGBE_HLREG0_LPBK;
1797 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1798 }
1799
ixgbe_create_lbtest_frame(struct sk_buff * skb,unsigned int frame_size)1800 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1801 unsigned int frame_size)
1802 {
1803 memset(skb->data, 0xFF, frame_size);
1804 frame_size >>= 1;
1805 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1806 memset(&skb->data[frame_size + 10], 0xBE, 1);
1807 memset(&skb->data[frame_size + 12], 0xAF, 1);
1808 }
1809
ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer * rx_buffer,unsigned int frame_size)1810 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1811 unsigned int frame_size)
1812 {
1813 unsigned char *data;
1814 bool match = true;
1815
1816 frame_size >>= 1;
1817
1818 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1819
1820 if (data[3] != 0xFF ||
1821 data[frame_size + 10] != 0xBE ||
1822 data[frame_size + 12] != 0xAF)
1823 match = false;
1824
1825 kunmap(rx_buffer->page);
1826
1827 return match;
1828 }
1829
ixgbe_clean_test_rings(struct ixgbe_ring * rx_ring,struct ixgbe_ring * tx_ring,unsigned int size)1830 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1831 struct ixgbe_ring *tx_ring,
1832 unsigned int size)
1833 {
1834 union ixgbe_adv_rx_desc *rx_desc;
1835 struct ixgbe_rx_buffer *rx_buffer;
1836 struct ixgbe_tx_buffer *tx_buffer;
1837 u16 rx_ntc, tx_ntc, count = 0;
1838
1839 /* initialize next to clean and descriptor values */
1840 rx_ntc = rx_ring->next_to_clean;
1841 tx_ntc = tx_ring->next_to_clean;
1842 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1843
1844 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1845 /* check Rx buffer */
1846 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1847
1848 /* sync Rx buffer for CPU read */
1849 dma_sync_single_for_cpu(rx_ring->dev,
1850 rx_buffer->dma,
1851 ixgbe_rx_bufsz(rx_ring),
1852 DMA_FROM_DEVICE);
1853
1854 /* verify contents of skb */
1855 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1856 count++;
1857
1858 /* sync Rx buffer for device write */
1859 dma_sync_single_for_device(rx_ring->dev,
1860 rx_buffer->dma,
1861 ixgbe_rx_bufsz(rx_ring),
1862 DMA_FROM_DEVICE);
1863
1864 /* unmap buffer on Tx side */
1865 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1866 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1867
1868 /* increment Rx/Tx next to clean counters */
1869 rx_ntc++;
1870 if (rx_ntc == rx_ring->count)
1871 rx_ntc = 0;
1872 tx_ntc++;
1873 if (tx_ntc == tx_ring->count)
1874 tx_ntc = 0;
1875
1876 /* fetch next descriptor */
1877 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1878 }
1879
1880 netdev_tx_reset_queue(txring_txq(tx_ring));
1881
1882 /* re-map buffers to ring, store next to clean values */
1883 ixgbe_alloc_rx_buffers(rx_ring, count);
1884 rx_ring->next_to_clean = rx_ntc;
1885 tx_ring->next_to_clean = tx_ntc;
1886
1887 return count;
1888 }
1889
ixgbe_run_loopback_test(struct ixgbe_adapter * adapter)1890 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1891 {
1892 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1893 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1894 int i, j, lc, good_cnt, ret_val = 0;
1895 unsigned int size = 1024;
1896 netdev_tx_t tx_ret_val;
1897 struct sk_buff *skb;
1898 u32 flags_orig = adapter->flags;
1899
1900 /* DCB can modify the frames on Tx */
1901 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1902
1903 /* allocate test skb */
1904 skb = alloc_skb(size, GFP_KERNEL);
1905 if (!skb)
1906 return 11;
1907
1908 /* place data into test skb */
1909 ixgbe_create_lbtest_frame(skb, size);
1910 skb_put(skb, size);
1911
1912 /*
1913 * Calculate the loop count based on the largest descriptor ring
1914 * The idea is to wrap the largest ring a number of times using 64
1915 * send/receive pairs during each loop
1916 */
1917
1918 if (rx_ring->count <= tx_ring->count)
1919 lc = ((tx_ring->count / 64) * 2) + 1;
1920 else
1921 lc = ((rx_ring->count / 64) * 2) + 1;
1922
1923 for (j = 0; j <= lc; j++) {
1924 /* reset count of good packets */
1925 good_cnt = 0;
1926
1927 /* place 64 packets on the transmit queue*/
1928 for (i = 0; i < 64; i++) {
1929 skb_get(skb);
1930 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1931 adapter,
1932 tx_ring);
1933 if (tx_ret_val == NETDEV_TX_OK)
1934 good_cnt++;
1935 }
1936
1937 if (good_cnt != 64) {
1938 ret_val = 12;
1939 break;
1940 }
1941
1942 /* allow 200 milliseconds for packets to go from Tx to Rx */
1943 msleep(200);
1944
1945 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1946 if (good_cnt != 64) {
1947 ret_val = 13;
1948 break;
1949 }
1950 }
1951
1952 /* free the original skb */
1953 kfree_skb(skb);
1954 adapter->flags = flags_orig;
1955
1956 return ret_val;
1957 }
1958
ixgbe_loopback_test(struct ixgbe_adapter * adapter,u64 * data)1959 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1960 {
1961 *data = ixgbe_setup_desc_rings(adapter);
1962 if (*data)
1963 goto out;
1964 *data = ixgbe_setup_loopback_test(adapter);
1965 if (*data)
1966 goto err_loopback;
1967 *data = ixgbe_run_loopback_test(adapter);
1968 ixgbe_loopback_cleanup(adapter);
1969
1970 err_loopback:
1971 ixgbe_free_desc_rings(adapter);
1972 out:
1973 return *data;
1974 }
1975
ixgbe_diag_test(struct net_device * netdev,struct ethtool_test * eth_test,u64 * data)1976 static void ixgbe_diag_test(struct net_device *netdev,
1977 struct ethtool_test *eth_test, u64 *data)
1978 {
1979 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1980 bool if_running = netif_running(netdev);
1981
1982 if (ixgbe_removed(adapter->hw.hw_addr)) {
1983 e_err(hw, "Adapter removed - test blocked\n");
1984 data[0] = 1;
1985 data[1] = 1;
1986 data[2] = 1;
1987 data[3] = 1;
1988 data[4] = 1;
1989 eth_test->flags |= ETH_TEST_FL_FAILED;
1990 return;
1991 }
1992 set_bit(__IXGBE_TESTING, &adapter->state);
1993 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1994 struct ixgbe_hw *hw = &adapter->hw;
1995
1996 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1997 int i;
1998 for (i = 0; i < adapter->num_vfs; i++) {
1999 if (adapter->vfinfo[i].clear_to_send) {
2000 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2001 data[0] = 1;
2002 data[1] = 1;
2003 data[2] = 1;
2004 data[3] = 1;
2005 data[4] = 1;
2006 eth_test->flags |= ETH_TEST_FL_FAILED;
2007 clear_bit(__IXGBE_TESTING,
2008 &adapter->state);
2009 goto skip_ol_tests;
2010 }
2011 }
2012 }
2013
2014 /* Offline tests */
2015 e_info(hw, "offline testing starting\n");
2016
2017 /* Link test performed before hardware reset so autoneg doesn't
2018 * interfere with test result
2019 */
2020 if (ixgbe_link_test(adapter, &data[4]))
2021 eth_test->flags |= ETH_TEST_FL_FAILED;
2022
2023 if (if_running)
2024 /* indicate we're in test mode */
2025 dev_close(netdev);
2026 else
2027 ixgbe_reset(adapter);
2028
2029 e_info(hw, "register testing starting\n");
2030 if (ixgbe_reg_test(adapter, &data[0]))
2031 eth_test->flags |= ETH_TEST_FL_FAILED;
2032
2033 ixgbe_reset(adapter);
2034 e_info(hw, "eeprom testing starting\n");
2035 if (ixgbe_eeprom_test(adapter, &data[1]))
2036 eth_test->flags |= ETH_TEST_FL_FAILED;
2037
2038 ixgbe_reset(adapter);
2039 e_info(hw, "interrupt testing starting\n");
2040 if (ixgbe_intr_test(adapter, &data[2]))
2041 eth_test->flags |= ETH_TEST_FL_FAILED;
2042
2043 /* If SRIOV or VMDq is enabled then skip MAC
2044 * loopback diagnostic. */
2045 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2046 IXGBE_FLAG_VMDQ_ENABLED)) {
2047 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2048 data[3] = 0;
2049 goto skip_loopback;
2050 }
2051
2052 ixgbe_reset(adapter);
2053 e_info(hw, "loopback testing starting\n");
2054 if (ixgbe_loopback_test(adapter, &data[3]))
2055 eth_test->flags |= ETH_TEST_FL_FAILED;
2056
2057 skip_loopback:
2058 ixgbe_reset(adapter);
2059
2060 /* clear testing bit and return adapter to previous state */
2061 clear_bit(__IXGBE_TESTING, &adapter->state);
2062 if (if_running)
2063 dev_open(netdev);
2064 else if (hw->mac.ops.disable_tx_laser)
2065 hw->mac.ops.disable_tx_laser(hw);
2066 } else {
2067 e_info(hw, "online testing starting\n");
2068
2069 /* Online tests */
2070 if (ixgbe_link_test(adapter, &data[4]))
2071 eth_test->flags |= ETH_TEST_FL_FAILED;
2072
2073 /* Offline tests aren't run; pass by default */
2074 data[0] = 0;
2075 data[1] = 0;
2076 data[2] = 0;
2077 data[3] = 0;
2078
2079 clear_bit(__IXGBE_TESTING, &adapter->state);
2080 }
2081
2082 skip_ol_tests:
2083 msleep_interruptible(4 * 1000);
2084 }
2085
ixgbe_wol_exclusion(struct ixgbe_adapter * adapter,struct ethtool_wolinfo * wol)2086 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2087 struct ethtool_wolinfo *wol)
2088 {
2089 struct ixgbe_hw *hw = &adapter->hw;
2090 int retval = 0;
2091
2092 /* WOL not supported for all devices */
2093 if (!ixgbe_wol_supported(adapter, hw->device_id,
2094 hw->subsystem_device_id)) {
2095 retval = 1;
2096 wol->supported = 0;
2097 }
2098
2099 return retval;
2100 }
2101
ixgbe_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2102 static void ixgbe_get_wol(struct net_device *netdev,
2103 struct ethtool_wolinfo *wol)
2104 {
2105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2106
2107 wol->supported = WAKE_UCAST | WAKE_MCAST |
2108 WAKE_BCAST | WAKE_MAGIC;
2109 wol->wolopts = 0;
2110
2111 if (ixgbe_wol_exclusion(adapter, wol) ||
2112 !device_can_wakeup(&adapter->pdev->dev))
2113 return;
2114
2115 if (adapter->wol & IXGBE_WUFC_EX)
2116 wol->wolopts |= WAKE_UCAST;
2117 if (adapter->wol & IXGBE_WUFC_MC)
2118 wol->wolopts |= WAKE_MCAST;
2119 if (adapter->wol & IXGBE_WUFC_BC)
2120 wol->wolopts |= WAKE_BCAST;
2121 if (adapter->wol & IXGBE_WUFC_MAG)
2122 wol->wolopts |= WAKE_MAGIC;
2123 }
2124
ixgbe_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2125 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2126 {
2127 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2128
2129 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2130 return -EOPNOTSUPP;
2131
2132 if (ixgbe_wol_exclusion(adapter, wol))
2133 return wol->wolopts ? -EOPNOTSUPP : 0;
2134
2135 adapter->wol = 0;
2136
2137 if (wol->wolopts & WAKE_UCAST)
2138 adapter->wol |= IXGBE_WUFC_EX;
2139 if (wol->wolopts & WAKE_MCAST)
2140 adapter->wol |= IXGBE_WUFC_MC;
2141 if (wol->wolopts & WAKE_BCAST)
2142 adapter->wol |= IXGBE_WUFC_BC;
2143 if (wol->wolopts & WAKE_MAGIC)
2144 adapter->wol |= IXGBE_WUFC_MAG;
2145
2146 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2147
2148 return 0;
2149 }
2150
ixgbe_nway_reset(struct net_device * netdev)2151 static int ixgbe_nway_reset(struct net_device *netdev)
2152 {
2153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2154
2155 if (netif_running(netdev))
2156 ixgbe_reinit_locked(adapter);
2157
2158 return 0;
2159 }
2160
ixgbe_set_phys_id(struct net_device * netdev,enum ethtool_phys_id_state state)2161 static int ixgbe_set_phys_id(struct net_device *netdev,
2162 enum ethtool_phys_id_state state)
2163 {
2164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2165 struct ixgbe_hw *hw = &adapter->hw;
2166
2167 switch (state) {
2168 case ETHTOOL_ID_ACTIVE:
2169 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2170 return 2;
2171
2172 case ETHTOOL_ID_ON:
2173 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2174 break;
2175
2176 case ETHTOOL_ID_OFF:
2177 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2178 break;
2179
2180 case ETHTOOL_ID_INACTIVE:
2181 /* Restore LED settings */
2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2183 break;
2184 }
2185
2186 return 0;
2187 }
2188
ixgbe_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec)2189 static int ixgbe_get_coalesce(struct net_device *netdev,
2190 struct ethtool_coalesce *ec)
2191 {
2192 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2193
2194 /* only valid if in constant ITR mode */
2195 if (adapter->rx_itr_setting <= 1)
2196 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2197 else
2198 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2199
2200 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2201 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2202 return 0;
2203
2204 /* only valid if in constant ITR mode */
2205 if (adapter->tx_itr_setting <= 1)
2206 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2207 else
2208 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2209
2210 return 0;
2211 }
2212
2213 /*
2214 * this function must be called before setting the new value of
2215 * rx_itr_setting
2216 */
ixgbe_update_rsc(struct ixgbe_adapter * adapter)2217 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2218 {
2219 struct net_device *netdev = adapter->netdev;
2220
2221 /* nothing to do if LRO or RSC are not enabled */
2222 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2223 !(netdev->features & NETIF_F_LRO))
2224 return false;
2225
2226 /* check the feature flag value and enable RSC if necessary */
2227 if (adapter->rx_itr_setting == 1 ||
2228 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2229 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2230 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2231 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2232 return true;
2233 }
2234 /* if interrupt rate is too high then disable RSC */
2235 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2236 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2237 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2238 return true;
2239 }
2240 return false;
2241 }
2242
ixgbe_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec)2243 static int ixgbe_set_coalesce(struct net_device *netdev,
2244 struct ethtool_coalesce *ec)
2245 {
2246 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2247 struct ixgbe_q_vector *q_vector;
2248 int i;
2249 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2250 bool need_reset = false;
2251
2252 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2253 /* reject Tx specific changes in case of mixed RxTx vectors */
2254 if (ec->tx_coalesce_usecs)
2255 return -EINVAL;
2256 tx_itr_prev = adapter->rx_itr_setting;
2257 } else {
2258 tx_itr_prev = adapter->tx_itr_setting;
2259 }
2260
2261 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2262 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2263 return -EINVAL;
2264
2265 if (ec->rx_coalesce_usecs > 1)
2266 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2267 else
2268 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2269
2270 if (adapter->rx_itr_setting == 1)
2271 rx_itr_param = IXGBE_20K_ITR;
2272 else
2273 rx_itr_param = adapter->rx_itr_setting;
2274
2275 if (ec->tx_coalesce_usecs > 1)
2276 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2277 else
2278 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2279
2280 if (adapter->tx_itr_setting == 1)
2281 tx_itr_param = IXGBE_10K_ITR;
2282 else
2283 tx_itr_param = adapter->tx_itr_setting;
2284
2285 /* mixed Rx/Tx */
2286 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2287 adapter->tx_itr_setting = adapter->rx_itr_setting;
2288
2289 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2290 if ((adapter->tx_itr_setting != 1) &&
2291 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2292 if ((tx_itr_prev == 1) ||
2293 (tx_itr_prev >= IXGBE_100K_ITR))
2294 need_reset = true;
2295 } else {
2296 if ((tx_itr_prev != 1) &&
2297 (tx_itr_prev < IXGBE_100K_ITR))
2298 need_reset = true;
2299 }
2300
2301 /* check the old value and enable RSC if necessary */
2302 need_reset |= ixgbe_update_rsc(adapter);
2303
2304 for (i = 0; i < adapter->num_q_vectors; i++) {
2305 q_vector = adapter->q_vector[i];
2306 if (q_vector->tx.count && !q_vector->rx.count)
2307 /* tx only */
2308 q_vector->itr = tx_itr_param;
2309 else
2310 /* rx only or mixed */
2311 q_vector->itr = rx_itr_param;
2312 ixgbe_write_eitr(q_vector);
2313 }
2314
2315 /*
2316 * do reset here at the end to make sure EITR==0 case is handled
2317 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2318 * also locks in RSC enable/disable which requires reset
2319 */
2320 if (need_reset)
2321 ixgbe_do_reset(netdev);
2322
2323 return 0;
2324 }
2325
ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * cmd)2326 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2327 struct ethtool_rxnfc *cmd)
2328 {
2329 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2330 struct ethtool_rx_flow_spec *fsp =
2331 (struct ethtool_rx_flow_spec *)&cmd->fs;
2332 struct hlist_node *node2;
2333 struct ixgbe_fdir_filter *rule = NULL;
2334
2335 /* report total rule count */
2336 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2337
2338 hlist_for_each_entry_safe(rule, node2,
2339 &adapter->fdir_filter_list, fdir_node) {
2340 if (fsp->location <= rule->sw_idx)
2341 break;
2342 }
2343
2344 if (!rule || fsp->location != rule->sw_idx)
2345 return -EINVAL;
2346
2347 /* fill out the flow spec entry */
2348
2349 /* set flow type field */
2350 switch (rule->filter.formatted.flow_type) {
2351 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2352 fsp->flow_type = TCP_V4_FLOW;
2353 break;
2354 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2355 fsp->flow_type = UDP_V4_FLOW;
2356 break;
2357 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2358 fsp->flow_type = SCTP_V4_FLOW;
2359 break;
2360 case IXGBE_ATR_FLOW_TYPE_IPV4:
2361 fsp->flow_type = IP_USER_FLOW;
2362 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2363 fsp->h_u.usr_ip4_spec.proto = 0;
2364 fsp->m_u.usr_ip4_spec.proto = 0;
2365 break;
2366 default:
2367 return -EINVAL;
2368 }
2369
2370 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2371 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2372 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2373 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2374 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2375 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2376 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2377 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2378 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2379 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2380 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2381 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2382 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2383 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2384 fsp->flow_type |= FLOW_EXT;
2385
2386 /* record action */
2387 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2388 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2389 else
2390 fsp->ring_cookie = rule->action;
2391
2392 return 0;
2393 }
2394
ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * cmd,u32 * rule_locs)2395 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2396 struct ethtool_rxnfc *cmd,
2397 u32 *rule_locs)
2398 {
2399 struct hlist_node *node2;
2400 struct ixgbe_fdir_filter *rule;
2401 int cnt = 0;
2402
2403 /* report total rule count */
2404 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2405
2406 hlist_for_each_entry_safe(rule, node2,
2407 &adapter->fdir_filter_list, fdir_node) {
2408 if (cnt == cmd->rule_cnt)
2409 return -EMSGSIZE;
2410 rule_locs[cnt] = rule->sw_idx;
2411 cnt++;
2412 }
2413
2414 cmd->rule_cnt = cnt;
2415
2416 return 0;
2417 }
2418
ixgbe_get_rss_hash_opts(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * cmd)2419 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2420 struct ethtool_rxnfc *cmd)
2421 {
2422 cmd->data = 0;
2423
2424 /* Report default options for RSS on ixgbe */
2425 switch (cmd->flow_type) {
2426 case TCP_V4_FLOW:
2427 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2428 /* fallthrough */
2429 case UDP_V4_FLOW:
2430 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2431 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2432 /* fallthrough */
2433 case SCTP_V4_FLOW:
2434 case AH_ESP_V4_FLOW:
2435 case AH_V4_FLOW:
2436 case ESP_V4_FLOW:
2437 case IPV4_FLOW:
2438 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2439 break;
2440 case TCP_V6_FLOW:
2441 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2442 /* fallthrough */
2443 case UDP_V6_FLOW:
2444 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2445 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2446 /* fallthrough */
2447 case SCTP_V6_FLOW:
2448 case AH_ESP_V6_FLOW:
2449 case AH_V6_FLOW:
2450 case ESP_V6_FLOW:
2451 case IPV6_FLOW:
2452 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2453 break;
2454 default:
2455 return -EINVAL;
2456 }
2457
2458 return 0;
2459 }
2460
ixgbe_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2461 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2462 u32 *rule_locs)
2463 {
2464 struct ixgbe_adapter *adapter = netdev_priv(dev);
2465 int ret = -EOPNOTSUPP;
2466
2467 switch (cmd->cmd) {
2468 case ETHTOOL_GRXRINGS:
2469 cmd->data = adapter->num_rx_queues;
2470 ret = 0;
2471 break;
2472 case ETHTOOL_GRXCLSRLCNT:
2473 cmd->rule_cnt = adapter->fdir_filter_count;
2474 ret = 0;
2475 break;
2476 case ETHTOOL_GRXCLSRULE:
2477 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2478 break;
2479 case ETHTOOL_GRXCLSRLALL:
2480 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2481 break;
2482 case ETHTOOL_GRXFH:
2483 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 return ret;
2490 }
2491
ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter * adapter,struct ixgbe_fdir_filter * input,u16 sw_idx)2492 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2493 struct ixgbe_fdir_filter *input,
2494 u16 sw_idx)
2495 {
2496 struct ixgbe_hw *hw = &adapter->hw;
2497 struct hlist_node *node2;
2498 struct ixgbe_fdir_filter *rule, *parent;
2499 int err = -EINVAL;
2500
2501 parent = NULL;
2502 rule = NULL;
2503
2504 hlist_for_each_entry_safe(rule, node2,
2505 &adapter->fdir_filter_list, fdir_node) {
2506 /* hash found, or no matching entry */
2507 if (rule->sw_idx >= sw_idx)
2508 break;
2509 parent = rule;
2510 }
2511
2512 /* if there is an old rule occupying our place remove it */
2513 if (rule && (rule->sw_idx == sw_idx)) {
2514 if (!input || (rule->filter.formatted.bkt_hash !=
2515 input->filter.formatted.bkt_hash)) {
2516 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2517 &rule->filter,
2518 sw_idx);
2519 }
2520
2521 hlist_del(&rule->fdir_node);
2522 kfree(rule);
2523 adapter->fdir_filter_count--;
2524 }
2525
2526 /*
2527 * If no input this was a delete, err should be 0 if a rule was
2528 * successfully found and removed from the list else -EINVAL
2529 */
2530 if (!input)
2531 return err;
2532
2533 /* initialize node and set software index */
2534 INIT_HLIST_NODE(&input->fdir_node);
2535
2536 /* add filter to the list */
2537 if (parent)
2538 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2539 else
2540 hlist_add_head(&input->fdir_node,
2541 &adapter->fdir_filter_list);
2542
2543 /* update counts */
2544 adapter->fdir_filter_count++;
2545
2546 return 0;
2547 }
2548
ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec * fsp,u8 * flow_type)2549 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2550 u8 *flow_type)
2551 {
2552 switch (fsp->flow_type & ~FLOW_EXT) {
2553 case TCP_V4_FLOW:
2554 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2555 break;
2556 case UDP_V4_FLOW:
2557 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2558 break;
2559 case SCTP_V4_FLOW:
2560 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2561 break;
2562 case IP_USER_FLOW:
2563 switch (fsp->h_u.usr_ip4_spec.proto) {
2564 case IPPROTO_TCP:
2565 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2566 break;
2567 case IPPROTO_UDP:
2568 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2569 break;
2570 case IPPROTO_SCTP:
2571 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2572 break;
2573 case 0:
2574 if (!fsp->m_u.usr_ip4_spec.proto) {
2575 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2576 break;
2577 }
2578 default:
2579 return 0;
2580 }
2581 break;
2582 default:
2583 return 0;
2584 }
2585
2586 return 1;
2587 }
2588
ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * cmd)2589 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2590 struct ethtool_rxnfc *cmd)
2591 {
2592 struct ethtool_rx_flow_spec *fsp =
2593 (struct ethtool_rx_flow_spec *)&cmd->fs;
2594 struct ixgbe_hw *hw = &adapter->hw;
2595 struct ixgbe_fdir_filter *input;
2596 union ixgbe_atr_input mask;
2597 int err;
2598
2599 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2600 return -EOPNOTSUPP;
2601
2602 /*
2603 * Don't allow programming if the action is a queue greater than
2604 * the number of online Rx queues.
2605 */
2606 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2607 (fsp->ring_cookie >= adapter->num_rx_queues))
2608 return -EINVAL;
2609
2610 /* Don't allow indexes to exist outside of available space */
2611 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2612 e_err(drv, "Location out of range\n");
2613 return -EINVAL;
2614 }
2615
2616 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2617 if (!input)
2618 return -ENOMEM;
2619
2620 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2621
2622 /* set SW index */
2623 input->sw_idx = fsp->location;
2624
2625 /* record flow type */
2626 if (!ixgbe_flowspec_to_flow_type(fsp,
2627 &input->filter.formatted.flow_type)) {
2628 e_err(drv, "Unrecognized flow type\n");
2629 goto err_out;
2630 }
2631
2632 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2633 IXGBE_ATR_L4TYPE_MASK;
2634
2635 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2636 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2637
2638 /* Copy input into formatted structures */
2639 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2640 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2641 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2642 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2643 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2644 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2645 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2646 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2647
2648 if (fsp->flow_type & FLOW_EXT) {
2649 input->filter.formatted.vm_pool =
2650 (unsigned char)ntohl(fsp->h_ext.data[1]);
2651 mask.formatted.vm_pool =
2652 (unsigned char)ntohl(fsp->m_ext.data[1]);
2653 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2654 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2655 input->filter.formatted.flex_bytes =
2656 fsp->h_ext.vlan_etype;
2657 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2658 }
2659
2660 /* determine if we need to drop or route the packet */
2661 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2662 input->action = IXGBE_FDIR_DROP_QUEUE;
2663 else
2664 input->action = fsp->ring_cookie;
2665
2666 spin_lock(&adapter->fdir_perfect_lock);
2667
2668 if (hlist_empty(&adapter->fdir_filter_list)) {
2669 /* save mask and program input mask into HW */
2670 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2671 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2672 if (err) {
2673 e_err(drv, "Error writing mask\n");
2674 goto err_out_w_lock;
2675 }
2676 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2677 e_err(drv, "Only one mask supported per port\n");
2678 goto err_out_w_lock;
2679 }
2680
2681 /* apply mask and compute/store hash */
2682 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2683
2684 /* program filters to filter memory */
2685 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2686 &input->filter, input->sw_idx,
2687 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2688 IXGBE_FDIR_DROP_QUEUE :
2689 adapter->rx_ring[input->action]->reg_idx);
2690 if (err)
2691 goto err_out_w_lock;
2692
2693 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2694
2695 spin_unlock(&adapter->fdir_perfect_lock);
2696
2697 return err;
2698 err_out_w_lock:
2699 spin_unlock(&adapter->fdir_perfect_lock);
2700 err_out:
2701 kfree(input);
2702 return -EINVAL;
2703 }
2704
ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * cmd)2705 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2706 struct ethtool_rxnfc *cmd)
2707 {
2708 struct ethtool_rx_flow_spec *fsp =
2709 (struct ethtool_rx_flow_spec *)&cmd->fs;
2710 int err;
2711
2712 spin_lock(&adapter->fdir_perfect_lock);
2713 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2714 spin_unlock(&adapter->fdir_perfect_lock);
2715
2716 return err;
2717 }
2718
2719 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2720 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
ixgbe_set_rss_hash_opt(struct ixgbe_adapter * adapter,struct ethtool_rxnfc * nfc)2721 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2722 struct ethtool_rxnfc *nfc)
2723 {
2724 u32 flags2 = adapter->flags2;
2725
2726 /*
2727 * RSS does not support anything other than hashing
2728 * to queues on src and dst IPs and ports
2729 */
2730 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2731 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2732 return -EINVAL;
2733
2734 switch (nfc->flow_type) {
2735 case TCP_V4_FLOW:
2736 case TCP_V6_FLOW:
2737 if (!(nfc->data & RXH_IP_SRC) ||
2738 !(nfc->data & RXH_IP_DST) ||
2739 !(nfc->data & RXH_L4_B_0_1) ||
2740 !(nfc->data & RXH_L4_B_2_3))
2741 return -EINVAL;
2742 break;
2743 case UDP_V4_FLOW:
2744 if (!(nfc->data & RXH_IP_SRC) ||
2745 !(nfc->data & RXH_IP_DST))
2746 return -EINVAL;
2747 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2748 case 0:
2749 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2750 break;
2751 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2752 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2753 break;
2754 default:
2755 return -EINVAL;
2756 }
2757 break;
2758 case UDP_V6_FLOW:
2759 if (!(nfc->data & RXH_IP_SRC) ||
2760 !(nfc->data & RXH_IP_DST))
2761 return -EINVAL;
2762 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2763 case 0:
2764 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2765 break;
2766 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2767 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2768 break;
2769 default:
2770 return -EINVAL;
2771 }
2772 break;
2773 case AH_ESP_V4_FLOW:
2774 case AH_V4_FLOW:
2775 case ESP_V4_FLOW:
2776 case SCTP_V4_FLOW:
2777 case AH_ESP_V6_FLOW:
2778 case AH_V6_FLOW:
2779 case ESP_V6_FLOW:
2780 case SCTP_V6_FLOW:
2781 if (!(nfc->data & RXH_IP_SRC) ||
2782 !(nfc->data & RXH_IP_DST) ||
2783 (nfc->data & RXH_L4_B_0_1) ||
2784 (nfc->data & RXH_L4_B_2_3))
2785 return -EINVAL;
2786 break;
2787 default:
2788 return -EINVAL;
2789 }
2790
2791 /* if we changed something we need to update flags */
2792 if (flags2 != adapter->flags2) {
2793 struct ixgbe_hw *hw = &adapter->hw;
2794 u32 mrqc;
2795 unsigned int pf_pool = adapter->num_vfs;
2796
2797 if ((hw->mac.type >= ixgbe_mac_X550) &&
2798 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2799 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2800 else
2801 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2802
2803 if ((flags2 & UDP_RSS_FLAGS) &&
2804 !(adapter->flags2 & UDP_RSS_FLAGS))
2805 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2806
2807 adapter->flags2 = flags2;
2808
2809 /* Perform hash on these packet types */
2810 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2811 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2812 | IXGBE_MRQC_RSS_FIELD_IPV6
2813 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2814
2815 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2816 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2817
2818 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2819 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2820
2821 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2822 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2823
2824 if ((hw->mac.type >= ixgbe_mac_X550) &&
2825 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2826 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
2827 else
2828 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2829 }
2830
2831 return 0;
2832 }
2833
ixgbe_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2834 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2835 {
2836 struct ixgbe_adapter *adapter = netdev_priv(dev);
2837 int ret = -EOPNOTSUPP;
2838
2839 switch (cmd->cmd) {
2840 case ETHTOOL_SRXCLSRLINS:
2841 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2842 break;
2843 case ETHTOOL_SRXCLSRLDEL:
2844 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2845 break;
2846 case ETHTOOL_SRXFH:
2847 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2848 break;
2849 default:
2850 break;
2851 }
2852
2853 return ret;
2854 }
2855
ixgbe_get_rxfh_key_size(struct net_device * netdev)2856 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
2857 {
2858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2859
2860 return sizeof(adapter->rss_key);
2861 }
2862
ixgbe_rss_indir_size(struct net_device * netdev)2863 static u32 ixgbe_rss_indir_size(struct net_device *netdev)
2864 {
2865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2866
2867 return ixgbe_rss_indir_tbl_entries(adapter);
2868 }
2869
ixgbe_get_reta(struct ixgbe_adapter * adapter,u32 * indir)2870 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
2871 {
2872 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
2873
2874 for (i = 0; i < reta_size; i++)
2875 indir[i] = adapter->rss_indir_tbl[i];
2876 }
2877
ixgbe_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)2878 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2879 u8 *hfunc)
2880 {
2881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2882
2883 if (hfunc)
2884 *hfunc = ETH_RSS_HASH_TOP;
2885
2886 if (indir)
2887 ixgbe_get_reta(adapter, indir);
2888
2889 if (key)
2890 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
2891
2892 return 0;
2893 }
2894
ixgbe_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)2895 static int ixgbe_get_ts_info(struct net_device *dev,
2896 struct ethtool_ts_info *info)
2897 {
2898 struct ixgbe_adapter *adapter = netdev_priv(dev);
2899
2900 switch (adapter->hw.mac.type) {
2901 case ixgbe_mac_X550:
2902 case ixgbe_mac_X550EM_x:
2903 case ixgbe_mac_X540:
2904 case ixgbe_mac_82599EB:
2905 info->so_timestamping =
2906 SOF_TIMESTAMPING_TX_SOFTWARE |
2907 SOF_TIMESTAMPING_RX_SOFTWARE |
2908 SOF_TIMESTAMPING_SOFTWARE |
2909 SOF_TIMESTAMPING_TX_HARDWARE |
2910 SOF_TIMESTAMPING_RX_HARDWARE |
2911 SOF_TIMESTAMPING_RAW_HARDWARE;
2912
2913 if (adapter->ptp_clock)
2914 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2915 else
2916 info->phc_index = -1;
2917
2918 info->tx_types =
2919 (1 << HWTSTAMP_TX_OFF) |
2920 (1 << HWTSTAMP_TX_ON);
2921
2922 info->rx_filters =
2923 (1 << HWTSTAMP_FILTER_NONE) |
2924 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2925 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2926 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2927 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2928 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2929 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2930 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2931 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2932 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2933 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2934 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2935 break;
2936 default:
2937 return ethtool_op_get_ts_info(dev, info);
2938 }
2939 return 0;
2940 }
2941
ixgbe_max_channels(struct ixgbe_adapter * adapter)2942 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2943 {
2944 unsigned int max_combined;
2945 u8 tcs = netdev_get_num_tc(adapter->netdev);
2946
2947 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2948 /* We only support one q_vector without MSI-X */
2949 max_combined = 1;
2950 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2951 /* SR-IOV currently only allows one queue on the PF */
2952 max_combined = 1;
2953 } else if (tcs > 1) {
2954 /* For DCB report channels per traffic class */
2955 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2956 /* 8 TC w/ 4 queues per TC */
2957 max_combined = 4;
2958 } else if (tcs > 4) {
2959 /* 8 TC w/ 8 queues per TC */
2960 max_combined = 8;
2961 } else {
2962 /* 4 TC w/ 16 queues per TC */
2963 max_combined = 16;
2964 }
2965 } else if (adapter->atr_sample_rate) {
2966 /* support up to 64 queues with ATR */
2967 max_combined = IXGBE_MAX_FDIR_INDICES;
2968 } else {
2969 /* support up to 16 queues with RSS */
2970 max_combined = ixgbe_max_rss_indices(adapter);
2971 }
2972
2973 return max_combined;
2974 }
2975
ixgbe_get_channels(struct net_device * dev,struct ethtool_channels * ch)2976 static void ixgbe_get_channels(struct net_device *dev,
2977 struct ethtool_channels *ch)
2978 {
2979 struct ixgbe_adapter *adapter = netdev_priv(dev);
2980
2981 /* report maximum channels */
2982 ch->max_combined = ixgbe_max_channels(adapter);
2983
2984 /* report info for other vector */
2985 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2986 ch->max_other = NON_Q_VECTORS;
2987 ch->other_count = NON_Q_VECTORS;
2988 }
2989
2990 /* record RSS queues */
2991 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2992
2993 /* nothing else to report if RSS is disabled */
2994 if (ch->combined_count == 1)
2995 return;
2996
2997 /* we do not support ATR queueing if SR-IOV is enabled */
2998 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2999 return;
3000
3001 /* same thing goes for being DCB enabled */
3002 if (netdev_get_num_tc(dev) > 1)
3003 return;
3004
3005 /* if ATR is disabled we can exit */
3006 if (!adapter->atr_sample_rate)
3007 return;
3008
3009 /* report flow director queues as maximum channels */
3010 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3011 }
3012
ixgbe_set_channels(struct net_device * dev,struct ethtool_channels * ch)3013 static int ixgbe_set_channels(struct net_device *dev,
3014 struct ethtool_channels *ch)
3015 {
3016 struct ixgbe_adapter *adapter = netdev_priv(dev);
3017 unsigned int count = ch->combined_count;
3018 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3019
3020 /* verify they are not requesting separate vectors */
3021 if (!count || ch->rx_count || ch->tx_count)
3022 return -EINVAL;
3023
3024 /* verify other_count has not changed */
3025 if (ch->other_count != NON_Q_VECTORS)
3026 return -EINVAL;
3027
3028 /* verify the number of channels does not exceed hardware limits */
3029 if (count > ixgbe_max_channels(adapter))
3030 return -EINVAL;
3031
3032 /* update feature limits from largest to smallest supported values */
3033 adapter->ring_feature[RING_F_FDIR].limit = count;
3034
3035 /* cap RSS limit */
3036 if (count > max_rss_indices)
3037 count = max_rss_indices;
3038 adapter->ring_feature[RING_F_RSS].limit = count;
3039
3040 #ifdef IXGBE_FCOE
3041 /* cap FCoE limit at 8 */
3042 if (count > IXGBE_FCRETA_SIZE)
3043 count = IXGBE_FCRETA_SIZE;
3044 adapter->ring_feature[RING_F_FCOE].limit = count;
3045
3046 #endif
3047 /* use setup TC to update any traffic class queue mapping */
3048 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
3049 }
3050
ixgbe_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)3051 static int ixgbe_get_module_info(struct net_device *dev,
3052 struct ethtool_modinfo *modinfo)
3053 {
3054 struct ixgbe_adapter *adapter = netdev_priv(dev);
3055 struct ixgbe_hw *hw = &adapter->hw;
3056 u32 status;
3057 u8 sff8472_rev, addr_mode;
3058 bool page_swap = false;
3059
3060 /* Check whether we support SFF-8472 or not */
3061 status = hw->phy.ops.read_i2c_eeprom(hw,
3062 IXGBE_SFF_SFF_8472_COMP,
3063 &sff8472_rev);
3064 if (status != 0)
3065 return -EIO;
3066
3067 /* addressing mode is not supported */
3068 status = hw->phy.ops.read_i2c_eeprom(hw,
3069 IXGBE_SFF_SFF_8472_SWAP,
3070 &addr_mode);
3071 if (status != 0)
3072 return -EIO;
3073
3074 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3075 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3076 page_swap = true;
3077 }
3078
3079 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3080 /* We have a SFP, but it does not support SFF-8472 */
3081 modinfo->type = ETH_MODULE_SFF_8079;
3082 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3083 } else {
3084 /* We have a SFP which supports a revision of SFF-8472. */
3085 modinfo->type = ETH_MODULE_SFF_8472;
3086 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3087 }
3088
3089 return 0;
3090 }
3091
ixgbe_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * ee,u8 * data)3092 static int ixgbe_get_module_eeprom(struct net_device *dev,
3093 struct ethtool_eeprom *ee,
3094 u8 *data)
3095 {
3096 struct ixgbe_adapter *adapter = netdev_priv(dev);
3097 struct ixgbe_hw *hw = &adapter->hw;
3098 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3099 u8 databyte = 0xFF;
3100 int i = 0;
3101
3102 if (ee->len == 0)
3103 return -EINVAL;
3104
3105 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3106 /* I2C reads can take long time */
3107 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3108 return -EBUSY;
3109
3110 if (i < ETH_MODULE_SFF_8079_LEN)
3111 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3112 else
3113 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3114
3115 if (status != 0)
3116 return -EIO;
3117
3118 data[i - ee->offset] = databyte;
3119 }
3120
3121 return 0;
3122 }
3123
3124 static const struct ethtool_ops ixgbe_ethtool_ops = {
3125 .get_settings = ixgbe_get_settings,
3126 .set_settings = ixgbe_set_settings,
3127 .get_drvinfo = ixgbe_get_drvinfo,
3128 .get_regs_len = ixgbe_get_regs_len,
3129 .get_regs = ixgbe_get_regs,
3130 .get_wol = ixgbe_get_wol,
3131 .set_wol = ixgbe_set_wol,
3132 .nway_reset = ixgbe_nway_reset,
3133 .get_link = ethtool_op_get_link,
3134 .get_eeprom_len = ixgbe_get_eeprom_len,
3135 .get_eeprom = ixgbe_get_eeprom,
3136 .set_eeprom = ixgbe_set_eeprom,
3137 .get_ringparam = ixgbe_get_ringparam,
3138 .set_ringparam = ixgbe_set_ringparam,
3139 .get_pauseparam = ixgbe_get_pauseparam,
3140 .set_pauseparam = ixgbe_set_pauseparam,
3141 .get_msglevel = ixgbe_get_msglevel,
3142 .set_msglevel = ixgbe_set_msglevel,
3143 .self_test = ixgbe_diag_test,
3144 .get_strings = ixgbe_get_strings,
3145 .set_phys_id = ixgbe_set_phys_id,
3146 .get_sset_count = ixgbe_get_sset_count,
3147 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3148 .get_coalesce = ixgbe_get_coalesce,
3149 .set_coalesce = ixgbe_set_coalesce,
3150 .get_rxnfc = ixgbe_get_rxnfc,
3151 .set_rxnfc = ixgbe_set_rxnfc,
3152 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3153 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3154 .get_rxfh = ixgbe_get_rxfh,
3155 .get_channels = ixgbe_get_channels,
3156 .set_channels = ixgbe_set_channels,
3157 .get_ts_info = ixgbe_get_ts_info,
3158 .get_module_info = ixgbe_get_module_info,
3159 .get_module_eeprom = ixgbe_get_module_eeprom,
3160 };
3161
ixgbe_set_ethtool_ops(struct net_device * netdev)3162 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3163 {
3164 netdev->ethtool_ops = &ixgbe_ethtool_ops;
3165 }
3166