1 /*
2 * isp.h
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #ifndef OMAP3_ISP_CORE_H
18 #define OMAP3_ISP_CORE_H
19
20 #include <media/omap3isp.h>
21 #include <media/v4l2-async.h>
22 #include <media/v4l2-device.h>
23 #include <linux/clk-provider.h>
24 #include <linux/device.h>
25 #include <linux/io.h>
26 #include <linux/iommu.h>
27 #include <linux/platform_device.h>
28 #include <linux/wait.h>
29
30 #include "ispstat.h"
31 #include "ispccdc.h"
32 #include "ispreg.h"
33 #include "ispresizer.h"
34 #include "isppreview.h"
35 #include "ispcsiphy.h"
36 #include "ispcsi2.h"
37 #include "ispccp2.h"
38
39 #define ISP_TOK_TERM 0xFFFFFFFF /*
40 * terminating token for ISP
41 * modules reg list
42 */
43 #define to_isp_device(ptr_module) \
44 container_of(ptr_module, struct isp_device, isp_##ptr_module)
45 #define to_device(ptr_module) \
46 (to_isp_device(ptr_module)->dev)
47
48 enum isp_mem_resources {
49 OMAP3_ISP_IOMEM_MAIN,
50 OMAP3_ISP_IOMEM_CCP2,
51 OMAP3_ISP_IOMEM_CCDC,
52 OMAP3_ISP_IOMEM_HIST,
53 OMAP3_ISP_IOMEM_H3A,
54 OMAP3_ISP_IOMEM_PREV,
55 OMAP3_ISP_IOMEM_RESZ,
56 OMAP3_ISP_IOMEM_SBL,
57 OMAP3_ISP_IOMEM_CSI2A_REGS1,
58 OMAP3_ISP_IOMEM_CSIPHY2,
59 OMAP3_ISP_IOMEM_CSI2A_REGS2,
60 OMAP3_ISP_IOMEM_CSI2C_REGS1,
61 OMAP3_ISP_IOMEM_CSIPHY1,
62 OMAP3_ISP_IOMEM_CSI2C_REGS2,
63 OMAP3_ISP_IOMEM_LAST
64 };
65
66 enum isp_sbl_resource {
67 OMAP3_ISP_SBL_CSI1_READ = 0x1,
68 OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
69 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
70 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
71 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
72 OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
73 OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
74 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
75 OMAP3_ISP_SBL_RESIZER_READ = 0x100,
76 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
77 };
78
79 enum isp_subclk_resource {
80 OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
81 OMAP3_ISP_SUBCLK_AEWB = (1 << 1),
82 OMAP3_ISP_SUBCLK_AF = (1 << 2),
83 OMAP3_ISP_SUBCLK_HIST = (1 << 3),
84 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4),
85 OMAP3_ISP_SUBCLK_RESIZER = (1 << 5),
86 };
87
88 /* ISP: OMAP 34xx ES 1.0 */
89 #define ISP_REVISION_1_0 0x10
90 /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
91 #define ISP_REVISION_2_0 0x20
92 /* ISP2P: OMAP 36xx */
93 #define ISP_REVISION_15_0 0xF0
94
95 #define ISP_PHY_TYPE_3430 0
96 #define ISP_PHY_TYPE_3630 1
97
98 struct regmap;
99
100 /*
101 * struct isp_res_mapping - Map ISP io resources to ISP revision.
102 * @isp_rev: ISP_REVISION_x_x
103 * @offset: register offsets of various ISP sub-blocks
104 * @syscon_offset: offset of the syscon register for 343x / 3630
105 * (CONTROL_CSIRXFE / CONTROL_CAMERA_PHY_CTRL, respectively)
106 * from the syscon base address
107 * @phy_type: ISP_PHY_TYPE_{3430,3630}
108 */
109 struct isp_res_mapping {
110 u32 isp_rev;
111 u32 offset[OMAP3_ISP_IOMEM_LAST];
112 u32 syscon_offset;
113 u32 phy_type;
114 };
115
116 /*
117 * struct isp_reg - Structure for ISP register values.
118 * @reg: 32-bit Register address.
119 * @val: 32-bit Register value.
120 */
121 struct isp_reg {
122 enum isp_mem_resources mmio_range;
123 u32 reg;
124 u32 val;
125 };
126
127 enum isp_xclk_id {
128 ISP_XCLK_A,
129 ISP_XCLK_B,
130 };
131
132 struct isp_xclk {
133 struct isp_device *isp;
134 struct clk_hw hw;
135 struct clk *clk;
136 enum isp_xclk_id id;
137
138 spinlock_t lock; /* Protects enabled and divider */
139 bool enabled;
140 unsigned int divider;
141 };
142
143 /*
144 * struct isp_device - ISP device structure.
145 * @dev: Device pointer specific to the OMAP3 ISP.
146 * @revision: Stores current ISP module revision.
147 * @irq_num: Currently used IRQ number.
148 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
149 * regions.
150 * @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register
151 * region.
152 * @syscon: Regmap for the syscon register space
153 * @syscon_offset: Offset of the CSIPHY control register in syscon
154 * @phy_type: ISP_PHY_TYPE_{3430,3630}
155 * @mapping: IOMMU mapping
156 * @stat_lock: Spinlock for handling statistics
157 * @isp_mutex: Mutex for serializing requests to ISP.
158 * @stop_failure: Indicates that an entity failed to stop.
159 * @crashed: Bitmask of crashed entities (indexed by entity ID)
160 * @has_context: Context has been saved at least once and can be restored.
161 * @ref_count: Reference count for handling multiple ISP requests.
162 * @cam_ick: Pointer to camera interface clock structure.
163 * @cam_mclk: Pointer to camera functional clock structure.
164 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
165 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
166 * @xclks: External clocks provided by the ISP
167 * @irq: Currently attached ISP ISR callbacks information structure.
168 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
169 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
170 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
171 * White Balance SCM.
172 * @isp_res: Pointer to current settings for ISP Resizer.
173 * @isp_prev: Pointer to current settings for ISP Preview.
174 * @isp_ccdc: Pointer to current settings for ISP CCDC.
175 * @platform_cb: ISP driver callback function pointers for platform code
176 *
177 * This structure is used to store the OMAP ISP Information.
178 */
179 struct isp_device {
180 struct v4l2_device v4l2_dev;
181 struct v4l2_async_notifier notifier;
182 struct media_device media_dev;
183 struct device *dev;
184 u32 revision;
185
186 /* platform HW resources */
187 struct isp_platform_data *pdata;
188 unsigned int irq_num;
189
190 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
191 unsigned long mmio_hist_base_phys;
192 struct regmap *syscon;
193 u32 syscon_offset;
194 u32 phy_type;
195
196 struct dma_iommu_mapping *mapping;
197
198 /* ISP Obj */
199 spinlock_t stat_lock; /* common lock for statistic drivers */
200 struct mutex isp_mutex; /* For handling ref_count field */
201 bool stop_failure;
202 u32 crashed;
203 int has_context;
204 int ref_count;
205 unsigned int autoidle;
206 #define ISP_CLK_CAM_ICK 0
207 #define ISP_CLK_CAM_MCLK 1
208 #define ISP_CLK_CSI2_FCK 2
209 #define ISP_CLK_L3_ICK 3
210 struct clk *clock[4];
211 struct isp_xclk xclks[2];
212
213 /* ISP modules */
214 struct ispstat isp_af;
215 struct ispstat isp_aewb;
216 struct ispstat isp_hist;
217 struct isp_res_device isp_res;
218 struct isp_prev_device isp_prev;
219 struct isp_ccdc_device isp_ccdc;
220 struct isp_csi2_device isp_csi2a;
221 struct isp_csi2_device isp_csi2c;
222 struct isp_ccp2_device isp_ccp2;
223 struct isp_csiphy isp_csiphy1;
224 struct isp_csiphy isp_csiphy2;
225
226 unsigned int sbl_resources;
227 unsigned int subclk_resources;
228
229 #define ISP_MAX_SUBDEVS 8
230 struct v4l2_subdev *subdevs[ISP_MAX_SUBDEVS];
231 };
232
233 struct isp_async_subdev {
234 struct v4l2_subdev *sd;
235 struct isp_bus_cfg bus;
236 struct v4l2_async_subdev asd;
237 };
238
239 #define v4l2_dev_to_isp_device(dev) \
240 container_of(dev, struct isp_device, v4l2_dev)
241
242 void omap3isp_hist_dma_done(struct isp_device *isp);
243
244 void omap3isp_flush(struct isp_device *isp);
245
246 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
247 atomic_t *stopping);
248
249 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
250 atomic_t *stopping);
251
252 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
253 enum isp_pipeline_stream_state state);
254 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
255 void omap3isp_configure_bridge(struct isp_device *isp,
256 enum ccdc_input_entity input,
257 const struct isp_parallel_cfg *buscfg,
258 unsigned int shift, unsigned int bridge);
259
260 struct isp_device *omap3isp_get(struct isp_device *isp);
261 void omap3isp_put(struct isp_device *isp);
262
263 void omap3isp_print_status(struct isp_device *isp);
264
265 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
266 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
267
268 void omap3isp_subclk_enable(struct isp_device *isp,
269 enum isp_subclk_resource res);
270 void omap3isp_subclk_disable(struct isp_device *isp,
271 enum isp_subclk_resource res);
272
273 int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
274
275 int omap3isp_register_entities(struct platform_device *pdev,
276 struct v4l2_device *v4l2_dev);
277 void omap3isp_unregister_entities(struct platform_device *pdev);
278
279 /*
280 * isp_reg_readl - Read value of an OMAP3 ISP register
281 * @isp: Device pointer specific to the OMAP3 ISP.
282 * @isp_mmio_range: Range to which the register offset refers to.
283 * @reg_offset: Register offset to read from.
284 *
285 * Returns an unsigned 32 bit value with the required register contents.
286 */
287 static inline
isp_reg_readl(struct isp_device * isp,enum isp_mem_resources isp_mmio_range,u32 reg_offset)288 u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
289 u32 reg_offset)
290 {
291 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
292 }
293
294 /*
295 * isp_reg_writel - Write value to an OMAP3 ISP register
296 * @isp: Device pointer specific to the OMAP3 ISP.
297 * @reg_value: 32 bit value to write to the register.
298 * @isp_mmio_range: Range to which the register offset refers to.
299 * @reg_offset: Register offset to write into.
300 */
301 static inline
isp_reg_writel(struct isp_device * isp,u32 reg_value,enum isp_mem_resources isp_mmio_range,u32 reg_offset)302 void isp_reg_writel(struct isp_device *isp, u32 reg_value,
303 enum isp_mem_resources isp_mmio_range, u32 reg_offset)
304 {
305 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
306 }
307
308 /*
309 * isp_reg_clr - Clear individual bits in an OMAP3 ISP register
310 * @isp: Device pointer specific to the OMAP3 ISP.
311 * @mmio_range: Range to which the register offset refers to.
312 * @reg: Register offset to work on.
313 * @clr_bits: 32 bit value which would be cleared in the register.
314 */
315 static inline
isp_reg_clr(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 clr_bits)316 void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
317 u32 reg, u32 clr_bits)
318 {
319 u32 v = isp_reg_readl(isp, mmio_range, reg);
320
321 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
322 }
323
324 /*
325 * isp_reg_set - Set individual bits in an OMAP3 ISP register
326 * @isp: Device pointer specific to the OMAP3 ISP.
327 * @mmio_range: Range to which the register offset refers to.
328 * @reg: Register offset to work on.
329 * @set_bits: 32 bit value which would be set in the register.
330 */
331 static inline
isp_reg_set(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 set_bits)332 void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
333 u32 reg, u32 set_bits)
334 {
335 u32 v = isp_reg_readl(isp, mmio_range, reg);
336
337 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
338 }
339
340 /*
341 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
342 * @isp: Device pointer specific to the OMAP3 ISP.
343 * @mmio_range: Range to which the register offset refers to.
344 * @reg: Register offset to work on.
345 * @clr_bits: 32 bit value which would be cleared in the register.
346 * @set_bits: 32 bit value which would be set in the register.
347 *
348 * The clear operation is done first, and then the set operation.
349 */
350 static inline
isp_reg_clr_set(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 clr_bits,u32 set_bits)351 void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
352 u32 reg, u32 clr_bits, u32 set_bits)
353 {
354 u32 v = isp_reg_readl(isp, mmio_range, reg);
355
356 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
357 }
358
359 static inline enum v4l2_buf_type
isp_pad_buffer_type(const struct v4l2_subdev * subdev,int pad)360 isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
361 {
362 if (pad >= subdev->entity.num_pads)
363 return 0;
364
365 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
366 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
367 else
368 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
369 }
370
371 #endif /* OMAP3_ISP_CORE_H */
372