1 #ifndef _LINUX_IRQ_H
2 #define _LINUX_IRQ_H
3
4 /*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
24 #include <linux/io.h>
25
26 #include <asm/irq.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
29
30 struct seq_file;
31 struct module;
32 struct msi_msg;
33 enum irqchip_irq_state;
34
35 /*
36 * IRQ line status.
37 *
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
39 *
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
53 *
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
55 *
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
64 * request_irq()
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
67 * request/setup_irq()
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 */
76 enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
86
87 IRQ_TYPE_PROBE = 0x00000010,
88
89 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
97 IRQ_NOTHREAD = (1 << 16),
98 IRQ_PER_CPU_DEVID = (1 << 17),
99 IRQ_IS_POLLED = (1 << 18),
100 };
101
102 #define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 IRQ_IS_POLLED)
107
108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
109
110 /*
111 * Return value for chip->irq_set_affinity()
112 *
113 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
118 */
119 enum {
120 IRQ_SET_MASK_OK = 0,
121 IRQ_SET_MASK_OK_NOCOPY,
122 IRQ_SET_MASK_OK_DONE,
123 };
124
125 struct msi_desc;
126 struct irq_domain;
127
128 /**
129 * struct irq_data - per irq and irq chip data passed down to chip functions
130 * @mask: precomputed bitmask for accessing the chip registers
131 * @irq: interrupt number
132 * @hwirq: hardware interrupt number, local to the interrupt domain
133 * @node: node index useful for balancing
134 * @state_use_accessors: status information for irq chip functions.
135 * Use accessor functions to deal with it
136 * @chip: low level interrupt hardware access
137 * @domain: Interrupt translation domain; responsible for mapping
138 * between hwirq number and linux irq number.
139 * @parent_data: pointer to parent struct irq_data to support hierarchy
140 * irq_domain
141 * @handler_data: per-IRQ data for the irq_chip methods
142 * @chip_data: platform-specific per-chip private data for the chip
143 * methods, to allow shared chip implementations
144 * @msi_desc: MSI descriptor
145 * @affinity: IRQ affinity on SMP
146 *
147 * The fields here need to overlay the ones in irq_desc until we
148 * cleaned up the direct references and switched everything over to
149 * irq_data.
150 */
151 struct irq_data {
152 u32 mask;
153 unsigned int irq;
154 unsigned long hwirq;
155 unsigned int node;
156 unsigned int state_use_accessors;
157 struct irq_chip *chip;
158 struct irq_domain *domain;
159 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
160 struct irq_data *parent_data;
161 #endif
162 void *handler_data;
163 void *chip_data;
164 struct msi_desc *msi_desc;
165 cpumask_var_t affinity;
166 };
167
168 /*
169 * Bit masks for irq_data.state
170 *
171 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
172 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
173 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
174 * IRQD_PER_CPU - Interrupt is per cpu
175 * IRQD_AFFINITY_SET - Interrupt affinity was set
176 * IRQD_LEVEL - Interrupt is level triggered
177 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
178 * from suspend
179 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
180 * context
181 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
182 * IRQD_IRQ_MASKED - Masked state of the interrupt
183 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
184 * IRQD_WAKEUP_ARMED - Wakeup mode armed
185 */
186 enum {
187 IRQD_TRIGGER_MASK = 0xf,
188 IRQD_SETAFFINITY_PENDING = (1 << 8),
189 IRQD_NO_BALANCING = (1 << 10),
190 IRQD_PER_CPU = (1 << 11),
191 IRQD_AFFINITY_SET = (1 << 12),
192 IRQD_LEVEL = (1 << 13),
193 IRQD_WAKEUP_STATE = (1 << 14),
194 IRQD_MOVE_PCNTXT = (1 << 15),
195 IRQD_IRQ_DISABLED = (1 << 16),
196 IRQD_IRQ_MASKED = (1 << 17),
197 IRQD_IRQ_INPROGRESS = (1 << 18),
198 IRQD_WAKEUP_ARMED = (1 << 19),
199 };
200
irqd_is_setaffinity_pending(struct irq_data * d)201 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
202 {
203 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
204 }
205
irqd_is_per_cpu(struct irq_data * d)206 static inline bool irqd_is_per_cpu(struct irq_data *d)
207 {
208 return d->state_use_accessors & IRQD_PER_CPU;
209 }
210
irqd_can_balance(struct irq_data * d)211 static inline bool irqd_can_balance(struct irq_data *d)
212 {
213 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
214 }
215
irqd_affinity_was_set(struct irq_data * d)216 static inline bool irqd_affinity_was_set(struct irq_data *d)
217 {
218 return d->state_use_accessors & IRQD_AFFINITY_SET;
219 }
220
irqd_mark_affinity_was_set(struct irq_data * d)221 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
222 {
223 d->state_use_accessors |= IRQD_AFFINITY_SET;
224 }
225
irqd_get_trigger_type(struct irq_data * d)226 static inline u32 irqd_get_trigger_type(struct irq_data *d)
227 {
228 return d->state_use_accessors & IRQD_TRIGGER_MASK;
229 }
230
231 /*
232 * Must only be called inside irq_chip.irq_set_type() functions.
233 */
irqd_set_trigger_type(struct irq_data * d,u32 type)234 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
235 {
236 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
237 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
238 }
239
irqd_is_level_type(struct irq_data * d)240 static inline bool irqd_is_level_type(struct irq_data *d)
241 {
242 return d->state_use_accessors & IRQD_LEVEL;
243 }
244
irqd_is_wakeup_set(struct irq_data * d)245 static inline bool irqd_is_wakeup_set(struct irq_data *d)
246 {
247 return d->state_use_accessors & IRQD_WAKEUP_STATE;
248 }
249
irqd_can_move_in_process_context(struct irq_data * d)250 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
251 {
252 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
253 }
254
irqd_irq_disabled(struct irq_data * d)255 static inline bool irqd_irq_disabled(struct irq_data *d)
256 {
257 return d->state_use_accessors & IRQD_IRQ_DISABLED;
258 }
259
irqd_irq_masked(struct irq_data * d)260 static inline bool irqd_irq_masked(struct irq_data *d)
261 {
262 return d->state_use_accessors & IRQD_IRQ_MASKED;
263 }
264
irqd_irq_inprogress(struct irq_data * d)265 static inline bool irqd_irq_inprogress(struct irq_data *d)
266 {
267 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
268 }
269
irqd_is_wakeup_armed(struct irq_data * d)270 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
271 {
272 return d->state_use_accessors & IRQD_WAKEUP_ARMED;
273 }
274
275
276 /*
277 * Functions for chained handlers which can be enabled/disabled by the
278 * standard disable_irq/enable_irq calls. Must be called with
279 * irq_desc->lock held.
280 */
irqd_set_chained_irq_inprogress(struct irq_data * d)281 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
282 {
283 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
284 }
285
irqd_clr_chained_irq_inprogress(struct irq_data * d)286 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
287 {
288 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
289 }
290
irqd_to_hwirq(struct irq_data * d)291 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
292 {
293 return d->hwirq;
294 }
295
296 /**
297 * struct irq_chip - hardware interrupt chip descriptor
298 *
299 * @name: name for /proc/interrupts
300 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
301 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
302 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
303 * @irq_disable: disable the interrupt
304 * @irq_ack: start of a new interrupt
305 * @irq_mask: mask an interrupt source
306 * @irq_mask_ack: ack and mask an interrupt source
307 * @irq_unmask: unmask an interrupt source
308 * @irq_eoi: end of interrupt
309 * @irq_set_affinity: set the CPU affinity on SMP machines
310 * @irq_retrigger: resend an IRQ to the CPU
311 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
312 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
313 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
314 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
315 * @irq_cpu_online: configure an interrupt source for a secondary CPU
316 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
317 * @irq_suspend: function called from core code on suspend once per chip
318 * @irq_resume: function called from core code on resume once per chip
319 * @irq_pm_shutdown: function called from core code on shutdown once per chip
320 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
321 * @irq_print_chip: optional to print special chip info in show_interrupts
322 * @irq_request_resources: optional to request resources before calling
323 * any other callback related to this irq
324 * @irq_release_resources: optional to release resources acquired with
325 * irq_request_resources
326 * @irq_compose_msi_msg: optional to compose message content for MSI
327 * @irq_write_msi_msg: optional to write message content for MSI
328 * @irq_get_irqchip_state: return the internal state of an interrupt
329 * @irq_set_irqchip_state: set the internal state of a interrupt
330 * @flags: chip specific flags
331 */
332 struct irq_chip {
333 const char *name;
334 unsigned int (*irq_startup)(struct irq_data *data);
335 void (*irq_shutdown)(struct irq_data *data);
336 void (*irq_enable)(struct irq_data *data);
337 void (*irq_disable)(struct irq_data *data);
338
339 void (*irq_ack)(struct irq_data *data);
340 void (*irq_mask)(struct irq_data *data);
341 void (*irq_mask_ack)(struct irq_data *data);
342 void (*irq_unmask)(struct irq_data *data);
343 void (*irq_eoi)(struct irq_data *data);
344
345 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
346 int (*irq_retrigger)(struct irq_data *data);
347 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
348 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
349
350 void (*irq_bus_lock)(struct irq_data *data);
351 void (*irq_bus_sync_unlock)(struct irq_data *data);
352
353 void (*irq_cpu_online)(struct irq_data *data);
354 void (*irq_cpu_offline)(struct irq_data *data);
355
356 void (*irq_suspend)(struct irq_data *data);
357 void (*irq_resume)(struct irq_data *data);
358 void (*irq_pm_shutdown)(struct irq_data *data);
359
360 void (*irq_calc_mask)(struct irq_data *data);
361
362 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
363 int (*irq_request_resources)(struct irq_data *data);
364 void (*irq_release_resources)(struct irq_data *data);
365
366 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
367 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
368
369 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
370 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
371
372 unsigned long flags;
373 };
374
375 /*
376 * irq_chip specific flags
377 *
378 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
379 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
380 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
381 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
382 * when irq enabled
383 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
384 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
385 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
386 */
387 enum {
388 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
389 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
390 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
391 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
392 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
393 IRQCHIP_ONESHOT_SAFE = (1 << 5),
394 IRQCHIP_EOI_THREADED = (1 << 6),
395 };
396
397 /* This include will go away once we isolated irq_desc usage to core code */
398 #include <linux/irqdesc.h>
399
400 /*
401 * Pick up the arch-dependent methods:
402 */
403 #include <asm/hw_irq.h>
404
405 #ifndef NR_IRQS_LEGACY
406 # define NR_IRQS_LEGACY 0
407 #endif
408
409 #ifndef ARCH_IRQ_INIT_FLAGS
410 # define ARCH_IRQ_INIT_FLAGS 0
411 #endif
412
413 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
414
415 struct irqaction;
416 extern int setup_irq(unsigned int irq, struct irqaction *new);
417 extern void remove_irq(unsigned int irq, struct irqaction *act);
418 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
419 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
420
421 extern void irq_cpu_online(void);
422 extern void irq_cpu_offline(void);
423 extern int irq_set_affinity_locked(struct irq_data *data,
424 const struct cpumask *cpumask, bool force);
425
426 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
427 void irq_move_irq(struct irq_data *data);
428 void irq_move_masked_irq(struct irq_data *data);
429 #else
irq_move_irq(struct irq_data * data)430 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)431 static inline void irq_move_masked_irq(struct irq_data *data) { }
432 #endif
433
434 extern int no_irq_affinity;
435
436 #ifdef CONFIG_HARDIRQS_SW_RESEND
437 int irq_set_parent(int irq, int parent_irq);
438 #else
irq_set_parent(int irq,int parent_irq)439 static inline int irq_set_parent(int irq, int parent_irq)
440 {
441 return 0;
442 }
443 #endif
444
445 /*
446 * Built-in IRQ handlers for various IRQ types,
447 * callable via desc->handle_irq()
448 */
449 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
450 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
451 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
452 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
453 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
454 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
455 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
456 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
457 extern void handle_nested_irq(unsigned int irq);
458
459 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
460 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
461 extern void irq_chip_ack_parent(struct irq_data *data);
462 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
463 extern void irq_chip_mask_parent(struct irq_data *data);
464 extern void irq_chip_unmask_parent(struct irq_data *data);
465 extern void irq_chip_eoi_parent(struct irq_data *data);
466 extern int irq_chip_set_affinity_parent(struct irq_data *data,
467 const struct cpumask *dest,
468 bool force);
469 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
470 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
471 #endif
472
473 /* Handling of unhandled and spurious interrupts: */
474 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
475 irqreturn_t action_ret);
476
477
478 /* Enable/disable irq debugging output: */
479 extern int noirqdebug_setup(char *str);
480
481 /* Checks whether the interrupt can be requested by request_irq(): */
482 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
483
484 /* Dummy irq-chip implementations: */
485 extern struct irq_chip no_irq_chip;
486 extern struct irq_chip dummy_irq_chip;
487
488 extern void
489 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
490 irq_flow_handler_t handle, const char *name);
491
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)492 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
493 irq_flow_handler_t handle)
494 {
495 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
496 }
497
498 extern int irq_set_percpu_devid(unsigned int irq);
499
500 extern void
501 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
502 const char *name);
503
504 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)505 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
506 {
507 __irq_set_handler(irq, handle, 0, NULL);
508 }
509
510 /*
511 * Set a highlevel chained flow handler for a given IRQ.
512 * (a chained handler is automatically enabled and set to
513 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
514 */
515 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)516 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
517 {
518 __irq_set_handler(irq, handle, 1, NULL);
519 }
520
521 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
522
irq_set_status_flags(unsigned int irq,unsigned long set)523 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
524 {
525 irq_modify_status(irq, 0, set);
526 }
527
irq_clear_status_flags(unsigned int irq,unsigned long clr)528 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
529 {
530 irq_modify_status(irq, clr, 0);
531 }
532
irq_set_noprobe(unsigned int irq)533 static inline void irq_set_noprobe(unsigned int irq)
534 {
535 irq_modify_status(irq, 0, IRQ_NOPROBE);
536 }
537
irq_set_probe(unsigned int irq)538 static inline void irq_set_probe(unsigned int irq)
539 {
540 irq_modify_status(irq, IRQ_NOPROBE, 0);
541 }
542
irq_set_nothread(unsigned int irq)543 static inline void irq_set_nothread(unsigned int irq)
544 {
545 irq_modify_status(irq, 0, IRQ_NOTHREAD);
546 }
547
irq_set_thread(unsigned int irq)548 static inline void irq_set_thread(unsigned int irq)
549 {
550 irq_modify_status(irq, IRQ_NOTHREAD, 0);
551 }
552
irq_set_nested_thread(unsigned int irq,bool nest)553 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
554 {
555 if (nest)
556 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
557 else
558 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
559 }
560
irq_set_percpu_devid_flags(unsigned int irq)561 static inline void irq_set_percpu_devid_flags(unsigned int irq)
562 {
563 irq_set_status_flags(irq,
564 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
565 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
566 }
567
568 /* Set/get chip/data for an IRQ: */
569 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
570 extern int irq_set_handler_data(unsigned int irq, void *data);
571 extern int irq_set_chip_data(unsigned int irq, void *data);
572 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
573 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
574 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
575 struct msi_desc *entry);
576 extern struct irq_data *irq_get_irq_data(unsigned int irq);
577
irq_get_chip(unsigned int irq)578 static inline struct irq_chip *irq_get_chip(unsigned int irq)
579 {
580 struct irq_data *d = irq_get_irq_data(irq);
581 return d ? d->chip : NULL;
582 }
583
irq_data_get_irq_chip(struct irq_data * d)584 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
585 {
586 return d->chip;
587 }
588
irq_get_chip_data(unsigned int irq)589 static inline void *irq_get_chip_data(unsigned int irq)
590 {
591 struct irq_data *d = irq_get_irq_data(irq);
592 return d ? d->chip_data : NULL;
593 }
594
irq_data_get_irq_chip_data(struct irq_data * d)595 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
596 {
597 return d->chip_data;
598 }
599
irq_get_handler_data(unsigned int irq)600 static inline void *irq_get_handler_data(unsigned int irq)
601 {
602 struct irq_data *d = irq_get_irq_data(irq);
603 return d ? d->handler_data : NULL;
604 }
605
irq_data_get_irq_handler_data(struct irq_data * d)606 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
607 {
608 return d->handler_data;
609 }
610
irq_get_msi_desc(unsigned int irq)611 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
612 {
613 struct irq_data *d = irq_get_irq_data(irq);
614 return d ? d->msi_desc : NULL;
615 }
616
irq_data_get_msi(struct irq_data * d)617 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
618 {
619 return d->msi_desc;
620 }
621
irq_get_trigger_type(unsigned int irq)622 static inline u32 irq_get_trigger_type(unsigned int irq)
623 {
624 struct irq_data *d = irq_get_irq_data(irq);
625 return d ? irqd_get_trigger_type(d) : 0;
626 }
627
628 unsigned int arch_dynirq_lower_bound(unsigned int from);
629
630 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
631 struct module *owner);
632
633 /* use macros to avoid needing export.h for THIS_MODULE */
634 #define irq_alloc_descs(irq, from, cnt, node) \
635 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
636
637 #define irq_alloc_desc(node) \
638 irq_alloc_descs(-1, 0, 1, node)
639
640 #define irq_alloc_desc_at(at, node) \
641 irq_alloc_descs(at, at, 1, node)
642
643 #define irq_alloc_desc_from(from, node) \
644 irq_alloc_descs(-1, from, 1, node)
645
646 #define irq_alloc_descs_from(from, cnt, node) \
647 irq_alloc_descs(-1, from, cnt, node)
648
649 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)650 static inline void irq_free_desc(unsigned int irq)
651 {
652 irq_free_descs(irq, 1);
653 }
654
655 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
656 unsigned int irq_alloc_hwirqs(int cnt, int node);
irq_alloc_hwirq(int node)657 static inline unsigned int irq_alloc_hwirq(int node)
658 {
659 return irq_alloc_hwirqs(1, node);
660 }
661 void irq_free_hwirqs(unsigned int from, int cnt);
irq_free_hwirq(unsigned int irq)662 static inline void irq_free_hwirq(unsigned int irq)
663 {
664 return irq_free_hwirqs(irq, 1);
665 }
666 int arch_setup_hwirq(unsigned int irq, int node);
667 void arch_teardown_hwirq(unsigned int irq);
668 #endif
669
670 #ifdef CONFIG_GENERIC_IRQ_LEGACY
671 void irq_init_desc(unsigned int irq);
672 #endif
673
674 /**
675 * struct irq_chip_regs - register offsets for struct irq_gci
676 * @enable: Enable register offset to reg_base
677 * @disable: Disable register offset to reg_base
678 * @mask: Mask register offset to reg_base
679 * @ack: Ack register offset to reg_base
680 * @eoi: Eoi register offset to reg_base
681 * @type: Type configuration register offset to reg_base
682 * @polarity: Polarity configuration register offset to reg_base
683 */
684 struct irq_chip_regs {
685 unsigned long enable;
686 unsigned long disable;
687 unsigned long mask;
688 unsigned long ack;
689 unsigned long eoi;
690 unsigned long type;
691 unsigned long polarity;
692 };
693
694 /**
695 * struct irq_chip_type - Generic interrupt chip instance for a flow type
696 * @chip: The real interrupt chip which provides the callbacks
697 * @regs: Register offsets for this chip
698 * @handler: Flow handler associated with this chip
699 * @type: Chip can handle these flow types
700 * @mask_cache_priv: Cached mask register private to the chip type
701 * @mask_cache: Pointer to cached mask register
702 *
703 * A irq_generic_chip can have several instances of irq_chip_type when
704 * it requires different functions and register offsets for different
705 * flow types.
706 */
707 struct irq_chip_type {
708 struct irq_chip chip;
709 struct irq_chip_regs regs;
710 irq_flow_handler_t handler;
711 u32 type;
712 u32 mask_cache_priv;
713 u32 *mask_cache;
714 };
715
716 /**
717 * struct irq_chip_generic - Generic irq chip data structure
718 * @lock: Lock to protect register and cache data access
719 * @reg_base: Register base address (virtual)
720 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
721 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
722 * @irq_base: Interrupt base nr for this chip
723 * @irq_cnt: Number of interrupts handled by this chip
724 * @mask_cache: Cached mask register shared between all chip types
725 * @type_cache: Cached type register
726 * @polarity_cache: Cached polarity register
727 * @wake_enabled: Interrupt can wakeup from suspend
728 * @wake_active: Interrupt is marked as an wakeup from suspend source
729 * @num_ct: Number of available irq_chip_type instances (usually 1)
730 * @private: Private data for non generic chip callbacks
731 * @installed: bitfield to denote installed interrupts
732 * @unused: bitfield to denote unused interrupts
733 * @domain: irq domain pointer
734 * @list: List head for keeping track of instances
735 * @chip_types: Array of interrupt irq_chip_types
736 *
737 * Note, that irq_chip_generic can have multiple irq_chip_type
738 * implementations which can be associated to a particular irq line of
739 * an irq_chip_generic instance. That allows to share and protect
740 * state in an irq_chip_generic instance when we need to implement
741 * different flow mechanisms (level/edge) for it.
742 */
743 struct irq_chip_generic {
744 raw_spinlock_t lock;
745 void __iomem *reg_base;
746 u32 (*reg_readl)(void __iomem *addr);
747 void (*reg_writel)(u32 val, void __iomem *addr);
748 unsigned int irq_base;
749 unsigned int irq_cnt;
750 u32 mask_cache;
751 u32 type_cache;
752 u32 polarity_cache;
753 u32 wake_enabled;
754 u32 wake_active;
755 unsigned int num_ct;
756 void *private;
757 unsigned long installed;
758 unsigned long unused;
759 struct irq_domain *domain;
760 struct list_head list;
761 struct irq_chip_type chip_types[0];
762 };
763
764 /**
765 * enum irq_gc_flags - Initialization flags for generic irq chips
766 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
767 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
768 * irq chips which need to call irq_set_wake() on
769 * the parent irq. Usually GPIO implementations
770 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
771 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
772 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
773 */
774 enum irq_gc_flags {
775 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
776 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
777 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
778 IRQ_GC_NO_MASK = 1 << 3,
779 IRQ_GC_BE_IO = 1 << 4,
780 };
781
782 /*
783 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
784 * @irqs_per_chip: Number of interrupts per chip
785 * @num_chips: Number of chips
786 * @irq_flags_to_set: IRQ* flags to set on irq setup
787 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
788 * @gc_flags: Generic chip specific setup flags
789 * @gc: Array of pointers to generic interrupt chips
790 */
791 struct irq_domain_chip_generic {
792 unsigned int irqs_per_chip;
793 unsigned int num_chips;
794 unsigned int irq_flags_to_clear;
795 unsigned int irq_flags_to_set;
796 enum irq_gc_flags gc_flags;
797 struct irq_chip_generic *gc[0];
798 };
799
800 /* Generic chip callback functions */
801 void irq_gc_noop(struct irq_data *d);
802 void irq_gc_mask_disable_reg(struct irq_data *d);
803 void irq_gc_mask_set_bit(struct irq_data *d);
804 void irq_gc_mask_clr_bit(struct irq_data *d);
805 void irq_gc_unmask_enable_reg(struct irq_data *d);
806 void irq_gc_ack_set_bit(struct irq_data *d);
807 void irq_gc_ack_clr_bit(struct irq_data *d);
808 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
809 void irq_gc_eoi(struct irq_data *d);
810 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
811
812 /* Setup functions for irq_chip_generic */
813 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
814 irq_hw_number_t hw_irq);
815 struct irq_chip_generic *
816 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
817 void __iomem *reg_base, irq_flow_handler_t handler);
818 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
819 enum irq_gc_flags flags, unsigned int clr,
820 unsigned int set);
821 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
822 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
823 unsigned int clr, unsigned int set);
824
825 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
826 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
827 int num_ct, const char *name,
828 irq_flow_handler_t handler,
829 unsigned int clr, unsigned int set,
830 enum irq_gc_flags flags);
831
832
irq_data_get_chip_type(struct irq_data * d)833 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
834 {
835 return container_of(d->chip, struct irq_chip_type, chip);
836 }
837
838 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
839
840 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)841 static inline void irq_gc_lock(struct irq_chip_generic *gc)
842 {
843 raw_spin_lock(&gc->lock);
844 }
845
irq_gc_unlock(struct irq_chip_generic * gc)846 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
847 {
848 raw_spin_unlock(&gc->lock);
849 }
850 #else
irq_gc_lock(struct irq_chip_generic * gc)851 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)852 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
853 #endif
854
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)855 static inline void irq_reg_writel(struct irq_chip_generic *gc,
856 u32 val, int reg_offset)
857 {
858 if (gc->reg_writel)
859 gc->reg_writel(val, gc->reg_base + reg_offset);
860 else
861 writel(val, gc->reg_base + reg_offset);
862 }
863
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)864 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
865 int reg_offset)
866 {
867 if (gc->reg_readl)
868 return gc->reg_readl(gc->reg_base + reg_offset);
869 else
870 return readl(gc->reg_base + reg_offset);
871 }
872
873 #endif /* _LINUX_IRQ_H */
874